Semiconductor structure and method of fabricating the same
By setting an etching stop layer between the channel layer and the P-type semiconductor layer, the problem of channel layer damage caused by inaccurate etching depth control is solved, thereby improving carrier mobility and device performance, especially the performance of PMOS devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ENKRIS SEMICON
- Filing Date
- 2020-08-13
- Publication Date
- 2026-06-19
AI Technical Summary
The low carrier mobility in the channel of MOSFET devices manufactured using existing processes is due to the inability to accurately control the etching depth, which leads to damage to the channel layer surface.
An etch stop layer is set between the channel layer and the P-type semiconductor layer. A material with a different etch selectivity than the P-type semiconductor layer is selected to ensure that the etching process stops accurately at the etch stop layer, avoiding damage to the channel layer. P-type doped materials can be used to compensate for holes in the channel layer.
It improves the mobility of hole carriers in the channel of the semiconductor structure, thereby improving the yield and performance of the device, especially the performance of PMOS devices.
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Figure CN115812246B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.
[0003] The carrier mobility in the channel of MOSFET devices manufactured using existing processes is relatively low.
[0004] In view of this, it is necessary to provide a new semiconductor structure and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor structure and its fabrication method to improve the carrier mobility of the channel.
[0006] To achieve the above objectives, the present invention provides a semiconductor structure comprising:
[0007] Semiconductor substrate, back barrier layer, channel layer and etch stop layer distributed from bottom to top;
[0008] And a P-type semiconductor layer located on the source and drain regions of the etch stop layer.
[0009] Optionally, the material of the P-type semiconductor layer includes a group III nitride material.
[0010] Optionally, the material of the P-type semiconductor layer is GaN.
[0011] Optionally, the material of the etching termination layer includes at least one of AlN, AlGaN, GaN / AlGaN alternating multilayer superlattice structure, and AlGaN / AlN alternating multilayer superlattice structure.
[0012] Optionally, the material of the etching termination layer includes at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure.
[0013] Optionally, the channel layer comprises a group III nitride material.
[0014] Optionally, an anti-alloy scattering layer is provided between the back barrier layer and the channel layer.
[0015] Optionally, the P-type semiconductor layer of the source region has a source electrode, the P-type semiconductor layer of the drain region has a drain electrode, and the gate region of the etch stop layer has a stacked structure including a gate insulating layer and a gate.
[0016] Another aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:
[0017] A semiconductor substrate is provided, on which a back barrier layer, a channel layer, an etch stop layer and a P-type semiconductor layer are sequentially formed.
[0018] The P-type semiconductor layer in the gate region is etched away, while the P-type semiconductor layer in the source and drain regions is retained.
[0019] Optionally, the material of the P-type semiconductor layer includes a group III nitride material.
[0020] Optionally, the material of the P-type semiconductor layer is GaN.
[0021] Optionally, the material of the etching termination layer includes at least one of AlN, AlGaN, GaN / AlGaN alternating multilayer superlattice structure, and AlGaN / AlN alternating multilayer superlattice structure.
[0022] Optionally, the material of the etching termination layer includes at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure.
[0023] Optionally, the channel layer comprises a group III nitride material.
[0024] Optionally, an anti-alloy scattering layer is provided between the back barrier layer and the channel layer.
[0025] Optionally, the method for fabricating the semiconductor structure further includes: forming a source on the P-type semiconductor layer of the source region, forming a drain on the P-type semiconductor layer of the drain region, and forming a stacked structure including a gate insulating layer and a gate on the gate region of the etch stop layer.
[0026] Existing manufacturing processes result in low carrier mobility in the channel of MOSFET devices. The inventors' analysis revealed that this problem stems from the fact that during the formation of the gate insulating layer and the gate, the P-type semiconductor layer on the channel layer surface must be removed. However, the etching depth cannot be accurately controlled, meaning it's impossible to accurately etch to the interface between the P-type semiconductor layer and the channel layer. This causes damage to the channel layer surface, reducing carrier mobility in the channel. Based on this analysis, this invention forms an etch stop layer between the channel layer and the P-type semiconductor layer.
[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0028] 1) Due to the setting of the etch stop layer, when etching away the P-type semiconductor layer in the gate region, the etching can stop at the etch stop layer, which can accurately control the etching depth and avoid etch damage to the channel layer. This can improve the mobility of hole carriers in the channel of the semiconductor structure and improve the yield and performance of the device.
[0029] 2) In the optional scheme, the material of the etching stop layer includes at least one of p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure. In other words, the etching stop layer is a p-type doped material, which can not only prevent etching damage to the channel layer, but also compensate for holes in the channel layer and improve the performance of the PMOS device.
[0030] 3) In an optional scheme, an anti-alloy scattering layer is provided between the back barrier layer and the channel layer. The anti-alloy scattering layer can improve the mobility of hole carriers in the channel. Attached Figure Description
[0031] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention;
[0032] Figure 2 yes Figure 1 A schematic diagram of the intermediate structure corresponding to the process in the document;
[0033] Figure 3 This is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present invention;
[0034] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention;
[0035] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure according to the third embodiment of the present invention;
[0036] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention;
[0037] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention;
[0038] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention;
[0039] Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure according to the seventh embodiment of the present invention;
[0040] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention.
[0041] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:
[0042] Semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8; Semiconductor substrate 10
[0043] Back barrier layer 11a Channel layer 11b
[0044] Etching stop layer 12 P-type semiconductor layer 13
[0045] Gate 14a Source 14b
[0046] Drain 14c, Gate insulating layer 15
[0047] P-type ion heavily doped layer 16, nucleation layer 17a
[0048] Buffer layer 17b Anti-alloy scattering layer 18 Detailed Implementation
[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0050] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention; Figure 2 yes Figure 1 The diagram shows the intermediate structure corresponding to the process flow. Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure according to the first embodiment of the present invention.
[0051] First, refer to Figure 1 Step S1 and Figure 2 As shown, a semiconductor substrate 10 is provided, on which a back barrier layer 11a, a channel layer 11b, an etch stop layer 12 and a P-type semiconductor layer 13 are sequentially formed.
[0052] The semiconductor substrate 10 can be made of sapphire, silicon carbide, silicon, GaN, or diamond.
[0053] The back barrier layer 11a and the channel layer 11b form a heterojunction, and two-dimensional cavitation gas can be formed at the interface between the back barrier layer 11a and the channel layer 11b.
[0054] The materials of the back barrier layer 11a and / or the channel layer 11b may include group III nitride materials. Group III nitride materials may be at least one of GaN, AlGaN, InGaN, and AlInGaN. The formation process of the back barrier layer 11a and / or the channel layer 11b may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or combinations thereof.
[0055] In one alternative, the channel layer 11b is an unintentionally doped GaN layer.
[0056] It should be noted that in this embodiment, chemical elements represent a certain material, but the molar percentage of each chemical element in the material is not limited. For example, GaN material contains Ga and N elements, but the molar percentage of Ga and N elements is not limited; AlGaN material contains Al, Ga, and N elements, but the molar percentage of each element is not limited.
[0057] The material of the etching stop layer 12 can be selected from materials with a large difference in etching selectivity compared to the P-type semiconductor layer 13, such as aluminum-containing materials, specifically including at least one of AlN and AlGaN. Alternatively, the material of the etching stop layer 12 can be at least one of GaN / AlGaN alternating multilayer superlattice structure and AlGaN / AlN alternating multilayer superlattice structure.
[0058] The thickness of the etching stop layer 12 can range from 0.1 nm to 10 nm.
[0059] In some embodiments, the etch stop layer 12 can be a p-type doped material, such as at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure, to compensate for holes in the channel layer 11b.
[0060] The material of the P-type semiconductor layer 13 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN. The P-type dopant ions therein can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions, which can provide holes to the channel layer 11b. The concentration of the P-type dopant ions in the P-type semiconductor layer 13 is sufficient to enable conductivity between the source 14b and the drain 14c through the channel layer 11b.
[0061] The formation process of the P-type semiconductor layer 13 can refer to the formation process of the channel layer 11b. The dopant ions in the P-type semiconductor layer 13 can be achieved by in-situ doping.
[0062] Next, refer to Figure 1 Step S2 and Figure 3 As shown, the P-type semiconductor layer 13 of the gate region is etched away, while the P-type semiconductor layer 13 of the source and drain regions is retained.
[0063] The P-type semiconductor layer 13 can be etched using dry etching. Dry etching can be inductively coupled plasma etching (ICP). The etching gas can include Cl2 and BCl3.
[0064] Because of the etching stop layer 12, when removing the P-type semiconductor layer 13, the etching can be stopped at the etching stop layer 12, thus accurately controlling the etching depth and preventing etching damage to the channel layer 11b.
[0065] Figure 3 In the illustrated embodiment, only the P-type semiconductor layer 13 of the gate region is removed; in some embodiments, only the P-type semiconductor layer 13 of the source and drain regions may be retained, or the P-type semiconductor layer 13 of the source and drain regions and their adjacent regions may be retained. This embodiment does not limit this.
[0066] Then, refer to Figure 1 Step S3 and Figure 3 As shown, a source 14b is formed on the P-type semiconductor layer 13 in the source region, a drain 14c is formed on the P-type semiconductor layer 13 in the drain region, and a stacked structure including a gate insulating layer 15 and a gate 14a is formed on the gate region of the etch stop layer 12.
[0067] In step S3, an insulating layer, such as silicon dioxide, can be formed on the P-type semiconductor layer 13 and the etch stop layer 12 using physical vapor deposition or chemical vapor deposition. Then, the insulating layer outside the gate region is etched away to form the gate insulating layer 15. Next, a metal layer, such as Ti / Al / Ni / Au or Ni / Au, is formed by sputtering. The metal layer outside the gate region, source region, and drain region is etched away, and high-temperature annealing is performed to form ohmic contacts between the source 14b and the P-type semiconductor layer 13, and between the drain 14c and the P-type semiconductor layer 13.
[0068] When the material of the P-type semiconductor layer 13 is GaN, the source 14b can directly form an ohmic contact layer with the P-type semiconductor layer 13 and the drain 14c can directly form an ohmic contact layer with the P-type semiconductor layer 13, avoiding high-temperature annealing.
[0069] Reference Figure 3 As shown, the semiconductor structure 1 in this embodiment includes:
[0070] The semiconductor substrate 10, back barrier layer 11a, channel layer 11b and etch stop layer 12 are distributed from bottom to top.
[0071] P-type semiconductor layer 13 located on the source and drain regions of the etch stop layer 12;
[0072] The source 14b on the P-type semiconductor layer 13 in the source region, the drain 14c on the P-type semiconductor layer 13 in the drain region, and the stacked structure including the gate insulating layer 15 and the gate 14a on the gate region of the etch stop layer 12.
[0073] The semiconductor substrate 10 can be made of sapphire, silicon carbide, silicon, GaN, or diamond.
[0074] The back barrier layer 11a and the channel layer 11b form a heterojunction, and two-dimensional cavitation gas can be formed at the interface between the back barrier layer 11a and the channel layer 11b.
[0075] The materials of the back barrier layer 11a and / or the channel layer 11b may include group III nitride materials. The group III nitride material may be at least one of GaN, AlGaN, InGaN, and AlInGaN. In one alternative embodiment, the back barrier layer 11a is made of AlGaN, and the channel layer 11b is an unintentionally doped GaN layer. Typically, when GaN-based epitaxial materials are grown using MOCVD, due to defects such as nitrogen vacancies and oxygen doping, unintentionally doped intrinsic GaN has a high background electron concentration, thus exhibiting N-type conductivity.
[0076] The material of the etching stop layer 12 can be selected from materials with a large difference in etching selectivity compared to the p-type semiconductor layer 13. For example, it can include at least one of AlN, AlGaN, GaN / AlGaN alternating multilayer superlattice structure, and AlGaN / AlN alternating multilayer superlattice structure. The thickness of the etching stop layer 12 can range from 0.1 nm to 10 nm.
[0077] In some embodiments, the etch stop layer 12 can be a p-type doped material, such as at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure, to compensate for holes in the channel layer 11b.
[0078] The material of the P-type semiconductor layer 13 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN. The P-type doped ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions, which can provide holes to the channel layer 11b.
[0079] Ohmic contacts are formed between the source 14b and the P-type semiconductor layer 13, and between the drain 14c and the P-type semiconductor layer 13. The source 14b, drain 14c, and gate 14a can be made of metals, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au. The gate insulating layer 15 can be made of silicon dioxide.
[0080] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention.
[0081] Reference Figure 4 and Figure 3 As shown, the semiconductor structure 2 in this embodiment is largely the same as the semiconductor structure 1 in embodiment 1, except that the semiconductor structure 2 is an intermediate semiconductor structure and does not have a gate insulating layer 15, a gate 14a, a source 14b, and a drain 14c.
[0082] Correspondingly, the method for fabricating the semiconductor structure 2 in this embodiment is roughly the same as the method for fabricating the semiconductor structure 1 in embodiment 1, except that step S3 is omitted.
[0083] Semiconductor structure 2 can also be produced and sold as a semi-finished product.
[0084] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure according to the third embodiment of the present invention.
[0085] Reference Figure 5 and Figure 3As shown, the semiconductor structure 3 of this embodiment is largely the same as the semiconductor structure 1 of embodiment 1, except that: the P-type semiconductor layer 13 in the source region and the drain region has a P-type ion heavily doped layer 16.
[0086] The material of the p-type ion heavily doped layer 16 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the p-type dopant ion can be at least one of Mg ion, Zn ion, Ca ion, Sr ion, or Ba ion.
[0087] The p-type ion-doped layer 16 can provide more holes to participate in the conductivity of the channel layer 11b.
[0088] In the p-type ion heavily doped layer 16, the doping concentration can be greater than 1E19 / cm3 for different p-type ions.
[0089] The heavily doped p-type ion layer 16 can be formed using an epitaxial growth process. During the epitaxial growth process, the etching stop layer 12 can serve as a mask layer to prevent the formation of the heavily doped p-type ion layer 16 on it. The p-type dopant ions in the heavily doped p-type ion layer 16 can be achieved using an in-situ doping process.
[0090] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention.
[0091] Reference Figure 6 and Figure 5 As shown, the semiconductor structure 4 in this embodiment 4 is largely the same as the semiconductor structure 3 in embodiment 3, except that the semiconductor structure 4 is an intermediate semiconductor structure and does not have a gate insulating layer 15, a gate 14a, a source 14b, and a drain 14c.
[0092] Correspondingly, the method for fabricating the semiconductor structure 4 in this embodiment is largely the same as the method for fabricating the semiconductor structure 3 in embodiment 3, except that step S3 is omitted.
[0093] Semiconductor structure 4 can also be produced and sold as a semi-finished product.
[0094] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention.
[0095] Reference Figure 7 , Figure 3 and Figure 5 As shown, the semiconductor structure 5 and its fabrication method in this embodiment are largely the same as the semiconductor structures 1 and 3 and their fabrication methods in embodiments one and three, except that: there is a nucleation layer 17a and a buffer layer 17b between the back barrier layer 11a and the semiconductor substrate 10 from bottom to top.
[0096] The material of nucleation layer 17a can be, for example, AlN, AlGaN, etc., and the material of buffer layer 17b can include at least one of AlN, GaN, AlGaN, and AlInGaN. Nucleation layer 17a can alleviate the problems of lattice mismatch and thermal mismatch between epitaxially grown semiconductor layers, such as back barrier layer 11a, and semiconductor substrate 10, while buffer layer 17b can reduce the dislocation density and defect density of epitaxially grown semiconductor layers, thereby improving crystal quality.
[0097] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.
[0098] Reference Figure 8 and Figure 7 As shown, the semiconductor structure 6 in this embodiment 6 is largely the same as the semiconductor structure 5 in embodiment 5, except that the semiconductor structure 6 is an intermediate semiconductor structure and does not have a gate insulating layer 15, a gate 14a, a source 14b, and a drain 14c.
[0099] Correspondingly, the method for fabricating the semiconductor structure 6 in this embodiment is largely the same as the method for fabricating the semiconductor structure 5 in embodiment 5, except that step S3 is omitted.
[0100] Semiconductor structure 6 can also be produced and sold as a semi-finished product.
[0101] Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure according to the seventh embodiment of the present invention.
[0102] Reference Figure 9 , Figure 3 , Figure 5 and Figure 7 As shown, the semiconductor structure 7 and its fabrication method in this embodiment are largely the same as the semiconductor structures 1, 3, and 5 and their fabrication methods in embodiments 1, 3, and 5, with the only difference being that an anti-alloy scattering layer 18 is present between the back barrier layer 11a and the channel layer 11b.
[0103] The anti-alloy scattering layer 18 may be made of AlN. The anti-alloy scattering layer 18 can prevent alloy scattering, further improving the mobility of hole carriers. The thickness of the anti-alloy scattering layer 18 can range from 0.1 nm to 10 nm.
[0104] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention.
[0105] Reference Figure 10 and Figure 9As shown, the semiconductor structure 8 in this embodiment 8 is largely the same as the semiconductor structure 7 in embodiment 7, except that the semiconductor structure 8 is an intermediate semiconductor structure and does not have a gate insulating layer 15, a gate 14a, a source 14b, and a drain 14c.
[0106] Correspondingly, the method for fabricating the semiconductor structure 8 in this embodiment is largely the same as the method for fabricating the semiconductor structure 7 in embodiment 7, except that step S3 is omitted.
[0107] Semiconductor structure 8 can also be produced and sold as a semi-finished product.
[0108] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: A semiconductor substrate (10), a back barrier layer (11a), a channel layer (11b), and an etch stop layer (12) are distributed from bottom to top, wherein a two-dimensional hole gas is formed at the interface between the back barrier layer (11a) and the channel layer (11b), and the etch stop layer (12) is located above the two-dimensional hole gas. And a P-type semiconductor layer (13) located on the source region and drain region on the etch stop layer (12), wherein the P-type semiconductor layer (13) on the source region and drain region has a P-type ion heavily doped layer (16).
2. The semiconductor structure according to claim 1, characterized in that, The material of the P-type semiconductor layer (13) includes group III nitride materials.
3. The semiconductor structure according to claim 1, characterized in that, The material of the etching termination layer (12) includes at least one of AlN, AlGaN, GaN / AlGaN alternating multilayer superlattice structure, and AlGaN / AlN alternating multilayer superlattice structure.
4. The semiconductor structure according to claim 3, characterized in that, The material of the etching termination layer (12) includes at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure.
5. The semiconductor structure according to claim 1, characterized in that, The channel layer (11b) comprises a group III nitride material.
6. The semiconductor structure according to claim 1, characterized in that, The P-type ion heavily doped layer (16) of the source region has a source (14b), the P-type ion heavily doped layer (16) of the drain region has a drain (14c), and the gate region of the etch stop layer (12) has a stacked structure including a gate insulating layer (15) and a gate (14a).
7. The semiconductor structure according to claim 1, characterized in that, The etching stop layer (12) serves as a mask layer to prevent the formation of the P-type ion heavily doped layer (16) on the etching stop layer.
8. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate (10) is provided, on which a back barrier layer (11a), a channel layer (11b), an etch stop layer (12) and a P-type semiconductor layer (13) are sequentially formed, wherein a two-dimensional hole gas is formed at the interface between the back barrier layer (11a) and the channel layer (11b), and the etch stop layer (12) is located above the two-dimensional hole gas; The P-type semiconductor layer (13) of the gate region is etched away, while the P-type semiconductor layer (13) of the source region and the drain region is retained. The P-type semiconductor layer (13) of the source region and the drain region has a P-type ion heavily doped layer (16).
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The material of the etching termination layer (12) includes at least one of p-AlN, p-AlGaN, p-GaN / p-AlGaN alternating multilayer superlattice structure, and p-AlGaN / p-AlN alternating multilayer superlattice structure.
10. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The doped ions in the P-type semiconductor layer (13) are achieved through an in-situ doping process.