Circuits, methods, systems, and power chips for control enable signals

Abstract

Embodiments of the present application provide a circuit, a method, a system and a power chip for controlling an enable signal, wherein the circuit comprises a first type transistor, a second type transistor, a first pull-up circuit, an energy storage circuit and a stable power supply, a gate of the first type transistor receives an input signal of an input end of a target power chip, a drain of the first type transistor is connected with a gate of the second type transistor, and a source of the first type transistor is grounded; the energy storage circuit is connected in parallel with the first pull-up circuit, the first pull-up circuit is connected in parallel with the second type transistor, the energy storage circuit, the first pull-up circuit and the second type transistor are all connected with the stable power supply, and are used to receive a level signal transmitted by the stable power supply; a drain of the second type transistor is connected with an output end of the target power chip, and a source of the second type transistor is connected with the stable power supply. Through the present application, the problem that a lower voltage input at an input end of a higher-level power chip cannot meet the starting voltage of a lower-level power chip in the related art is solved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a circuit, method, system, and power chip for controlling an enable signal. Background Technology

[0002] In the current server field, CPUs, GPUs, integrated southbridges (Platform Controller Hub, PCH), hard drives, and other components all require various types of board-level DC power supplies. Common DC power supplies include electronic fuses, point-of-load (POL) power supplies, and low-dropout linear regulators (LDOs). Most of these DC power conversion chips require an enable signal input to produce a normal output voltage, and they all have specific sequential requirements. The enable signal is usually driven by the power good (PG) signal output from the previous stage of the DC power supply, or controlled by a CPLD (Complex Programmable Logic Device) chip, and is a crucial condition for the normal operation of this DC power supply. If the enable signal exhibits glitches, backtracking, or other waveform defects, it will cause the output of the next stage of the power supply to activate, affecting the timing of the entire circuit and potentially leading to system power failure and crashes. Therefore, controlling the monotonicity and delay of the enable signal is extremely important.

[0003] In related technologies, the PG signal of the previous stage power supply is used as the enable signal of this stage power supply. The PG signal of the previous stage is pulled up by its own output voltage or by an additional voltage. If the turn-on voltage threshold of this stage power supply chip is relatively high, and its turn-on voltage or drive voltage minimum value exceeds the upper limit of the PG signal and CPLD signal of the previous stage power supply, then this stage power supply chip cannot be turned on.

[0004] There is currently no effective solution to the problems mentioned above. Summary of the Invention

[0005] This application provides a circuit, method, system, and power chip for controlling an enable signal, to at least solve the problem in the related art that when a low voltage is input to the input terminal of the previous stage power chip, the turn-on voltage of the next stage power chip cannot be met.

[0006] According to one embodiment of this application, a circuit for controlling an enable signal is provided, comprising: a first type of transistor, a second type of transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply. The gate of the first type of transistor is used to receive an input signal from the input terminal of a target power supply chip. The drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded. The energy storage circuit is connected in parallel with the first pull-up circuit, and the first pull-up circuit is connected in parallel with the second type of transistor. The energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to the stable power supply to receive a level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power supply chip, and the source of the second type of transistor is connected to the stable power supply.

[0007] In one exemplary embodiment, the first type of transistor is in a cutoff state when the gate voltage of the first type of transistor is less than the cutoff voltage of the first type of transistor, and in a conduction state when the gate voltage of the first type of transistor is greater than or equal to the cutoff voltage of the first type of transistor.

[0008] In one exemplary embodiment, the second type of transistor is in the on state when the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, and in the off state when the gate voltage of the second type of transistor is greater than or equal to the cutoff voltage of the second type of transistor.

[0009] In one exemplary embodiment, when the gate of the first type of transistor does not receive an input signal transmitted from the input terminal, both the first type of transistor and the second type of transistor are in the off state, and the energy storage circuit is charged by the stable power supply.

[0010] In one exemplary embodiment, the energy storage circuit includes at least a first resistor and a first capacitor, which are connected in series.

[0011] In an exemplary embodiment, the source of the second type of transistor is connected to a stable power supply through a first current limiting circuit. The second type of transistor is connected in series with the first current limiting circuit and then in parallel with the first pull-up circuit.

[0012] In one exemplary embodiment, a second resistor is connected in parallel to the input terminal of the target power chip, with one end of the second resistor grounded, to stabilize the input signal at the input terminal.

[0013] In one exemplary embodiment, a second capacitor and a third resistor are connected in parallel at the output terminal of the target power chip, and one end of the second capacitor and the third resistor are grounded. The second capacitor and the third resistor are used to optimize the output signal of the target power chip.

[0014] In one exemplary embodiment, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

[0015] According to another embodiment of this application, a method for controlling an enable signal is provided, applied to the circuit for controlling the enable signal described above, comprising: receiving an input signal from an input terminal of a target power chip; turning on a first type of transistor when the input signal is greater than or equal to the cutoff voltage of a first type of transistor, wherein the gate of the first type of transistor is connected to the input terminal for receiving the input signal transmitted from the input terminal, the drain of the first type of transistor is connected to the gate of a second type of transistor, and the source of the first type of transistor is grounded; controlling an energy storage circuit to discharge while the first type of transistor is turned on, thereby reducing the gate voltage of the second type of transistor, wherein the energy storage circuit is connected in parallel with a first current limiting circuit, a first pull-up circuit is connected in parallel with the second type of transistor, the energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to a stable power supply for receiving a level signal transmitted from the stable power supply, the drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply; turning on the second type of transistor when the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, thereby transmitting the signal from the stable power supply to the output terminal.

[0016] According to another embodiment of this application, a power chip is also provided, which includes the circuitry for controlling the above-mentioned enable signal.

[0017] According to another embodiment of this application, a system for controlling an enable signal is also provided. The system includes a plurality of power chips and a control circuit connecting the power chips. The control circuit includes the circuit described above for controlling the enable signal.

[0018] This application utilizes a first-type transistor, a second-type transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply to process the input signal from the previous-stage power chip to the next-stage target power chip. The gate of the first-type transistor receives the input signal from the input terminal of the target power chip, the drain of the first-type transistor is connected to the gate of the second-type transistor, and the source of the first-type transistor is grounded. The energy storage circuit is connected in parallel with the first pull-up circuit, and the first pull-up circuit is connected in parallel with the second-type transistor. The energy storage circuit, the first pull-up circuit, and the second-type transistor are all connected to the stable power supply to receive the level signal transmitted by the stable power supply. The drain of the second-type transistor is connected to the output terminal of the target power chip, and the source of the second-type transistor is connected to the stable power supply. By controlling the enable signal through the above-mentioned circuit, the signal driving capability can be improved, and the time for the signal to reach the effective level can be extended. Therefore, the problem that the turn-on voltage of the next-stage power chip cannot be met when the input voltage of the previous-stage power chip is low can be solved, thus achieving the technical effect of ensuring the normal operation of the target power chip. Attached Figure Description

[0019] Figure 1 This is a circuit structure diagram of a control enable signal according to an embodiment of this application;

[0020] Figure 2 This is a flowchart of a method for controlling an enable signal according to an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] In the process of explaining the embodiments of this application, some nouns or terms appearing in the description shall be interpreted as follows:

[0024] The Central Processing Unit (CPU) is the core of a computer system for computation and control, and is the final execution unit for information processing and program execution.

[0025] A graphics processing unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor specifically designed for performing image and graphics-related computations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones).

[0026] NMOS transistor: The full name is N-Metal-Oxide-Semiconductor, meaning N-type metal-oxide-semiconductor. Transistors with this structure are called NMOS transistors. MOS transistors are divided into P-type MOS transistors and N-type MOS transistors. Integrated circuits composed of MOS transistors are called MOS integrated circuits. Circuits composed of NMOS transistors are called NMOS integrated circuits, circuits composed of PMOS transistors are called PMOS integrated circuits, and complementary MOS circuits composed of NMOS and PMOS transistors are called CMOS circuits.

[0027] In related technologies, the PG signal from the previous stage power supply is used as the enable signal for this stage power supply. The PG signal from the previous stage is pulled up by its own output voltage or by an additional voltage. After the turn-on level requirement is met, it is output to the enable terminal of the current stage power supply chip to drive the current stage power supply to turn on, or the CPLD output signal controls the current stage power supply to turn on. However, the above method of controlling the current stage power supply to turn on has the following drawbacks: 1) If the current stage power supply chip itself has a high turn-on voltage threshold, its minimum turn-on voltage or drive voltage exceeds the upper limit of the PG signal and CPLD signal from the previous stage power supply, and their driving capabilities are insufficient, then the current stage power supply chip cannot be directly driven by the above two signals. 2) If the enable signal is provided by another power supply that does not have a direct signal input relationship with the current stage power supply chip, then the power-on timing of the DC power supply cannot be guaranteed to be normal. The enable signal may reach a high level before or after the input voltage, which also poses a risk to the downstream load devices and the power system.

[0028] In order to solve the problems existing in the related technologies, the embodiments of this application provide corresponding solutions, which are described in detail below.

[0029] Figure 1 This is a circuit structure diagram of a control enable signal according to an embodiment of this application, such as... Figure 1 As shown, the circuit includes:

[0030] Type 1 transistor 101 (e.g.) Figure 1 Q1 in the second type of transistor 102 (e.g., Q1) Figure 1 Q2 in the first pull-up circuit 103 (e.g., Q2) Figure 1 R5 in the middle), energy storage circuit 104 (such as ... Figure 1 The circuit consisting of C1 and R1 connected in series) and the stable power supply 105 (such as Figure 1 In the 3V3 configuration, the gate of the first type of transistor is used to receive the input signal from the input terminal of the target power chip, the drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded; the energy storage circuit is connected in parallel with the first pull-up circuit, the first pull-up circuit is connected in parallel with the second type of transistor, and the energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to the stable power supply to receive the level signal transmitted by the stable power supply; the drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply.

[0031] In the embodiments of this application, the first type of transistor Q1 can be, for example, an NMOS transistor. The gate (G) of the NMOS transistor is connected to the input signal, which is also the input signal of the input terminal of the target power chip (referring to the current power chip or the power chip at this level). The drain (D) of the NMOS transistor is connected to the gate of the second type of transistor Q2, and the source (S) of the NMOS transistor is grounded.

[0032] In this embodiment, the second type of transistor Q2 can be, for example, a PMOS transistor, whose gate is connected to the drain of the first type of transistor Q1, and whose source is connected to a stable 3.3V power supply. In another optional embodiment, the source of the PMOS transistor is connected to a resistor (i.e., the first current-limiting circuit hereinafter referred to as the first current-limiting circuit). Figure 1 The middle finger (R2) is connected to the aforementioned stable power supply. The drain of this PMOS transistor is connected to the signal receiving terminal of the next stage power chip, that is, the drain of this PMOS transistor is connected to the output terminal of the target power chip.

[0033] In the circuit that controls the enable signal, the first type of transistor is in the off state when the gate voltage of the first type of transistor is less than the cutoff voltage of the first type of transistor, and in the on state when the gate voltage of the first type of transistor is greater than or equal to the cutoff voltage of the first type of transistor.

[0034] In the circuit that controls the enable signal, the second type of transistor is in the on state when the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, and in the off state when the gate voltage of the second type of transistor is greater than or equal to the cutoff voltage of the second type of transistor.

[0035] In the circuit that controls the enable signal, when the gate of the first type of transistor does not receive the input signal transmitted from the input terminal, both the first type of transistor and the second type of transistor are in the off state, and the energy storage circuit is charged by the stable power supply.

[0036] In the circuit that controls the enable signal, the energy storage circuit includes at least a first resistor 106 (e.g., Figure 1 R1) and the first capacitor 107 (as shown in the figure) Figure 1 In the first resistor and the first capacitor, C1 is connected in series.

[0037] In this embodiment of the application, at the input terminal of the target power chip (e.g. Figure 1 Before the input signal (INPUT) is received, the INPUT terminal is at a low level, the gate voltage of NMOS transistor Q1 is pulled low, transistor Q1 is turned off, and the stabilizing power supply (such as...) Figure 1 The 3V3 voltage in the circuit charges the first capacitor C1 through the first pull-up circuit (such as...). Figure 1 R5 in the circuit pulls the gate of the second transistor Q2 high. The gate of the PMOS transistor Q2 is pulled up to the same voltage as the stable power supply. For example, when the stable power supply outputs a voltage of 3.3V, the gate voltage of the PMOS transistor Q2 is also 3.3V. At this time, the PMOS transistor Q2 is also in the off state. The output terminal of the target power chip (such as...) Figure 1 The OUTPUT signal in the circuit does not output a signal. Meanwhile, the first capacitor C1 and the first resistor R1 form a simple energy storage circuit to stabilize the power supply (such as...) before the INPUT signal arrives. Figure 1 The 3V3 in the circuit charges the first capacitor C1 in the energy storage circuit.

[0038] When a stable voltage signal, such as 3.3V or lower, is input to the INPUT terminal, this signal will drive the first type transistor Q1 to turn on, that is, pull the gate of the first type transistor Q1 high. The gate voltage of the first type transistor Q1 is greater than the source voltage of the first type transistor Q1, making the drain and source of the first type transistor Q1 conduct. At the same time, the gate level of the second type transistor Q2 is pulled low. However, due to the presence of the energy storage circuit, the gate level of the second type transistor Q2 is not pulled low instantaneously, but gradually decreases as the first capacitor C1 slowly discharges. This causes the gate voltage of the second type transistor Q2 to gradually decrease from the same voltage as the stable power supply. For example, when the stable power supply is 3.3V, the gate voltage of the second type transistor Q2 gradually decreases from 3.3V to 0V, until the gate level of the second type transistor Q2 is lower than the threshold level (i.e., the cutoff voltage) of the second type transistor Q2, making the second type transistor Q2 conduct. The 3V3 signal output from the stable power supply is output through the second type transistor Q2 and reaches the OUTPUT terminal. This process achieves the goal of controlling the charging and discharging time of the capacitor by controlling its capacity, thereby further controlling the power-on time.

[0039] In the circuit that controls the enable signal, the source of the second type of transistor is connected to the stable power supply through the first current limiting circuit 108. The second type of transistor is connected in series with the first current limiting circuit and then in parallel with the first pull-up circuit.

[0040] In the circuit for controlling the enable signal mentioned above, a second resistor 109 (e.g., ...) is connected in parallel to the input terminal of the target power chip. Figure 1 R3 in the diagram, one end of the second resistor is grounded to stabilize the input signal at the input terminal.

[0041] In the circuit for controlling the enable signal mentioned above, the output terminal of the target power chip is connected in parallel with a second capacitor 110 (e.g., Figure 1 C2) and the third resistor 111 (as shown in the image) Figure 1In the R4 section, one end of the second capacitor and the third resistor are both grounded. The second capacitor and the third resistor are used to optimize the output signal of the target power chip.

[0042] In the circuit that controls the enable signal, the signal level is generally around 3.3V. However, due to the conversion of this circuit, a signal with a voltage lower than 3.3V can be received at the INPUT terminal, and the signal voltage only needs to be greater than the turn-on voltage of the first type transistor Q1 (that is, the cut-off voltage of the first type transistor mentioned above).

[0043] The control enable signal circuit provided in this application embodiment can receive a low voltage signal and generate a signal with the same output voltage as the stable power supply (generally 3.3V) through the switching of the transistor. This facilitates the design of the circuit for low voltage power supply and can add a certain delay and soft-start function to the processed signal, increasing the adjustability of the power-on time or timing.

[0044] The circuit for controlling the enable signal provided in this application uses a first type of transistor, a second type of transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply to process the input signal from the previous stage power chip to the next stage target power chip. The gate of the first type of transistor is used to receive the input signal from the input terminal of the target power chip, the drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded. The energy storage circuit is connected in parallel with the first pull-up circuit, and the first pull-up circuit is connected in parallel with the second type of transistor. The energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to the stable power supply to receive the level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply. The circuit for controlling the enable signal can improve the signal driving capability and extend the time for the signal to reach the effective level. Therefore, it can solve the problem that when the input voltage of the previous stage power chip is low, the turn-on voltage of the next stage power chip cannot be met. It achieves the technical effect of processing the previous stage PG signal or CPLD signal, extending the time for the signal to reach the effective level, ensuring the signal monotonicity and the normal operation of the target power chip.

[0045] Figure 2 This is a flowchart of a method for controlling an enable signal according to an embodiment of this application. The method is applied to the circuit for controlling the enable signal, such as... Figure 2 As shown, the method includes:

[0046] Step S202: Receive the input signal from the input terminal of the target power chip;

[0047] Step S204: When the input signal is greater than or equal to the cutoff voltage of the first type of transistor, the first type of transistor is turned on. The gate of the first type of transistor is connected to the input terminal to receive the input signal transmitted from the input terminal. The drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded.

[0048] Step S206: When the first type of transistor is turned on, the energy storage circuit is controlled to discharge, thereby reducing the gate voltage of the second type of transistor. The energy storage circuit is connected in parallel with the first current limiting circuit, and the first pull-up circuit is connected in parallel with the second type of transistor. The energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to the stable power supply to receive the level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply.

[0049] In step S208, when the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, the second type of transistor is turned on, so that the second type of transistor transmits the signal of the stable power supply to the output terminal.

[0050] The above steps solve the problem that the turn-on voltage of the next stage power chip cannot be met when the input voltage of the previous stage power chip is low, thus achieving the technical effect of ensuring the normal operation of the target power chip.

[0051] In the embodiments of this application, the first type of transistor Q1 can be, for example, an NMOS transistor. The gate (G) of the NMOS transistor is connected to the input signal, which is also the input signal of the input terminal of the target power chip (referring to the current power chip or the power chip at this level). The drain (D) of the NMOS transistor is connected to the gate of the second type of transistor Q2, and the source (S) of the NMOS transistor is grounded.

[0052] In this embodiment, the second type of transistor Q2 can be, for example, a PMOS transistor, whose gate is connected to the drain of the first type of transistor Q1, and whose source is connected to a stable 3.3V power supply. In another optional embodiment, the source of the PMOS transistor is connected to a resistor (i.e., the first current-limiting circuit hereinafter referred to as the first current-limiting circuit). Figure 1 The middle finger (R2) is connected to the aforementioned stable power supply. The drain of this PMOS transistor is connected to the signal receiving terminal of the next stage power chip, that is, the drain of this PMOS transistor is connected to the output terminal of the target power chip.

[0053] In the above method for controlling the enable signal, the first type of transistor is in the off state when the gate voltage of the first type of transistor is less than the cutoff voltage of the first type of transistor, and in the on state when the gate voltage of the first type of transistor is greater than or equal to the cutoff voltage of the first type of transistor.

[0054] In the above method for controlling the enable signal, the second type of transistor is in the on state when the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, and in the off state when the gate voltage of the second type of transistor is greater than or equal to the cutoff voltage of the second type of transistor.

[0055] In the above method for controlling the enable signal, when the gate of the first type of transistor does not receive the input signal transmitted from the input terminal, both the first type of transistor and the second type of transistor are in the off state, and the energy storage circuit is charged by the stable power supply.

[0056] In the above method for controlling the enable signal, the energy storage circuit includes at least a first resistor and a first capacitor, which are connected in series.

[0057] In this embodiment of the application, at the input terminal of the target power chip (e.g. Figure 1 Before the input signal (INPUT) is received, the INPUT terminal is at a low level, the gate voltage of NMOS transistor Q1 is pulled low, transistor Q1 is turned off, and the stabilizing power supply (such as...) Figure 1 The 3V3 voltage in the circuit charges the first capacitor C1 through the first pull-up circuit (such as...). Figure 1 R5 in the circuit pulls the gate of the second transistor Q2 high. The gate of the PMOS transistor Q2 is pulled up to the same voltage as the stable power supply. For example, when the stable power supply outputs a voltage of 3.3V, the gate voltage of the PMOS transistor Q2 is also 3.3V. At this time, the PMOS transistor Q2 is also in the off state. The output terminal of the target power chip (such as...) Figure 1 The OUTPUT function in the code does not output a signal. Meanwhile, Figure 1 The first capacitor C1 and the first resistor R1 form a simple energy storage circuit to stabilize the power supply (such as...) before the INPUT signal arrives. Figure 1 The 3V3 in the circuit charges the first capacitor C1 in the energy storage circuit.

[0058] When a stable voltage signal, such as 3.3V or lower, is input to the INPUT terminal, this signal will drive the first type transistor Q1 to turn on, that is, pull the gate of the first type transistor Q1 high. The gate voltage of the first type transistor Q1 is greater than the source voltage of the first type transistor Q1, making the drain and source of the first type transistor Q1 conduct. At the same time, the gate level of the second type transistor Q2 is pulled low. However, due to the presence of the energy storage circuit, the gate level of the second type transistor Q2 is not pulled low instantaneously, but gradually decreases as the first capacitor C1 slowly discharges. This causes the gate voltage of the second type transistor Q2 to gradually decrease from the same voltage as the stable power supply. For example, when the stable power supply is 3.3V, the gate voltage of the second type transistor Q2 gradually decreases from 3.3V to 0V, until the gate level of the second type transistor Q2 is lower than the threshold level (i.e., the cutoff voltage) of the second type transistor Q2, making the second type transistor Q2 conduct. The 3V3 signal output from the stable power supply is output through the second type transistor Q2 and reaches the OUTPUT terminal. This process achieves the goal of controlling the charging and discharging time of the capacitor by controlling its capacity, thereby further controlling the power-on time.

[0059] In the above method for controlling the enable signal, the source of the second type of transistor is connected to the stable power supply through the first current limiting circuit. The second type of transistor is connected in series with the first current limiting circuit and then in parallel with the first pull-up circuit.

[0060] In the above method for controlling the enable signal, a second resistor (such as...) is connected in parallel to the input terminal of the target power supply chip. Figure 1 R3 in the diagram, one end of the second resistor is grounded to stabilize the input signal at the input terminal.

[0061] In the above method for controlling the enable signal, a second capacitor (such as...) is connected in parallel to the output terminal of the target power chip. Figure 1 C2) and the third resistor (such as Figure 1 In the R4 section, one end of the second capacitor and the third resistor are both grounded. The second capacitor and the third resistor are used to optimize the output signal of the target power chip.

[0062] In the above method of controlling the enable signal, the signal level is generally around 3.3V. However, since this method realizes the circuit conversion, it can receive signals with voltages lower than 3.3V at the INPUT terminal, and the signal voltage only needs to be greater than the turn-on voltage of the first type transistor Q1 (that is, the cut-off voltage of the first type transistor mentioned above).

[0063] The method for controlling the enable signal provided in this application uses a first-type transistor, a second-type transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply to process the input signal from the previous-stage power chip to the next-stage target power chip, and receives the input signal from the input terminal of the target power chip; when the input signal is greater than or equal to the cutoff voltage of the first-type transistor, the first-type transistor is turned on, wherein the gate of the first-type transistor is connected to the input terminal for receiving the input signal transmitted from the input terminal, the drain of the first-type transistor is connected to the gate of the second-type transistor, and the source of the first-type transistor is grounded; in the first-type transistor... When the circuit is on, the energy storage circuit is discharged, causing the gate voltage of the second-type transistor to decrease. The energy storage circuit is connected in parallel with the first current-limiting circuit, and the first pull-up circuit is connected in parallel with the second-type transistor. The energy storage circuit, the first pull-up circuit, and the second-type transistor are all connected to a stable power supply to receive the level signal transmitted from the stable power supply. The drain of the second-type transistor is connected to the output terminal of the target power chip, and the source of the second-type transistor is connected to the stable power supply. When the gate voltage of the second-type transistor is lower than its cutoff voltage, the second-type transistor is turned on, allowing it to transmit the signal from the stable power supply to the output terminal. This circuit, which controls the enable signal, can improve the signal driving capability and extend the time for the signal to reach an effective level. Therefore, it can solve the problem that when a low voltage is input to the input terminal of the previous-stage power chip, the turn-on voltage of the next-stage power chip cannot be met. This achieves the technical effect of processing the previous-stage PG signal or CPLD signal, extending the time for the signal to reach an effective level, ensuring signal monotonicity, and maintaining the normal operation of the target power chip.

[0064] This application also provides a power chip that includes the aforementioned control enable signal circuit. In other words, the control enable signal circuit is integrated into the power chip. By using the integrated control enable signal circuit to transmit signals with other conventional power chips, the enable signal can be directly controlled without the need to set up a separate control enable signal circuit between power chips. This simplifies the connection lines between power chips. Therefore, the relevant explanations and descriptions of the control enable signal circuit described above also apply to this power chip, and will not be repeated here.

[0065] This application embodiment also provides a system for controlling an enable signal. The system includes multiple power chips and a control circuit connecting the power chips. The control circuit includes the aforementioned circuit for controlling the enable signal, specifically comprising: a first type of transistor, a second type of transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply. The gate of the first type of transistor is used to receive an input signal from the input terminal of the target power chip. The drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded. The energy storage circuit is connected in parallel with the first pull-up circuit, and the first pull-up circuit is connected in parallel with the second type of transistor. The energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to the stable power supply to receive the level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply.

[0066] In the embodiments of this application, the first type of transistor Q1 can be, for example, an NMOS transistor. The gate (G) of the NMOS transistor is connected to the input signal, which is also the input signal of the input terminal of the target power chip (referring to the current power chip or the power chip at this level). The drain (D) of the NMOS transistor is connected to the gate of the second type of transistor Q2, and the source (S) of the NMOS transistor is grounded.

[0067] In this embodiment, the second type of transistor Q2 can be, for example, a PMOS transistor, whose gate is connected to the drain of the first type of transistor Q1, and whose source is connected to a stable 3.3V power supply. In another optional embodiment, the source of the PMOS transistor is connected to a resistor (i.e., the first current-limiting circuit hereinafter referred to as the first current-limiting circuit). Figure 1 The middle finger (R2) is connected to the aforementioned stable power supply. The drain of this PMOS transistor is connected to the signal receiving terminal of the next stage power chip, that is, the drain of this PMOS transistor is connected to the output terminal of the target power chip.

[0068] In the system of the above-mentioned control enable signal, when the gate voltage of the first type of transistor is less than the cutoff voltage of the first type of transistor, the first type of transistor is in the off state, and when the gate voltage of the first type of transistor is greater than or equal to the cutoff voltage of the first type of transistor, the first type of transistor is in the on state.

[0069] In the system of the above-mentioned control enable signal, when the gate voltage of the second type transistor is less than the cutoff voltage of the second type transistor, the second type transistor is in the on state, and when the gate voltage of the second type transistor is greater than or equal to the cutoff voltage of the second type transistor, the second type transistor is in the off state.

[0070] In the system that controls the enable signal described above, when the gate of the first type of transistor does not receive the input signal transmitted from the input terminal, both the first type of transistor and the second type of transistor are in the off state, and the energy storage circuit is charged by the stable power supply.

[0071] In the system for controlling the enable signal described above, the energy storage circuit includes at least a first resistor and a first capacitor, which are connected in series.

[0072] In the above-mentioned control enable signal system, the source of the second type of transistor is connected to the stable power supply through the first current limiting circuit. The second type of transistor is connected in series with the first current limiting circuit and then in parallel with the first pull-up circuit.

[0073] In the aforementioned system for controlling the enable signal, a second resistor is connected in parallel to the input terminal of the target power chip, with one end of the second resistor grounded to stabilize the input signal at the input terminal.

[0074] In the aforementioned control enable signal system, a second capacitor and a third resistor are connected in parallel at the output terminal of the target power chip, with one end of each capacitor and resistor grounded. The second capacitor and the third resistor are used to optimize the output signal of the target power chip.

[0075] In this embodiment of the application, at the input terminal of the target power chip (e.g. Figure 1 Before the input signal (INPUT) is received, the INPUT terminal is at a low level, the gate voltage of NMOS transistor Q1 is pulled low, transistor Q1 is turned off, and the stabilizing power supply (such as...) Figure 1 The 3V3 voltage in the circuit charges the first capacitor C1 through the first pull-up circuit (such as...). Figure 1 R5 in the circuit pulls the gate of the second transistor Q2 high. The gate of the PMOS transistor Q2 is pulled up to the same voltage as the stable power supply. For example, when the stable power supply outputs a voltage of 3.3V, the gate voltage of the PMOS transistor Q2 is also 3.3V. At this time, the PMOS transistor Q2 is also in the off state. The output terminal of the target power chip (such as...) Figure 1 The OUTPUT in the circuit does not output a signal. Meanwhile, the first capacitor C1 and the first resistor R1 form a simple energy storage circuit (see...). Figure 1 The circuit in the middle), before the INPUT signal arrives, stabilizes the power supply (such as... Figure 1 The 3V3 in the circuit charges the first capacitor C1 in the energy storage circuit.

[0076] When a stable voltage signal, such as 3.3V or lower, is input to the INPUT terminal, this signal will drive the first type transistor Q1 to turn on, that is, pull the gate of the first type transistor Q1 high. The gate voltage of the first type transistor Q1 is greater than the source voltage of the first type transistor Q1, making the drain and source of the first type transistor Q1 conduct. At the same time, the gate level of the second type transistor Q2 is pulled low. However, due to the presence of the energy storage circuit, the gate level of the second type transistor Q2 is not pulled low instantaneously, but gradually decreases as the first capacitor C1 slowly discharges. This causes the gate voltage of the second type transistor Q2 to gradually decrease from the same voltage as the stable power supply. For example, when the stable power supply is 3.3V, the gate voltage of the second type transistor Q2 gradually decreases from 3.3V to 0V, until the gate level of the second type transistor Q2 is lower than the threshold level (i.e., the cutoff voltage) of the second type transistor Q2, making the second type transistor Q2 conduct. The 3V3 signal output from the stable power supply is output through the second type transistor Q2 and reaches the OUTPUT terminal. This process achieves the goal of controlling the charging and discharging time of the capacitor by controlling its capacity, thereby further controlling the power-on time.

[0077] The system for controlling the enable signal provided in this application embodiment can receive a low voltage signal and generate a signal with the same output voltage as the stable power supply (generally 3.3V) through the switching of the transistor. This facilitates the design of the circuit for low voltage power supply and can add a certain delay and soft-start function to the processed signal, increasing the adjustability of the power-on time or timing.

[0078] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0079] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0080] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular hardware and software combination.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A circuit for controlling an enable signal, characterized in that, include: The system comprises a first-class transistor, a second-class transistor, a first pull-up circuit, an energy storage circuit, and a stable power supply, wherein... The gate of the first type of transistor is used to receive the input signal from the input terminal of the target power chip, the drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded. The energy storage circuit is connected in parallel with the first pull-up circuit, the first pull-up circuit is connected in parallel with the second type of transistor, and the energy storage circuit, the first pull-up circuit and the second type of transistor are all connected to the stable power supply for receiving the level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply.

2. The circuit according to claim 1, characterized in that, When the gate voltage of the first type of transistor is less than the cutoff voltage of the first type of transistor, the first type of transistor is in the off state; when the gate voltage of the first type of transistor is greater than or equal to the cutoff voltage of the first type of transistor, the first type of transistor is in the on state.

3. The circuit according to claim 1, characterized in that, When the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, the second type of transistor is in the on state; when the gate voltage of the second type of transistor is greater than or equal to the cutoff voltage of the second type of transistor, the second type of transistor is in the off state.

4. The circuit according to claim 1, characterized in that, When the gate of the first type of transistor does not receive the input signal transmitted from the input terminal, both the first type of transistor and the second type of transistor are in the off state, and the energy storage circuit is charged by the stable power supply.

5. The circuit according to claim 1, characterized in that, The energy storage circuit includes at least a first resistor and a first capacitor, which are connected in series.

6. The circuit according to claim 1, characterized in that, The source of the second type of transistor is connected to the stable power supply through the first current limiting circuit. The second type of transistor is connected in series with the first current limiting circuit and then in parallel with the first pull-up circuit.

7. The circuit according to claim 1, characterized in that, A second resistor is connected in parallel to the input terminal of the target power chip, with one end of the second resistor grounded, to stabilize the input signal at the input terminal.

8. The circuit according to claim 1, characterized in that, A second capacitor and a third resistor are connected in parallel at the output terminal of the target power chip. One end of the second capacitor and the third resistor are both grounded. The second capacitor and the third resistor are used to optimize the output signal of the target power chip.

9. The circuit according to any one of claims 1 to 8, characterized in that, The first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

10. A method for controlling an enable signal, characterized in that, The circuit applied to the control enable signal according to any one of claims 1 to 9 comprises: Receive input signals from the input terminal of the target power chip; When the input signal is greater than or equal to the cutoff voltage of the first type of transistor, the first type of transistor is turned on, wherein the gate of the first type of transistor is connected to the input terminal for receiving the input signal transmitted by the input terminal, the drain of the first type of transistor is connected to the gate of the second type of transistor, and the source of the first type of transistor is grounded. When the first type of transistor is turned on, the energy storage circuit is controlled to discharge, thereby reducing the gate voltage of the second type of transistor. The energy storage circuit is connected in parallel with the first current limiting circuit, and the first pull-up circuit is connected in parallel with the second type of transistor. The energy storage circuit, the first pull-up circuit, and the second type of transistor are all connected to a stable power supply to receive the level signal transmitted by the stable power supply. The drain of the second type of transistor is connected to the output terminal of the target power chip, and the source of the second type of transistor is connected to the stable power supply. When the gate voltage of the second type of transistor is less than the cutoff voltage of the second type of transistor, the second type of transistor is turned on, so that the second type of transistor transmits the signal of the stable power supply to the output terminal.

11. A power supply chip, characterized in that, The power chip includes the circuitry for the control enable signal as described in any one of claims 1 to 9.

12. A system for controlling an enable signal, characterized in that, The system includes multiple power chips and a control circuit connecting the power chips, the control circuit including the control enable signal as described in any one of claims 1 to 9.

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