Task synchronization method and apparatus

Abstract

The application provides a task synchronization method and device, and relates to the field of integrated circuits. The application obtains time deviations of multiple subsystems in an SOC chip from a common time latching unit; in response to a requirement of synchronously executing a target task by the multiple subsystems, a target time corresponding to the target task is obtained; for each subsystem, a task execution time of the target task corresponding to the subsystem is determined based on the target time and the time deviation of the subsystem; and the subsystem is controlled to execute the target task at the task execution time. In the application, the time deviations of the multiple subsystems from the common time latching unit can be obtained, and when task synchronization between the subsystems is required, the task execution times of the tasks of the multiple subsystems can be obtained, thereby effectively solving the problem of SOC cross-system time information synchronization, ensuring stable operation of the chip, not requiring additional time synchronization related special tasks, and reducing the operation burden of the CPU.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a task synchronization method and apparatus thereof. Background Technology

[0002] In related technologies, the time information between various subsystems in a system-on-a-chip (SOC) is synchronized by software. This can easily lead to inaccurate synchronization information. When communication or information sharing is required between subsystems, it may not be able to be completed effectively, and additional CPU resources are required, affecting the stable operation of the chip. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, one objective of this application is to propose a task synchronization method, which involves obtaining the time deviation between each of the multiple subsystems in a SOC chip and a common time latch unit; in response to the need for multiple subsystems to execute a target task synchronously, obtaining the target time corresponding to the target task; for each subsystem, determining the task execution time of the target task corresponding to the subsystem based on the target time and the time deviation of the subsystem; and controlling the subsystem to execute the target task at the task execution time.

[0005] The second objective of this application is to propose a task synchronization device.

[0006] The third objective of this application is to propose an electronic device.

[0007] The fourth objective of this application is to provide a computer storage medium.

[0008] The fifth objective of this application is to provide a computer program product.

[0009] To achieve the above objectives, the first aspect of this application proposes a task synchronization method, comprising: acquiring the time deviation between each of multiple subsystems in a SOC chip and a common time latch unit; in response to the need for multiple subsystems to synchronously execute a target task, acquiring the target time corresponding to the target task; for each subsystem, determining the task execution time of the target task corresponding to the subsystem based on the target time and the time deviation of the subsystem; and controlling the subsystem to execute the target task at the task execution time.

[0010] In this application, the time deviation between each subsystem and the common time latch unit can be obtained. When task synchronization between subsystems is required, the task execution time of each subsystem task can be obtained, which effectively solves the problem of cross-system time information synchronization of SOC, ensures stable chip operation, eliminates the need for additional time synchronization-related dedicated tasks, and reduces the CPU's operating burden.

[0011] According to one embodiment of this application, determining the task execution time of the target task corresponding to the subsystem based on the time deviation between the target time and the subsystem includes: for any subsystem, obtaining the sum of the time deviations between the target time and the subsystem; and determining the task execution time of the subsystem based on the sum.

[0012] According to one embodiment of this application, obtaining the time deviation between each of the multiple subsystems in a SOC chip and a common time latch unit includes: receiving time latch signals sent by each subsystem in the SOC chip at startup, and synchronously obtaining a first moment when the common time latch unit receives the time latch signals; parsing the time latch signals to obtain a second moment when the subsystem starts up; and determining the time deviation based on the first moment and the second moment.

[0013] According to one embodiment of this application, after receiving the time latch signals sent by each subsystem in the SOC chip at startup, the method further includes: buffering the time latch signals; and parsing the time latch signals, including: retrieving the time latch signals from the buffer and parsing the time latch signals.

[0014] According to one embodiment of this application, buffering a time latch signal includes: determining the latch register corresponding to the subsystem based on the subsystem identifier of the time latch signal; and registering the time latch signal in the corresponding latch register.

[0015] According to one embodiment of this application, the task synchronization method further includes: reacquiring the time deviation between the subsystem and the common time latch unit at set intervals.

[0016] To achieve the above objectives, a second aspect of this application provides a task synchronization device, comprising: a first acquisition module for acquiring the time deviation between each of multiple subsystems in a SOC chip and a common time latch unit; a second acquisition module for acquiring the target time corresponding to the target task in response to the need for multiple subsystems to synchronously execute a target task; a determination module for determining, for each subsystem, the task execution time of the target task corresponding to the subsystem based on the target time and the time deviation of the subsystem; and a control module for controlling the subsystems to execute the target task at the task execution time.

[0017] According to one embodiment of this application, the determining module is further configured to: for any subsystem, obtain the sum of the time deviations between the target time and the time deviations corresponding to the subsystem; and determine the task execution time of the subsystem based on the sum.

[0018] According to one embodiment of this application, the first acquisition module is further configured to: receive time latch signals sent by each subsystem in the SOC chip at startup, and synchronously acquire the first moment when the common time latch unit receives the time latch signals; parse the time latch signals to acquire the second moment when the subsystem starts up; and determine the time deviation based on the first moment and the second moment.

[0019] According to one embodiment of this application, the first acquisition module is further configured to: buffer the time latch signal; parse the time latch signal, including: acquiring the time latch signal from the buffer and parsing the time latch signal.

[0020] According to one embodiment of this application, the first acquisition module is further configured to: determine the latch register corresponding to the subsystem based on the subsystem identifier of the time latch signal; and register the time latch signal into the corresponding latch register.

[0021] According to one embodiment of this application, the task synchronization device further includes: a third acquisition module, used to reacquire the time deviation between the subsystem and the common time latch unit at set intervals.

[0022] To achieve the above objectives, a third aspect of this application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to implement the task synchronization method as described in the first aspect of this application.

[0023] To achieve the above objectives, a fourth aspect of this application provides a computer storage medium storing computer instructions for instructing a computer to perform a task synchronization method as described in the first aspect of this application.

[0024] To achieve the above objectives, a fifth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the task synchronization method as described in the first aspect of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 This is a schematic diagram illustrating a task synchronization method according to one embodiment of this application.

[0027] Figure 2 This is a schematic diagram illustrating an embodiment of the present application of obtaining the time deviation between each of the multiple subsystems in a SOC chip and the common time latch unit.

[0028] Figure 3 This is a signal diagram illustrating the various subsystems and common time latch unit in a SOC chip according to one embodiment of this application.

[0029] Figure 4 This is a general flowchart illustrating a task synchronization method according to one embodiment of this application.

[0030] Figure 5 This is a schematic diagram of a task synchronization device shown in one embodiment of this application.

[0031] Figure 6 This is a schematic diagram of an electronic device according to one embodiment of this application. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0033] Figure 1 This is an exemplary implementation of a task synchronization method proposed in this application, such as... Figure 1 As shown, the task synchronization method includes:

[0034] S101, obtain the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit.

[0035] A System-on-Chip (SOC), also known as a system-on-a-chip, is a product, an integrated circuit with a specific purpose, containing a complete system and embedded software. Large and complex SOC chips contain many complex and functionally independent subsystems. Each subsystem operates independently, and its system time may not be completely consistent with standard time. When cross-system information exchange or synchronization tasks are required, the time information of each task needs to be obtained to enable the subsystems to coordinate and complete their work.

[0036] In this application, a common time latch unit is set in the common area of ​​the SOC chip to obtain the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit. In implementation, a specific counter circuit is introduced into each subsystem, and the same counter circuit is also introduced into the common time latch unit of the SOC. The counter circuits are designed to support mutual locking of time information. Each subsystem can lock the time information of its own counter circuit and send a time latch signal to the common time latch unit. Upon receiving the time latch signal, the common time latch unit locks the time information of its own counter circuit. Through these two sets of one-to-one locked time information, the time deviation between each subsystem in the SOC chip and the common time latch unit can be obtained.

[0037] It is important to note that there is no delay between the subsystem sending a time latch signal to the common time latch unit and the common time latch unit locking its own counter circuit's time information upon receiving the time latch signal. In other words, the time deviation between the subsystem and the common time latch unit is the system time difference between them at the same instant. For example, if a subsystem locks in time information of 23:59:55, while the common time latch unit locks in time information of 00:00:00, then the time deviation between the subsystem and the common time latch unit is considered to be -5 seconds.

[0038] S102, in response to the need for multiple subsystems to execute the target task synchronously, obtain the target time corresponding to the target task.

[0039] In a System-on-a-Chip (SoC) chip, some tasks require simultaneous execution by multiple subsystems. For example, information interaction tasks that need to be executed synchronously are designated as target tasks, and their corresponding execution times are designated as target times. For instance, if multiple subsystems of the SoC chip need to simultaneously execute task A at 8:00:00, then task A is the target task, and 8:00:00 corresponding to task A is designated as the target time. It is important to note that the target time refers to the time indicated by the counter circuit of the common time latch unit. In this application, the system time of the common time latch unit is used as the standard time.

[0040] S103, for each subsystem, determine the task execution time of the target task corresponding to the subsystem based on the time deviation between the target time and the subsystem.

[0041] Based on the time deviation between each subsystem and the common time latch unit obtained above, and the target time corresponding to the target task, the task execution time of the target task corresponding to each subsystem is determined. Specifically, for each subsystem, the sum of the target time of the target task and the time deviation between that subsystem and the common time latch unit is obtained, and the task execution time of that subsystem is determined based on this sum. Here, the task execution time refers to the time indicated by the counter circuit of the subsystem.

[0042] For example, if the target task requires three subsystems to execute simultaneously, namely subsystem 1, subsystem 2 and subsystem 3, and the target time of the target task is 8:00:00, and the time deviation of subsystem 1 from the common time latch unit is -6 seconds, then the sum of the target time of the target task 8:00:00 and the time deviation of subsystem 1 from the common time latch unit -6 seconds is 07:59:54. Then the task execution time of subsystem 1 is determined to be the time when subsystem 1's own time is 07:59:54.

[0043] For example, if the target time of the target task is 8:00:00, and the time deviation between subsystem 2 and the common time latch unit is 3 seconds, then the sum of the target time of the target task 8:00:00 and the time deviation of subsystem 2 from the common time latch unit is 3 seconds, then the task execution time of subsystem 2 is determined to be the time when subsystem 2 itself is 8:00:03.

[0044] For example, if the target time of the target task is 8:00:00, and the time deviation between subsystem 3 and the common time latch unit is 0 seconds, then the sum of the target time of the target task 8:00:00 and the time deviation of subsystem 3 from the common time latch unit is 0 seconds is obtained as 8:00:00. Then the task execution time of subsystem 3 is determined to be the time when subsystem 3 itself is 8:00:00.

[0045] S104, the control subsystem executes the target task at the task execution time.

[0046] When multiple subsystems need to execute a target task synchronously, based on the task execution time of the target task corresponding to each subsystem obtained above, each subsystem is controlled to execute the target task at its corresponding task execution time. For example, if the task execution time of subsystem 1 is 07:59:54, then subsystem 1 is controlled to start executing the target task when its counter circuit reaches 07:59:54; if the task execution time of subsystem 2 is 8:00:03, then subsystem 2 is controlled to start executing the target task when its counter circuit reaches 8:00:03; if the task execution time of subsystem 3 is 8:00:00, then subsystem 3 is controlled to start executing the target task when its counter circuit reaches 8:00:00.

[0047] It should be noted that, since the time of each subsystem is not completely consistent with the standard time, the system time of some subsystems may be earlier than the standard time, and the system time of some subsystems may be later than the standard time. Therefore, although the system time of the target tasks executed by these three subsystems may appear to be inconsistent, they are actually the same standard time.

[0048] This application proposes a task synchronization method. It involves obtaining the time deviation between each subsystem in a System-on-a-Chip (SoC) and a common time latch unit; in response to the need for multiple subsystems to synchronously execute a target task, obtaining the target time corresponding to the target task; for each subsystem, determining the task execution time of the target task corresponding to that subsystem based on the target time and the subsystem's time deviation; and controlling the subsystem to execute the target task at the task execution time. This method obtains the time deviation between each subsystem and the common time latch unit. When task synchronization between subsystems is required, the task execution time of each subsystem's task can be obtained, effectively solving the problem of cross-system time information synchronization in an SoC, ensuring stable chip operation, eliminating the need for additional time synchronization-related dedicated tasks, and reducing the CPU's workload.

[0049] Furthermore, in addition to locking time information with the common time latch unit, each subsystem can also lock time information with each other to obtain the system time difference between multiple subsystems.

[0050] Figure 2 This is an exemplary implementation of a task synchronization method proposed in this application, such as... Figure 2 As shown, based on the above embodiments, the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit is obtained, including:

[0051] S201 receives the time latch signals sent by each subsystem in the SOC chip during startup, and synchronously acquires the first moment when the common time latch unit receives the time latch signal.

[0052] Figure 3 This is a signal diagram illustrating the various subsystems and common time latch unit within a SOC chip, such as... Figure 3 As shown, each subsystem in the SOC chip sends a time latch signal to the common time latch unit during startup. The common time latch unit receives the time latch signals sent by each subsystem during startup and synchronously acquires the first moment when the common time latch unit receives the time latch signal. After receiving the time latch signals sent by each subsystem during startup, the common time latch unit also needs to determine the corresponding latch register for each subsystem based on the subsystem identifier of the time latch signal, and then register the time latch signal in the corresponding latch register to buffer the time latch signal.

[0053] like Figure 3 As shown, if subsystem 0 needs to perform a synchronization task, subsystem 0 sends a time latch signal 0. After receiving the time latch signal 0, the common time latch unit locks the time information of its own counter circuit as the first moment and buffers the time latch signal 0 in the latch register 0.

[0054] Similarly, if subsystem 1 needs to perform a synchronization task, subsystem 1 sends time latch signal 1. After receiving time latch signal 1, the common time latch unit locks the time information of its own counter circuit as the first moment and buffers time latch signal 1 in latch register 1.

[0055] The interaction process between other subsystems and the common time latch unit is similar to the interaction process between subsystem 0 or subsystem 1 and the common time latch unit.

[0056] S202, parse the time latch signal to obtain the second moment when the subsystem starts.

[0057] The time latch signal sent by the subsystem contains the time information of the subsystem's counter circuit at the time the time latch signal is sent. The time latch signal is retrieved from the buffer of the common time latch unit, and the time latch signal received by the common time latch unit is parsed to obtain the second moment when the subsystem starts.

[0058] S203, determine the time deviation based on the first and second time points.

[0059] Based on the first and second time points obtained above, the time deviations between each of the multiple subsystems in the SOC chip and the common time latch unit are determined. The time deviation is the difference between the second time point and the first time point.

[0060] For example, if the first time of the common time latch unit corresponding to subsystem 1 is 8:00:00, and the second time that subsystem 1 itself latches is 07:59:56, then the time deviation is -4 seconds.

[0061] For example, if the first time of the common time latch unit corresponding to subsystem 2 is 8:00:00, and the second time of the time latched by subsystem 2 itself is 8:00:00, then the time deviation is 0 seconds.

[0062] For example, if the first time of the common time latch unit corresponding to subsystem 3 is 8:00:00, and the second time of the time latched by subsystem 3 itself is 8:00:06, then the time deviation is 6 seconds.

[0063] This application embodiment receives the time latch signals sent by each subsystem in the SOC chip at startup, and synchronously obtains the first moment when the common time latch unit receives the time latch signal. The time latch signal is parsed to obtain the second moment when the subsystem starts up. Based on the first and second moments, a more accurate time deviation is determined, ensuring that when task synchronization is required between subsystems in the future, the task execution time of each subsystem task can be obtained, effectively solving the problem of cross-system time information synchronization in SOC.

[0064] Figure 4 This is an exemplary implementation of a task synchronization method proposed in this application, such as... Figure 4 As shown, the task synchronization method includes:

[0065] S401 receives the time latch signals sent by each subsystem in the SOC chip during startup, and synchronously acquires the first moment when the common time latch unit receives the time latch signal.

[0066] S402 parses the time latch signal to obtain the second moment when the subsystem starts.

[0067] S403, determine the time deviation based on the first and second time points.

[0068] The implementation methods of steps S401 to S403 can be referred to the description of the corresponding parts in the above embodiments, and will not be repeated here.

[0069] S404, in response to the need for multiple subsystems to execute a target task synchronously, obtains the target time corresponding to the target task.

[0070] S405: For any subsystem, obtain the sum of the time deviations between the target time and the corresponding time of the subsystem.

[0071] S406, based on the sum, determines the task execution time of the subsystem.

[0072] S407, the control subsystem executes the target task at the task execution time.

[0073] The implementation methods of steps S404 to S407 can be referred to the description of the corresponding parts in the above embodiments, and will not be repeated here.

[0074] This application proposes a task synchronization method. It involves obtaining the time deviation between each subsystem in a System-on-a-Chip (SoC) and a common time latch unit; in response to the need for multiple subsystems to synchronously execute a target task, obtaining the target time corresponding to the target task; for each subsystem, determining the task execution time of the target task corresponding to that subsystem based on the target time and the subsystem's time deviation; and controlling the subsystem to execute the target task at the task execution time. This method obtains the time deviation between each subsystem and the common time latch unit. When task synchronization between subsystems is required, the task execution time of each subsystem's task can be obtained, effectively solving the problem of cross-system time information synchronization in an SoC, ensuring stable chip operation, eliminating the need for additional time synchronization-related dedicated tasks, and reducing the CPU's workload.

[0075] Figure 5 This is a schematic diagram of a task synchronization device proposed in this application, such as... Figure 5 As shown, the task synchronization device 500 includes a first acquisition module 51, a second acquisition module 52, a determination module 53, and a control module 54, wherein:

[0076] The first acquisition module 51 is used to acquire the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit.

[0077] The second acquisition module 52 is used to acquire the target time corresponding to the target task in response to the need for multiple subsystems to execute the target task synchronously.

[0078] The determination module 53 is used to determine the task execution time of the target task corresponding to each subsystem based on the target time and the time deviation of the subsystem.

[0079] The control module 54 is used to control the subsystem to execute the target task at the time of task execution.

[0080] Furthermore, the determining module 53 is also used to: for any subsystem, obtain the sum of the time deviations between the target time and the time deviations corresponding to the subsystem; and determine the task execution time of the subsystem based on the sum.

[0081] Furthermore, the first acquisition module 51 is also used to: receive the time latch signals sent by each subsystem in the SOC chip at startup, and synchronously acquire the first moment when the common time latch unit receives the time latch signals; parse the time latch signals to acquire the second moment when the subsystem starts up; and determine the time deviation based on the first moment and the second moment.

[0082] Furthermore, the first acquisition module 51 is also used to: buffer the time latch signal; parse the time latch signal, including: acquiring the time latch signal from the buffer and parsing the time latch signal.

[0083] Furthermore, the first acquisition module 51 is also used to: determine the latch register corresponding to the subsystem based on the subsystem identifier of the time latch signal; and register the time latch signal into the corresponding latch register.

[0084] Furthermore, the task synchronization device 500 also includes a third acquisition module 55, used to reacquire the time deviation between the subsystem and the common time latch unit at set intervals.

[0085] To implement the above embodiments, this application also proposes an electronic device 600, such as... Figure 6 As shown, the electronic device 600 includes a processor 601 and a memory 602 communicatively connected to the processor. The memory 602 stores instructions that can be executed by at least one processor. The instructions are executed by at least one processor 601 to implement the task synchronization method as shown in the above embodiment.

[0086] To implement the above embodiments, this application also proposes a computer storage medium storing computer instructions for instructing a computer to execute the task synchronization method shown in the above embodiments.

[0087] To implement the above embodiments, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements the task synchronization method shown in the above embodiments.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0089] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0090] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A task synchronization method, characterized in that, include: Receive the time latch signals sent by each subsystem in the SOC chip at startup, and synchronously acquire the first moment when the common time latch unit receives the time latch signals; The time latch signal is parsed to obtain the second moment when the subsystem starts up; Based on the first time point and the second time point, the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit is determined; In response to the need for multiple subsystems to execute a target task synchronously, the target time corresponding to the target task is obtained; For each subsystem, the task execution time of the target task corresponding to the subsystem is determined based on the time deviation between the target time and the subsystem. The control subsystem executes the target task at the time of task execution.

2. The method according to claim 1, characterized in that, Determining the task execution time of the target task corresponding to the subsystem based on the time deviation between the target time and the subsystem includes: For any of the subsystems, obtain the sum of the time deviations between the target time and the time deviations corresponding to the subsystem; Based on the sum, the task execution time of the subsystem is determined.

3. The method according to claim 1, characterized in that, After receiving the time-latch signals sent by each subsystem in the SOC chip during startup, the method further includes: The time-latched signal is buffered; The parsing of the time-latched signal includes: The time latch signal is obtained from the cache and then parsed.

4. The method according to claim 3, characterized in that, The buffering of the time-latched signal includes: Based on the subsystem identifier of the time latch signal, determine the latch register corresponding to the subsystem; The time latch signal is registered to the corresponding latch register.

5. The method according to claim 1, characterized in that, Also includes: The time deviation between the subsystem and the common time latch unit is reacquired at set intervals.

6. A task synchronization device, characterized in that, include: The first acquisition module is used to receive time latch signals sent by each subsystem in the SOC chip at startup, and synchronously acquire the first moment when the common time latch unit receives the time latch signals; parse the time latch signals to acquire the second moment when the subsystem starts up; and determine the time deviation between each of the multiple subsystems in the SOC chip and the common time latch unit based on the first moment and the second moment. The second acquisition module is used to acquire the target time corresponding to the target task in response to the need for multiple subsystems to execute the target task synchronously. The determining module is used to determine the task execution time of the target task corresponding to each subsystem based on the target time and the time deviation of the subsystem. The control module is used to control the subsystem to execute the target task at the task execution time.

7. The apparatus according to claim 6, characterized in that, The determining module is further configured to: For any of the subsystems, obtain the sum of the time deviations between the target time and the time deviations corresponding to the subsystem; Based on the sum, the task execution time of the subsystem is determined.

8. The apparatus according to claim 6, characterized in that, The first acquisition module is further configured to: The time-latched signal is buffered; The parsing of the time-latched signal includes: The time latch signal is obtained from the cache and then parsed.

9. The apparatus according to claim 8, characterized in that, The first acquisition module is further configured to: Based on the subsystem identifier of the time latch signal, determine the latch register corresponding to the subsystem; The time latch signal is registered to the corresponding latch register.

10. The apparatus according to claim 6, characterized in that, Also includes: The third acquisition module is used to reacquire the time deviation between the subsystem and the common time latch unit at set intervals.

11. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

12. A computer storage medium storing computer instructions, characterized in that, The computer instructions are used to instruct the computer to perform the method according to any one of claims 1-5.

13. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-5.

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