A chip interface verification method, device, equipment and medium

Abstract

The application discloses a chip interface verification method, device, equipment and medium. The method comprises the following steps: receiving an interface verification command, determining a target verification program corresponding to the interface verification command according to the interface verification command, determining a target application program corresponding to a chip to be verified according to the interface verification command, and downloading the target application program into the chip to be verified, determining a target configuration parameter file and a target script according to the interface verification command and the target verification program, configuring parameters of an FPGA according to the target configuration parameter file, and verifying the interface of the chip to be verified by calling the target script and using the target application program and the target verification program. Through the configuration of the parameters of the FPGA, the circuit corresponding to the interface to be verified is connected and the corresponding parameters are configured. Through the calling of the target script and the verification of the chip interface by using the target application program and the verification program, the automatic verification of the chip is realized, and the verification efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a chip interface verification method, apparatus, device and medium. Background Technology

[0002] With the development of science and technology, chips have gradually become the core of electronic products. Currently, the chip verification phase occupies most of the entire chip development cycle, making chip system verification a crucial step in prototype chip verification.

[0003] In existing technologies, chip interface verification typically involves a combination of interface circuit and prototype chip verification. One approach is to fabricate a verification motherboard after the chip's I / O circuit functionality is finalized. Another approach is to initially not connect the external interface circuit to the chip's interface during motherboard fabrication, then manually connect the circuit later. For example, to verify a specific I / O interface function, manual jumper adjustments are required. The first method establishes the entire verification motherboard; however, modifying the verification function necessitates rebuilding the motherboard, which is time-consuming and labor-intensive, reducing the efficiency of chip interface verification. Furthermore, due to the large number of I / O pins, with each pin potentially having up to 15 multiplexed functions, it may be impossible to verify all I / O interface functions in practice, resulting in low verification coverage. The second method involves manual circuit adjustments and modifications; however, incorrect connections or faulty wires during these modifications can prevent chip interface verification and may even damage the chip, reducing the accuracy of the verification results and overall efficiency.

[0004] Therefore, how to improve the accuracy of verification results and how to improve the verification efficiency of chip interfaces are technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a method, apparatus, device, and medium for verifying chip interfaces, thereby improving the accuracy of verification results and the efficiency of chip interface verification.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for verifying a chip interface, the method comprising:

[0008] Receive interface verification commands;

[0009] The target verification program corresponding to the interface verification command is determined based on the interface verification command;

[0010] The target application corresponding to the chip to be verified is determined according to the interface verification command, and the target application is downloaded to the chip to be verified.

[0011] The target configuration parameter file and target script are determined based on the interface verification command and the target verification program;

[0012] Configure the FPGA parameters according to the target configuration parameter file;

[0013] The interface of the chip to be verified is verified by calling the target script using the target application and the target verification program.

[0014] Optionally, determining the target configuration parameter file and target script based on the interface verification command and the target verification program includes:

[0015] Determine the circuit diagram corresponding to the interface verification command based on the interface verification command;

[0016] Based on the circuit diagram, determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified, and generate an interface circuit connection correspondence table.

[0017] Generate the target configuration parameter file based on the interface circuit connection correspondence table;

[0018] The target script is determined based on the target verification procedure.

[0019] Optionally, determining the target verification program corresponding to the interface verification command based on the interface verification command includes:

[0020] The target verification interface circuit of the chip to be verified is determined according to the interface verification command; the target verification interface circuit is either a master interface circuit or a slave interface circuit.

[0021] If the target verification interface circuit is the main interface circuit, then the main interface verification program corresponding to the main interface circuit will be used as the target verification program.

[0022] If the target verification interface circuit is a slave interface circuit, then the slave interface verification program corresponding to the slave interface circuit will be used as the target verification program.

[0023] Optionally, configuring the FPGA parameters according to the target configuration parameter file includes:

[0024] Configure the parameters of the interface circuit of the chip to be verified according to the target configuration parameter file;

[0025] Configure the parameters of the verification interface circuit in the FPGA according to the target configuration parameter file.

[0026] Secondly, embodiments of this application provide a chip interface verification device, the device comprising: an interface verification command receiving module, a target verification program determining module, a target application determining and downloading module, a parameter and script determining module, a parameter configuration module, and a chip interface verification module;

[0027] The interface verification command receiving module is used to receive interface verification commands;

[0028] The target verification program determination module is used to determine the target verification program corresponding to the interface verification command based on the interface verification command.

[0029] The target application determination and download module is used to determine the target application corresponding to the chip to be verified according to the interface verification command, and download the target application to the chip to be verified;

[0030] The parameter and script determination module is used to determine the target configuration parameter file and the target script based on the interface verification command and the target verification program.

[0031] The parameter configuration module is used to configure the parameters of the FPGA according to the target configuration parameter file;

[0032] The chip interface verification module is used to verify the chip to be verified by calling the target script using the target application and the target verification program.

[0033] Optionally, the parameter and script determination module includes:

[0034] The circuit diagram determination module is used to determine the circuit diagram corresponding to the interface verification command based on the interface verification command.

[0035] The relationship table determination module is used to determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified based on the circuit diagram, and generate an interface circuit connection correspondence table.

[0036] The parameter determination module is used to generate a target configuration parameter file based on the interface correspondence table.

[0037] The script determination module is used to determine the target script based on the target verification program.

[0038] Optionally, the module for determining based on the target verification procedure includes:

[0039] The interface circuit determination module is used to determine the target verification interface circuit of the chip to be verified according to the interface verification command; the target verification interface circuit is a main interface circuit or a slave interface circuit.

[0040] The first target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is the main interface circuit, and then use the main interface verification procedure corresponding to the main interface circuit as the target verification procedure.

[0041] The second target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is a slave interface circuit, and then use the slave interface verification procedure corresponding to the slave interface circuit as the target verification procedure.

[0042] Optionally, the parameter configuration module includes:

[0043] The first parameter configuration module is used to configure the parameters of the interface circuit of the chip to be verified according to the target configuration parameter file;

[0044] The second parameter configuration module is used to configure the parameters of the verification interface circuit in the FPGA according to the target configuration parameter file.

[0045] Thirdly, embodiments of this application provide a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the chip interface verification method as described in the first aspect.

[0046] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a terminal device, cause the terminal device to perform the chip interface verification method as described in the first aspect.

[0047] Compared to existing technologies, this application has the following advantages: This application receives an interface verification command, determines the target verification program corresponding to the interface verification command, determines the target application program corresponding to the chip to be verified based on the interface verification command, downloads the target application program to the chip to be verified, determines a target configuration parameter file and a target script based on the interface verification command and the target verification program, configures the FPGA parameters according to the target configuration parameter file, and verifies the interface of the chip to be verified by calling the target script using the target application program and the target verification program. Specifically, configuring the FPGA parameters through the target configuration parameter file enables the circuit connection corresponding to the function to be verified, i.e., configuring the parameters corresponding to the function to be verified eliminates the need for manual circuit modification or adjustment. Simultaneously, by calling the target script and using the target application program and verification program to verify the chip interface, automated verification of the chip interface is achieved, improving verification efficiency and avoiding the problem of inaccurate verification results caused by manual circuit modification and adjustment. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A flowchart illustrating a chip interface verification method provided in an embodiment of this application;

[0050] Figure 2 A schematic diagram of a chip interface verification system in practical application provided by an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of a chip interface verification device provided in an embodiment of this application. Detailed Implementation

[0052] As described earlier, research on prototype chip verification revealed that in existing technologies, chip interface verification typically involves combining interface circuitry with prototype chip verification. One approach is to fabricate the verification motherboard after the chip's I / O circuitry is largely finalized. Another approach is to not connect the external interface circuitry to the chip's interface during motherboard fabrication, but instead manually connect the circuitry later. For example, verifying a specific I / O interface function requires manual jumper adjustments to the circuitry. The first method establishes the entire verification motherboard; however, modifying the verification function necessitates rebuilding the motherboard, which is time-consuming and labor-intensive, reducing the efficiency of chip interface verification. Furthermore, due to the large number of I / O pins, with each pin potentially having up to 15 multiplexed functions, it may be impossible to verify all I / O interface functions in practice, resulting in low verification coverage. The second method involves manual adjustment and modification of the circuitry; however, incorrect connections or faulty wires during circuitry modification can prevent chip interface verification and may even damage the chip, reducing the accuracy of the verification results and overall efficiency.

[0053] To address the aforementioned problems, embodiments of this application provide a method, apparatus, device, and medium for verifying chip interfaces. The method includes: receiving an interface verification command; determining a target verification program corresponding to the interface verification command; determining a target application program corresponding to a chip to be verified based on the interface verification command; downloading the target application program to the chip to be verified; determining a target configuration parameter file and a target script based on the interface verification command and the target verification program; configuring FPGA parameters according to the target configuration parameter file; and verifying the interface of the chip to be verified by calling the target script using the target application program and the target verification program.

[0054] In this way, by configuring the FPGA parameters through the target configuration parameter file, the circuit corresponding to the function to be verified can be connected. That is, the parameters corresponding to the function to be verified are configured, and no manual circuit modification or adjustment is required. At the same time, by calling the target script and using the target application and verification program to verify the chip interface, the chip verification is automated, which improves the verification efficiency and avoids the problem of inaccurate verification results caused by manual modification and adjustment of the circuit.

[0055] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0056] Regarding the following embodiments, it should be noted that in real-world scenarios, a chip's I / O interface has numerous pins, and each pin corresponds to a variety of functions. Therefore, in existing technologies, whether the verification motherboard is fabricated after the chip's I / O circuit functionality is finalized, or the external interface circuit is not connected to the chip's interface during motherboard fabrication and the connection is established manually later, there is a technical problem that the large number of pins and their corresponding functions makes it impossible to verify all of them. Therefore, this application provides a chip interface verification method that can automate the verification of the chip's I / O interface and all pins and their corresponding functions, thereby improving the coverage of chip interface verification.

[0057] See Figure 1 This figure is a flowchart of a chip interface verification method provided in an embodiment of this application, combined with... Figure 1 As shown, the method may include:

[0058] S101: Receive interface verification command.

[0059] An interface verification command refers to a command received by the input interface of the main control device to verify the interface of the chip. The interface verification command may include verification function requirements, chip information to be verified, and other control parameters, etc., including but not limited to the two types of information, which are not specifically limited here.

[0060] S102: Determine the target verification program corresponding to the interface verification command based on the interface verification command.

[0061] The target verification program refers to the program used by the host device to verify the interface of the chip to be verified, and it is an application program running on the host device. The specific functions that the target verification program can achieve may include: processing the target script, downloading the verification interface circuit parameters of the FPGA, downloading the target application program, controlling the verification steps and processes, etc., including but not limited to the functions that the target verification program can achieve as described above, and are not specifically limited here.

[0062] In one feasible implementation, step S105 may specifically include:

[0063] Step 1: Determine the target verification interface circuit of the chip to be verified according to the interface verification command; the target verification interface circuit is either a master interface circuit or a slave interface circuit.

[0064] Step 2: If the target verification interface circuit is the main interface circuit, then the main interface verification program corresponding to the main interface circuit is used as the target verification program.

[0065] Step 3: If the target verification interface circuit is a slave interface circuit, then the slave interface verification program corresponding to the slave interface circuit shall be used as the target verification program.

[0066] It should be noted that when the target verification program is the main interface verification program, the target application is the slave interface application; when the target verification program is the slave interface verification program, the target application is the main interface application.

[0067] The serial numbers corresponding to steps one through three are only used to distinguish different steps or to distinguish the temporal relationship between different steps, and are not shown in the attached figures.

[0068] S103: Determine the target application corresponding to the chip to be verified according to the interface verification command, and download the target application to the chip to be verified.

[0069] The target application refers to the application that runs and tests the interface of the chip to be verified. It may include initializing the chip interface pins, configuring interface parameters (such as mode, speed and function), and accepting communication commands from the target verification program to complete the functions of the interface and return communication responses.

[0070] Since the target application is used in the chip to be verified, the identified target application needs to be downloaded to the chip to facilitate subsequent verification of the chip's interface.

[0071] S104: Determine the target configuration parameter file and target script based on the interface verification command and the target verification program.

[0072] The target configuration parameter file refers to the file used to configure the parameters of the FPGA module.

[0073] There is a correspondence between the interface verification command and the target configuration file. For example, if the interface verification command verifies the I / O port of the chip to be verified, then the target configuration parameter file corresponding to the interface verification command can contain parameters related to the I / O port.

[0074] As one possible implementation, step S104 may specifically include:

[0075] Step 1: Determine the circuit diagram corresponding to the interface verification command based on the interface verification command;

[0076] Step 2: Determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified based on the circuit diagram, and generate an interface circuit connection correspondence table;

[0077] Step 3: Generate the target configuration parameter file based on the interface circuit connection correspondence table;

[0078] Step 4: Determine the target script based on the target verification procedure.

[0079] The verification interface circuit refers to the interface function of the verification device used to verify the chip.

[0080] The correspondence refers to the connection between the verification interface circuit and the interface circuit of the chip to be verified. It should be noted that both the verification interface and the chip interface have multiple pins (which can also be called sub-interfaces). Therefore, there is more than one correspondence (or connection) between the two.

[0081] The generated interface mapping table can be an Excel spreadsheet or a mapping table; no specific limitation is made here.

[0082] The target configuration parameter file can be generated using a script tool interface mapping table to a configuration parameter file usable by the verification program. Alternatively, other methods can also be used to generate the target configuration parameter file; no specific limitations are specified here.

[0083] The serial numbers corresponding to steps 1 to 4 are only used to distinguish different steps or to distinguish the temporal relationship between different steps, and are not shown in the attached figures.

[0084] S105: Configure the FPGA parameters according to the target configuration parameter file.

[0085] FPGA stands for Application-Specific Integrated Circuit, a type of semi-custom circuit that is a programmable logic array. The basic structure of an FPGA can include programmable input / output units, configurable logic blocks, a digital clock management module, embedded block RAM, routing resources, embedded dedicated hard cores, and low-level embedded functional units.

[0086] In this embodiment, the FPGA is integrated on a verification motherboard containing the FPGA chip to be verified. In other possible implementations, the FPGA can also be integrated on other circuit boards, and no specific limitation is made here.

[0087] As an example, S105 may specifically include:

[0088] Configure the parameters of the target verification interface circuit of the chip to be verified according to the target configuration parameter file;

[0089] Configure the parameters of the verification interface circuit in the FPGA according to the target configuration parameter file.

[0090] The FPGA is configured according to the target configuration parameter file to achieve bidirectional communication from the specified input to the output pin and complete the circuit logic connection.

[0091] S106: Using the target application and the target verification program, the interface of the chip to be verified is verified by calling the target script.

[0092] Specifically, the interface of the chip to be verified is verified by using the target application and the target verification program, following predetermined steps in the target script.

[0093] The target verification program parses the target script and controls the execution of communication commands from the target application. It obtains the communication response of the target application's execution result and compares it with a preset response in the target script. If the execution result matches the preset response, the test interface is considered successful; otherwise, the test interface is considered to have failed. The target script may contain communication commands that control the target application to run and their preset communication results.

[0094] The chip interface verification method provided in this application configures the FPGA parameters through a target configuration parameter file, thereby connecting the circuits corresponding to the function to be verified. This means that once the parameters corresponding to the function to be verified are configured, no manual circuit construction, modification, or adjustment is required. Then, using the target application and the target verification program, the interface of the chip to be verified is verified by calling the target script, achieving automated verification of the chip interface. This improves verification efficiency and avoids the problem of inaccurate verification results caused by manual circuit modification and adjustment. Furthermore, since this application embodiment can achieve automated verification of chip interfaces, all chip interfaces can be verified using this method, improving verification coverage.

[0095] Based on the chip interface verification method provided in the above embodiments, this application provides a chip interface verification system for practical applications. (See attached document.) Figure 2 This figure is a schematic diagram of a chip interface verification system in practical application provided by an embodiment of this application, combined with... Figure 2 As shown, the chip interface verification system provided in this application embodiment can include: Raspberry Pi, digital integrated circuit SoC (also known as prototype chip or chip), FPGA and interface circuit.

[0096] like Figure 2 As shown, the prototype chip is connected to the interface circuit via an FPGA.

[0097] like Figure 2 As shown, the Raspberry Pi communicates with the prototype chip via UART1; the Raspberry Pi communicates with the FPGA via UART2. Here, UART (Universal Asynchronous Receiver / Transmitter) refers to a universal asynchronous receiver / transmitter.

[0098] like Figure 2 As shown, the Raspberry Pi's master SPI interface [abbreviated as SPI(M)] is electrically connected to the prototype chip's slave SPI interface [abbreviated as SPI(S)] via the FPGA. Specifically, when verifying the prototype chip's slave SPI interface, the Raspberry Pi acts as the master in SPI communication, and the prototype chip acts as the slave in SPI communication.

[0099] SPI (Serial Peripheral Interface) is a serial peripheral interface. The master serial peripheral interface can be abbreviated as SPI(M), and the slave serial peripheral interface can be abbreviated as SPI(S).

[0100] like Figure 2As shown, the Raspberry Pi's master I2C interface [abbreviated as I2C(M)] is electrically connected to the prototype chip's slave I2C interface [abbreviated as I2C(S)] via the FPGA. When verifying the prototype chip's slave I2C(S) interface, the Raspberry Pi acts as the master for I2C communication, and the prototype chip acts as the slave for I2C communication.

[0101] The Chinese translation of I2C (I-squared-C or I-two-C) is bidirectional two-wire synchronous serial bus. The master I2C interface can be abbreviated as I2C(M), and the slave I2C interface can be abbreviated as I2C(S).

[0102] The Raspberry Pi is used for the control, logic judgment, and log storage of the verification system for the chip interface.

[0103] The prototype chip is used to test all the logic operation functions of the peripheral functions of the SoC chip; the Chinese interpretation of SoC chip (System on Chip) is system-level chip, which can also be interpreted as system on chip.

[0104] The FPGA is used to implement logic decoding, connect the specified I / O of the prototype chip to a specific external interface circuit, detect and sample the clock or data signal quality of the I / O data, and return the monitoring results of the interface signal quality to the Raspberry Pi.

[0105] The interface circuit is a hardware circuit used to verify the digital functions of the prototype chip's I / O, and may include the following interfaces: input / output interface (GPIO), serial port (UART), main serial peripheral interface [SPI(M)], main bidirectional two-wire synchronous serial bus [abbreviated as I2C(M)] and contact smart card [abbreviated as 7816(M)], etc.

[0106] The Raspberry Pi (abbreviated as RPi, also known as RasPi / RPI) is a device used to learn programming. It is based on an embedded chip design, has a computer operating system, and can connect to external devices.

[0107] In this embodiment, a Raspberry Pi is used as the master terminal of the chip interface verification system. However, it is not limited to using a Raspberry Pi as the master terminal of the system. It can also be a computer or other devices. Other devices refer to those containing a SoC chip with certain processing capabilities, which is not specifically limited here.

[0108] Based on the schematic diagram of a chip interface verification system in practical application provided in the above embodiments, this application embodiment also provides a chip interface verification process. When the content to be verified is the main interface circuit of the prototype chip, taking the smart card interface [abbreviated as 7816(M)] as an example, the verification process can be as follows:

[0109] (1) Make a verification test board.

[0110] The verification test board may include a prototype chip, an FPGA, interface circuits, and other peripheral circuits. The peripheral circuits are not specifically described here; any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

[0111] The prototype chip's digital I / O is connected to a portion of the FPGA's I / O, and the FPGA's I / O is connected to the interface circuit. The interface circuit can be a physical peripheral, which includes an I2C(S) interface EEPROM, an SPI(S) interface FLASH, a contact smart card interface (7816(M)), communication conversion, and input / output circuits (e.g., PWM and indicator lights).

[0112] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a type of memory chip that retains data even when power is off. EEPROM can be erased and reprogrammed on a computer or dedicated device.

[0113] FLASH (Flash EEPROM Memory) is a type of memory chip that allows data to be modified using a specific program. In the electronics and semiconductor fields, FLASH often refers to Flash Memory, commonly known as "flash memory."

[0114] PWM (Pulse width modulation) is a technique that modulates pulse width.

[0115] (2) Create FPGA parameter files.

[0116] Based on the test function requirements, create the corresponding circuit diagram. According to the circuit diagram, create an Excel spreadsheet showing the correspondence between FPGA input and output I / O and the signal types. Use a scripting tool to convert the Excel spreadsheet into a configuration parameter file used by the Raspberry Pi test tool software program. This parameter file contains the circuit connection correspondence and signal types (types are divided into clock or communication signals).

[0117] (3) Write FPGA RTL code.

[0118] It accepts parameter setting commands from the Raspberry Pi testing tool software program, which contains the aforementioned configuration parameter file; at the same time, it detects the signal quality of the corresponding interface circuit in real time according to the signal type in the configuration parameter file, and sends the results back to the Raspberry Pi testing tool software program.

[0119] The FPGA RTL code is used to configure the parameters of the FPGA.

[0120] (4) Create a verification script parameter file.

[0121] Based on the testing functional requirements, parameters such as communication commands and communication command responses between the target verification program and the target application are created, and a verification script parameter file is created using a scripting tool for the Raspberry Pi testing tool software program.

[0122] It should be noted that, in this embodiment of the application, the verification script parameter file (i.e., the target script) is run on the Raspberry Pi, thereby enabling the sending and receiving of communication commands between the target verification program on the Raspberry Pi and the target application on the chip to be verified.

[0123] (5) Write the target application.

[0124] Based on the purpose of system interface verification, a corresponding application is written and stored in the Raspberry Pi. The application can be upgraded online via the Raspberry Pi's serial port to upgrade the prototype chip's application.

[0125] The prototype chip program refers to the application program that is run later for verification.

[0126] (6) Write the target verification program.

[0127] Based on the purpose of system interface verification, an application program was written for the Raspberry Pi. First, the Raspberry Pi sends communication commands to the prototype chip via serial port 1 and receives the response results of these commands. Second, the Raspberry Pi sets the FPGA operating parameters via serial port 2 and simultaneously receives data on the communication quality of the FPGA's interconnect circuits, which can be monitored in real time. Third, the Raspberry Pi parses the verification script file, processes the response to the sent or received communication commands according to the script file, and automatically determines the test result based on the received execution result and the predetermined return result, thus automating the system interface verification.

[0128] (7) Test and analyze the test results.

[0129] The target verification program runs on the Raspberry Pi, automatically determining the test results based on the responses to received communication commands and predetermined outcomes, or simultaneously recording runtime logs in real time, which can then be analyzed. Further testing tools are run via command-line input, allowing selection of one or more parameters to perform tests on single or multiple test cases.

[0130] The above steps (1) to (7) can also be used to verify the I2C(M), SPI(M) interfaces, communication conversion and input / output circuits of the prototype chip, which will not be described in detail here.

[0131] The above embodiments provide a Raspberry Pi as the master end of the chip interface verification system and the chip to be verified as the slave end. In one feasible implementation, the Raspberry Pi can also be used as the slave end of the chip interface verification system and the chip to be verified as the master end. The specific implementation method is the same as the above embodiments, so it will not be described again.

[0132] Based on the chip interface verification method provided in the above embodiments, this application further provides a chip interface verification device, see [link to relevant documentation]. Figure 3 This figure is a schematic diagram of the structure of a chip interface verification device provided in an embodiment of this application, combined with... Figure 3 As shown in the embodiments of this application, the chip interface verification device may include: an interface verification command receiving module 301, a target verification program determining module 302, a target application determining and downloading module 303, a parameter and script determining module 304, a parameter configuration module 305, and a chip interface verification module 306.

[0133] The interface verification command receiving module 301 is used to receive interface verification commands;

[0134] The target verification program determination module 302 is used to determine the target verification program corresponding to the interface verification command according to the interface verification command.

[0135] The target application determination and download module 303 is used to determine the target application corresponding to the chip to be verified according to the interface verification command, and download the target application to the chip to be verified;

[0136] The parameter and script determination module 304 is used to determine the target configuration parameter file and the target script based on the interface verification command and the target verification program.

[0137] The parameter configuration module 305 is used to configure the parameters of the FPGA according to the target configuration parameter file;

[0138] The chip interface verification module 306 is used to verify the chip to be verified by calling the target script using the target application and the target verification program.

[0139] As an example, the parameter and script determination module 304 includes:

[0140] The circuit diagram determination module is used to determine the circuit diagram corresponding to the interface verification command based on the interface verification command.

[0141] The relationship table determination module is used to determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified based on the circuit diagram, and generate an interface circuit connection correspondence table.

[0142] The parameter determination module is used to generate a target configuration parameter file based on the interface circuit connection correspondence table.

[0143] The script determination module is used to determine the target script based on the target verification program.

[0144] As an example, the target verification procedure determination module 302 includes:

[0145] The interface circuit determination module is used to determine the target verification interface circuit of the chip to be verified according to the interface verification command; the target verification interface circuit is a main interface circuit or a slave interface circuit.

[0146] The first target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is the main interface circuit, and then use the main interface verification procedure corresponding to the main interface circuit as the target verification procedure.

[0147] The second target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is a slave interface circuit, and then use the slave interface verification procedure corresponding to the slave interface circuit as the target verification procedure.

[0148] As an example, the parameter configuration module 302 includes:

[0149] The first parameter configuration module is used to configure the parameters of the interface circuit of the chip to be verified according to the target configuration parameter file.

[0150] The second parameter configuration module is used to configure the parameters of the verification interface circuit according to the target configuration parameter file.

[0151] The chip interface verification device provided in this application embodiment has the same beneficial effects as the chip interface verification method provided in the above embodiments, so it will not be described again.

[0152] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.

[0153] The device includes a memory and a processor. The memory is used to store instructions or code, and the processor is used to execute the instructions or code to enable the device to perform the chip interface verification method described in any embodiment of this application.

[0154] The computer storage medium stores code, and when the code is run, the device running the code implements the chip interface verification method described in any embodiment of this application.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The device and equipment embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0156] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0157] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0158] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for verifying a chip interface, characterized in that, The method includes: Receive interface verification commands; The target verification program corresponding to the interface verification command is determined based on the interface verification command; The target application corresponding to the chip to be verified is determined according to the interface verification command, and the target application is downloaded to the chip to be verified. Determine the circuit diagram corresponding to the interface verification command based on the interface verification command; Based on the circuit diagram, determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified, and generate an interface circuit connection correspondence table. Generate the target configuration parameter file based on the interface circuit connection correspondence table; The target script is determined based on the target verification procedure; Configure the FPGA parameters according to the target configuration parameter file; The interface of the chip to be verified is verified by calling the target script using the target application and the target verification program.

2. The chip interface verification method according to claim 1, characterized in that, The step of determining the target verification program corresponding to the interface verification command based on the interface verification command includes: The target verification interface circuit of the chip to be verified is determined according to the interface verification command; the target verification interface circuit is either a master interface circuit or a slave interface circuit. If the target verification interface circuit is the main interface circuit, then the main interface verification program corresponding to the main interface circuit will be used as the target verification program. If the target verification interface circuit is a slave interface circuit, then the slave interface verification program corresponding to the slave interface circuit will be used as the target verification program.

3. The chip interface verification method according to claim 1, characterized in that, The step of configuring the FPGA parameters according to the target configuration parameter file includes: Configure the parameters of the interface circuit of the chip to be verified according to the target configuration parameter file; Configure the parameters of the verification interface circuit in the FPGA according to the target configuration parameter file.

4. A chip interface verification device, characterized in that, The device includes: an interface verification command receiving module, a target verification program determination module, a target application determination and download module, a parameter and script determination module, a parameter configuration module, and a chip interface verification module. The parameter and script determination module includes: a circuit diagram determination module, a relationship table determination module, a parameter determination module, and a script determination module. The interface verification command receiving module is used to receive interface verification commands; The target verification program determination module is used to determine the target verification program corresponding to the interface verification command based on the interface verification command. The target application determination and download module is used to determine the target application corresponding to the chip to be verified according to the interface verification command, and download the target application to the chip to be verified; The circuit diagram determination module is used to determine the circuit diagram corresponding to the interface verification command based on the interface verification command. The relationship table determination module is used to determine multiple correspondences between the verification interface circuit and the interface circuit of the chip to be verified based on the circuit diagram, and generate an interface circuit connection correspondence table. The parameter determination module is used to generate a target configuration parameter file based on the interface circuit connection correspondence table. The script determination module is used to determine the target script based on the target verification program; The parameter configuration module is used to configure the parameters of the FPGA according to the target configuration parameter file; The chip interface verification module is used to verify the chip to be verified by calling the target script using the target application and the target verification program.

5. The chip interface verification device according to claim 4, characterized in that, The target verification procedure determination module includes: The interface circuit determination module is used to determine the target verification interface circuit of the chip to be verified according to the interface verification command; the target verification interface circuit is a main interface circuit or a slave interface circuit. The first target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is the main interface circuit, and then use the main interface verification procedure corresponding to the main interface circuit as the target verification procedure. The second target verification procedure determination module is used to determine the target verification procedure if the target verification interface circuit is a slave interface circuit, and then use the slave interface verification procedure corresponding to the slave interface circuit as the target verification procedure.

6. The chip interface verification device according to claim 4, characterized in that, The parameter configuration module includes: The first parameter configuration module is used to configure the parameters of the interface circuit of the chip to be verified according to the target configuration parameter file; The second parameter configuration module is used to configure the parameters of the verification interface circuit in the FPGA according to the target configuration parameter file.

7. A computer device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the chip interface verification method as described in any one of claims 1-3.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a terminal device, cause the terminal device to perform the chip interface verification method as described in any one of claims 1-3.

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