Method, apparatus, electronic device and storage medium for data prefetching

Abstract

The application provides a data prefetching method and device, electronic equipment and a storage medium. The method can include: obtaining a to-be-accessed address, determining whether there is a cache miss for to-be-read data corresponding to the to-be-accessed address, if yes, determining a prefetch stride by using an access condition of a neighboring address of the to-be-accessed address, and updating a prefetch request queue by using the prefetch stride. The prefetch request queue is used for data prefetching from a storage unit. According to the embodiment of the application, the time for waiting for the next level storage after the cache miss is reduced.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data prefetching method, apparatus, electronic device, and storage medium. Background Technology

[0002] Cache is a key module for improving the performance of high-performance processors. Its design often requires comprehensive consideration of factors such as data coverage, accuracy, and timeliness. In other words, it needs to ensure that the data to be read is located in the cache as much as possible to improve the cache hit rate and thus reduce the latency caused by multiple accesses to the next level of storage after data loss.

[0003] In sequentially executing processors, data access addresses are issued sequentially, and these addresses have a certain correlation over a period of time, making them easy to record and prefetch. However, in out-of-order execution processors, data access addresses are out of order, requiring more and more disorganized historical information to be recorded, increasing the difficulty of prefetch address calculation. Therefore, a prefetch strategy specifically for out-of-order processors is needed. Summary of the Invention

[0004] This application provides a data prefetching method, apparatus, electronic device, and storage medium.

[0005] In a first aspect, embodiments of this application provide a data prefetching method, which may include:

[0006] Obtain the address to be accessed, determine whether there is a cache missing in the data to be read corresponding to the address to be accessed, and if so, determine the prefetch stride by using the access situation of the neighboring addresses of the address to be accessed.

[0007] The prefetch request queue is updated using the prefetch step size; the prefetch request queue is used to prefetch data from storage units.

[0008] Determining the prefetch stride by utilizing the access patterns of neighboring addresses of the address to be accessed may include:

[0009] The address identifier status of adjacent addresses is obtained using the memory access address mapping table. The address identifier status includes whether the address has been accessed or not.

[0010] The prefetch stride is determined based on the stride interval between the neighboring addresses of the visited state and the address to be visited.

[0011] This also includes obtaining the cumulative number of occurrences of the prefetch step size and determining the prefetch degree, which is used to characterize the number of prefetch addresses selected using the prefetch step size;

[0012] Update the prefetch request queue using the prefetch step size and prefetch degree.

[0013] Among these steps, obtaining the cumulative number of occurrences of the prefetched step size and determining the prefetching degree may include:

[0014] Obtain the existing prefetch level N, where N is a positive integer;

[0015] If the cumulative number of times the prefetched step size occurs is not less than the corresponding number threshold, N+a is used as the determined prefetching degree, where a is a natural number;

[0016] If the cumulative number of times the prefetched step size occurs is less than the corresponding threshold, N is used as the determined prefetch degree.

[0017] Obtaining the cumulative number of occurrences of the prefetched step size can include:

[0018] Use the stride queue list to obtain the prefetch stride usage status of the memory access address mapping table, including whether it has been used or not.

[0019] If the adoption condition is not adopted, the cumulative number of occurrences of the prefetched step size will be set to 0;

[0020] If the adoption condition is already adopted, the cumulative number of occurrences of the prefetched step size is set from M to M+1, where M is an integer not less than 0.

[0021] Additionally, it may include: dynamically adjusting the prefetching degree of the prefetching step using the results of data prefetching;

[0022] The process of prefetching the stride length includes:

[0023] The prefetching degree and / or the cumulative occurrence of prefetching steps are dynamically adjusted based on at least one of the following: the adoption of data prefetching results and historical duration.

[0024] Additionally, it may include storing data prefetched from the storage unit using a prefetch request queue into a prefetch buffer.

[0025] Additionally, it may include: generating a data retrieval request and copying or migrating the data corresponding to the data retrieval request from the prefetch buffer to the cache.

[0026] Additionally, it may include: generating a data retrieval request, which is used to retrieve data directly from the storage unit.

[0027] Additionally, updating the prefetch request queue may include deduplicating the prefetch request queue.

[0028] Deduplication of the prefetch request queue can specifically include:

[0029] Compare the updated prefetch request queue with the previous prefetch request queue to remove duplicate data; and / or

[0030] The updated prefetch request queue is compared with the data in the prefetch buffer, and duplicate data is deduplicated.

[0031] Secondly, embodiments of this application provide a data prefetching apparatus, which may include:

[0032] The prefetch stride determination module is used to determine whether there is a cache missing data to be read and to determine the address to be accessed. The prefetch stride is determined by the access situation of the neighboring addresses of the address to be accessed.

[0033] The prefetch request queue update module is used to update the prefetch request queue using the prefetch step size; the prefetch request queue is used to prefetch data from the storage unit.

[0034] The pre-fetch stride determination module may include:

[0035] The address identifier status acquisition submodule is used to obtain the address identifier status of adjacent addresses using the memory access address mapping table. The address identifier status includes whether the address has been accessed or not.

[0036] The prefetch stride determination submodule is used to determine the prefetch stride based on the stride interval between the neighboring addresses of the visited state and the address to be visited.

[0037] Additionally, it may include a prefetch degree determination module, which is used to obtain the cumulative number of occurrences of the prefetch step size and determine the prefetch degree. The prefetch degree is used to characterize the number of prefetch addresses selected using the prefetch step size.

[0038] The prefetch request queue update module is also used to update the prefetch request queue using the prefetch step size and prefetch degree.

[0039] In addition, the prefetching degree determination module may also include:

[0040] The existing prefetch degree acquisition submodule is used to acquire the existing prefetch degree N, where N is a positive integer;

[0041] The first prefetch degree determination execution submodule is used to determine N+a as the prefetch degree when the cumulative number of occurrences of the prefetch step is not less than the corresponding number threshold, where a is a natural number.

[0042] The second prefetch degree determination execution submodule is used to determine N as the prefetch degree when the cumulative number of prefetch steps is less than the corresponding number threshold.

[0043] The prefetching degree determination module may further include:

[0044] The prefetch stride adoption status acquisition submodule is used to obtain the prefetch stride adoption status of the memory access address mapping table using the stride queue list. The adoption status includes whether it is not adopted or has been adopted.

[0045] The first prefetch step count determination submodule is used to set the prefetch step count to 0 when the adoption status is not adopted.

[0046] The second prefetch step count determination submodule is used to set the prefetch step count from M to M+1 when the adoption status is adopted, where M is an integer not less than 0.

[0047] Additionally, a dynamic prefetching level adjustment module may be included. This module can be used to dynamically adjust the prefetching level of the prefetching stride and / or the cumulative number of occurrences of the prefetching stride based on at least one of the following: the adoption of data prefetching results and historical duration.

[0048] Additionally, a prefetch buffer may be included. The prefetch buffer is used to store data prefetched from the storage unit using a prefetch request queue.

[0049] Additionally, it may include a data acquisition request generation module, which generates a data acquisition request and copies or migrates the data corresponding to the data acquisition request from the prefetch buffer to the cache.

[0050] In addition, the data acquisition request generation module can also be used to generate data acquisition requests, which are used to directly acquire data from the storage unit.

[0051] Additionally, a deduplication module may be included to deduplicate the prefetch request queue after updating it.

[0052] The deduplication module may specifically include:

[0053] The first deduplication execution submodule is used to compare the updated prefetch request queue with the previous prefetch request queue to deduplicate duplicate data; and / or

[0054] The second deduplication execution submodule is used to compare the updated prefetch request queue with the data in the prefetch buffer and perform deduplication on duplicate data.

[0055] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor, when executing the computer program, implements the method described in any of the above-mentioned embodiments.

[0056] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method described in any of the above-mentioned embodiments.

[0057] Compared with the prior art, this application has the following advantages:

[0058] According to the embodiments of this application, by setting a data prefetching mechanism with a prefetching step size, for out-of-order data access addresses, when encountering large-scale computation, some data with obvious address continuity will be prefetched in advance, thereby reducing the waiting time for the next level of storage after a data access address is missed. In addition, the prefetching degree is dynamically adjusted according to the prefetching step size within a certain period of time, which can better adapt to the dynamic changes of the program and avoid the situation of prefetching being too aggressive or too conservative.

[0059] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0060] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this application and should not be construed as limiting the scope of this application.

[0061] Figure 1 This is one of the flowcharts for a data prefetching method according to an embodiment of this application;

[0062] Figure 2 This is a schematic diagram of the structural topology of a data prefetching method according to an embodiment of this application;

[0063] Figure 3 This is a schematic diagram of the prefetching degree determination process according to an embodiment of this application;

[0064] Figure 4 This is a second flowchart of a data prefetching method according to an embodiment of this application;

[0065] Figure 5 This is a structural block diagram of a data prefetching apparatus according to another embodiment of this application; and

[0066] Figure 6 This is a block diagram of an electronic device used to implement embodiments of this application. Detailed Implementation

[0067] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the concept or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0068] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0069] This application provides a data prefetching method, such as... Figure 1 The diagram shown is a flowchart of a data prefetching method according to an embodiment of this application, which may include:

[0070] Step S10: Determine if there is a cache missing data to be read and determine its address to be accessed. Use the access situation of neighboring addresses to determine the prefetch stride.

[0071] Step S11: Update the prefetch request queue using the prefetch stride; the prefetch request queue is used to prefetch data from the storage unit.

[0072] Through the above process, by setting a data prefetching mechanism with a prefetching step size, when encountering large-scale computation, some data with obvious address continuity will be prefetched in advance, thereby reducing the time to wait for the next level of storage after a cache miss.

[0073] Further embodiments may also include the following steps:

[0074] Step S101: Determine if there is a cache missing in the data to be read and determine its address to be accessed. Use the access situation of the neighboring addresses of the address to be accessed to determine the prefetch stride.

[0075] Step S102: Obtain the cumulative number of occurrences of the prefetch step and determine the prefetch degree. The prefetch degree is used to characterize the number of prefetch addresses selected using the prefetch step.

[0076] Step S103: Update the prefetch request queue using the prefetch step size and prefetch degree; the prefetch request queue is used to prefetch data from the storage unit.

[0077] During operation, the chip sends instructions to retrieve data from the cache / store and transmit it to other execution units. This data can be used for computation or to generate execution instructions. It is understood that the data in this application is not limited to computation or instruction generation; it can also be used for other common chip operations, such as generating image or audio data output. In one specific application, during data computation, it is necessary to read data from out-of-order access addresses for computation. Combined with... Figure 2 The example shown demonstrates a query to check if the data to be read exists in the cache. If the data exists in the cache, it can be assumed that there is no cache miss. Conversely, if the data does not exist in the cache, it can be determined that there is a cache miss.

[0078] The data to be read corresponds to an access address. In one example, the access address can include 0x00 to 0x08. For example, first, the access address is obtained, and then it is determined whether there is a cache miss in the data to be read corresponding to the access address. Taking the access address 0x04 as an example, the neighboring addresses of the access address can include 0x03, 0x02, 0x05, 0x06, etc. The access status of the neighboring addresses can include either an accessed state (accessed) or an unaccessed state (initial). The determination of the above access status can correspond to... Figure 2 The access address status is matched. If the access status of a neighboring address is already accessed, the prefetch stride between the address to be accessed and the neighboring address that is already accessed can be determined.

[0079] For example, using a stride interval of 1 as a baseline, examining the address flag status of adjacent addresses before and after the address to be accessed, 0x04, reveals that 0x03 and 0x02 are already accessed. Therefore, stride interval 1 can be determined as a prefetch stride. If the prefetch level is 1, address 0x05 should be updated to the prefetch request queue. However, since 0x05 is already accessed, it indicates that the cache or storage unit has already used this address, and there is no need to update it to the prefetch request queue again. Of course, in some execution strategies, 0x02 and / or 0x05 can also be updated to the prefetch request queue to avoid data loss even though the address has been previously accessed. Using a stride interval of 2 as a baseline, examining the address flag status of adjacent addresses before and after the address to be accessed, 0x04, reveals that 0x00 and 0x02 are already accessed. Therefore, stride interval 2 can be determined as a prefetch stride. If the prefetch level is 2, addresses 0x06 and 0x08 should be updated to the prefetch request queue. Using a step interval of 3 as a reference, we check the address flag status of adjacent addresses before and after the address to be accessed, 0x04. 0x01 is in an unaccessed state (initial), and 0x07 is in an accessed state (accessed). There are no two consecutive addresses that satisfy both a step interval of 3 and an accessed state (accessed), so a step interval of 3 is not used as the prefetch step.

[0080] In the above embodiments, the criterion for determining the step size as the prefetch step size is: there are two consecutive adjacent addresses of visited states (accessed) forward or backward. According to the settings, it can also be adjusted to have three, four, or other consecutive adjacent addresses of visited states (accessed), thus determining whether the prefetch step size is hit or valid.

[0081] In some other embodiments, if there are consecutive addresses following the address to be accessed based on stride 1, 2, 3 or other strides, after determining the prefetch stride and prefetch level, neighboring addresses can be selected forward to update the prefetch request queue.

[0082] The cumulative occurrence count of the prefetch stride involved in step S102 can be stored in the stride queue list. The cumulative occurrence count of the prefetch stride can be dynamically updated based on the result in step S101. If the cumulative occurrence count of the prefetch stride exceeds a preset threshold, the prefetch level will also be adjusted accordingly. For example, if the threshold is 4, when the cumulative occurrence count of prefetch stride 1 exceeds 4, the prefetch level will increase by one count unit for each occurrence of prefetch stride 1. The prefetch level is used to characterize the number of prefetch addresses selected using the prefetch stride. Taking the address to be accessed as 0x04 as an example, when the prefetch level of prefetch stride 1 is 2, it means that a prefetch needs to be performed at the neighboring address 0x05, and also at the neighboring address 0x06. Taking the address to be accessed as an example, when the prefetch level of prefetch stride 2 is 2, it means that a prefetch needs to be performed at the neighboring address 0x06, and also at the neighboring address 0x08. That is, the above process corresponds to Figure 2 The diagram illustrates continuous stride prefetching calculation. Continuous stride prefetching calculation comprises a stride queue and prefetching generation logic. The stride queue stores prefetched strides generated over a period of time, along with the corresponding prefetching degree and valid stride count. The prefetching generation logic primarily performs prefetching based on the current stride and prefetching degree.

[0083] The prefetch request queue can be updated using the prefetch step size and prefetch degree. The prefetch request queue is used to prefetch data from memory cells. Figure 2 The intermediate storage unit can include the next-level storage and the main storage. In terms of storage capacity, the main storage > the next-level storage. Generally, data can be retrieved from the next-level storage first. If the data to be retrieved is not present in the next-level storage, it can be retrieved from the main storage. Data retrieved from the main storage is first stored in the next-level storage, and then sent from the next-level storage to the prefetch buffer. Therefore, the data in the next-level storage or the prefetch buffer is dynamically changing.

[0084] Initially, the access status of the addresses in the memory access address mapping table is always "unaccessed (initial)". The access status of these addresses is first determined by data fetch requests. Each time a data fetch request arrives, whether from the cache, prefetch buffer, or storage unit, the final retrieval of data will inevitably change the address in the memory access address mapping table to "accessed (accessed)". Secondly, the address flag status in the memory access address mapping table can also be adjusted based on the data status in the cache and / or next-level storage. Newly called or stored data may displace existing data. When existing data is displaced, the access status of the corresponding address in the memory access address mapping table will change from "accessed (accessed)" to "unaccessed (initial)". Furthermore, if data loss occurs due to system resets or cache congestion leading to data loss in the cache and / or next-level storage, the "accessed (accessed)" status in the memory access address mapping table will change accordingly.

[0085] Through the above process, by setting a data prefetching mechanism with a prefetching step size, when encountering large-scale computations, some data with obvious address contiguousness will be prefetched in advance, thereby reducing the time spent waiting for the next level of storage after cache misses. Furthermore, the prefetching degree can be set to determine the number of addresses selected for prefetching within the prefetching step size, thus adjusting the amount of data prefetched in advance. This further improves the flexibility of data prefetching, and the prefetching degree is dynamically adjusted based on the performance of the prefetching step size over a certain period, making it more adaptable to dynamic changes in the program and avoiding overly aggressive or overly conservative prefetching.

[0086] In one implementation, determining the prefetch stride using access patterns of neighboring addresses of the address to be accessed in step S101 may include:

[0087] Step S201: Use the memory access address mapping table to obtain the address identifier status of the neighboring address. The address identifier status includes the accessed status or the unaccessed status.

[0088] Step S202: Determine the prefetch stride based on the stride interval between the neighboring addresses of the visited state and the address to be visited.

[0089] The memory access address mapping table records the address flag status of adjacent addresses, including "accessed" and "not accessed" states. Since there are only two states, only 1 bit of "0 or 1" data is needed to represent the address flag status. Therefore, the memory access address mapping table can be optimized. That is, the address flag status in the memory access address mapping table only represents two states, reducing resource consumption.

[0090] The principle of prefetch stride calculation is to look up the stride interval forward or backward, starting from the current memory access address. This stride interval can be set in advance, such as 1, 2, or 3. The calculated prefetch stride can also be used for status verification forward or backward, that is, to ensure that the address to be prefetched has not been accessed.

[0091] Combination Figure 3 As shown, the address to be accessed ( Figure 3 The value shown is 0x04 ("Cache miss"), and its state in the memory access address mapping table is "Initial". "Initial" can correspond to no access. Therefore, the address flag status of neighboring addresses can be obtained. For example, if neighboring addresses 0x02 and 0x03 are "accessed", with a determination step size of 1, and if the prefetch level is determined to be 1, then neighboring address 0x05 should be prefetched. If neighboring address 0x05 is "accessed", then the data does not need to be prefetched. If neighboring addresses 0x00 and 0x02 are "accessed", with a determination step size of 2, and if the prefetch level is determined to be 2, then neighboring addresses 0x06 and 0x08 are "Initial", and can be prefetched to update the prefetch request queue. Figure 3 The term "stride" in this context corresponds to the pre-fetched stride in the embodiments of this application.

[0092] In one implementation, step S102, which involves obtaining the cumulative number of occurrences of the prefetched stride and determining the prefetching degree, may include:

[0093] Step S401: Obtain the existing prefetch level N, where N is a positive integer;

[0094] Step S402: If the cumulative number of occurrences of the prefetched step is not less than the corresponding number threshold, N+a is used as the determined prefetching degree, where a is a natural number;

[0095] Step S403: If the cumulative number of times the prefetch step size occurs is less than the corresponding number threshold, N is used as the determined prefetch degree.

[0096] The existing prefetching degree N can be the result of statistics within one clock cycle. Furthermore, a count threshold can be preset. For example, the count threshold can be 3, 4, 5, etc. The prefetching degree N is determined based on the cumulative number of occurrences of the prefetching step size in step S101. For example, if the cumulative number of occurrences of the prefetching step size is not less than the count threshold, then the prefetching degree can be N+a. Generally, a can be 1. Combined with... Figure 3 As shown in the figure, the example is that the determined prefetch step size is 2, and the cumulative number of prefetch steps of 2 is 3. Figure 3 As shown in the figure, if the number of times exceeds the threshold, the prefetching degree changes from 1 time to 2 times. Figure 3The "1+1" method is shown. In addition, if the determined prefetch step size is 1, and the cumulative number of prefetch steps of 1 is 5, if the number of times exceeds the threshold, then the prefetch level will change from the original 3 times to 4 times.

[0097] Furthermore, the natural number 'a' can be dynamically adjusted. For example, if the cumulative number of prefetched steps is high, the value of 'a' can be increased. "Higher" could mean 2 times, 3 times, or similar times the threshold. Conversely, if the existing value of 'a' is high, but the cumulative number of prefetched steps is low, the value of 'a' can be decreased. On the other hand, when the cumulative number of prefetched steps is less than the corresponding threshold, the original 'N' can be used as the prefetching level.

[0098] Therefore, the prefetching level is determined by the cumulative number of steps, which better adapts to dynamic changes in the program and avoids overly aggressive or conservative prefetching. Of course, the prefetching level can also be set to other values ​​such as 1, 2, or 3, without being determined by the cumulative number of steps.

[0099] In one implementation, obtaining the cumulative number of occurrences of the prefetched stride in step S102 may include:

[0100] Step S501: Use the stride queue list to obtain the prefetch stride adoption status of the memory access address mapping table, including whether it is not adopted or has been adopted;

[0101] Step S502: If the adoption status is not adopted, set the cumulative number of occurrences of the prefetched step size to 0;

[0102] Step S503: If the adoption status is already adopted, set the cumulative number of occurrences of the prefetched step size from M to M+1, where M is an integer not less than 0.

[0103] The stride queue list and user storage memory access address mapping table prefetch stride usage. Still combined with... Figure 3 As shown, the stride queue in the example can record prefetched stride 1 and prefetched stride 2. The effective count for prefetched stride 1 is 5, indicating that prefetched stride 1 has appeared a total of 5 times (the cumulative number of appearances corresponds to...). Figure 3(The "effective count" in the text). The effective count for prefetch step size 2 is 2+1 (corresponding to M+1), indicating that the cumulative occurrence of prefetch step size 2 has been 2 times. If the currently determined prefetch step size is still 2, the effective count for prefetch step size 2 changes from 2 times to 3 times. It is easy to understand that if the currently determined prefetch step size is 1, the effective count for prefetch step size 1 changes from 5 times to 6 times. Taking the address to be accessed as 0x04 as an example, if the prefetch step size is 2 and the prefetch level is also 2, it means that starting from the address to be accessed 0x04, the address that needs to be prefetched with a step size of 2 is address 0x06. In addition, since the prefetch level is 2, it means that when the prefetch step size is 2, two prefetches need to be performed, that is, in addition to prefetching the data in address 0x06, it is also necessary to prefetch the data in address 0x08.

[0104] Additionally, if the currently determined prefetch step size is 3, and prefetch step size 3 has not been used previously, the prefetch step size of 3 can be recorded in the step size queue list, and the cumulative count of prefetch step size 3 occurrences can be set to 0, i.e., the effective count can be set to 0. It is easy to understand that if the prefetch step size of 3 occurs again, the cumulative count of prefetch step size 3 occurrences will change from 0 to 1.

[0105] The above-mentioned stride length adjustment process can be performed in cycles based on clock cycles. One clock cycle can be from time T0 to T... i Time (i can be an integer greater than 0). When a clock cycle ends, the entire stride queue can be set to 0.

[0106] In one implementation, it may further include: dynamically adjusting the prefetching degree of the prefetching stride using the results of data prefetching. Specifically, the process of prefetching the degree of the prefetching stride may include:

[0107] Step S601: Based on at least one of the following: the adoption of data prefetching results and historical duration, dynamically adjust the prefetching degree and / or the cumulative occurrence of prefetching steps.

[0108] Step S602: The prefetch address in the prefetch buffer will be loaded with identification information. The identification information will record the prefetch stride used when the current prefetch address is prefetched, such as 1, 2 or 3.

[0109] The result of data prefetching can include whether it has been read or not. For example, the prefetch address in the prefetch buffer may contain an identifier for the prefetch step size. For instance, the prefetch step size loaded at prefetch address 0x04 could be prefetch step size 2, and the prefetch step size loaded at prefetch address 0x03 could be prefetch step size 1.

[0110] If data in the prefetch address is not read within a certain period, the prefetch level and / or the cumulative occurrence count of the prefetch step can be decremented. This period can be a natural time interval, such as 1 second, 2 seconds, etc. Alternatively, it can be measured in clock cycles. For example, if the clock cycle is 1 second, and data is not read for more than 1 / 10 of a second, the prefetch level and / or the cumulative occurrence count of the prefetch step can be decremented. Another approach is to use the clock cycle as the basis, resetting the prefetch level and cumulative occurrence count of all steps to zero at the start of each new clock cycle.

[0111] Conversely, if the prefetch address corresponding to a certain prefetch step is read multiple times, the prefetch level of the prefetch step and / or the cumulative number of occurrences of the prefetch step can be incremented. The incrementing process is the same as the process described above and will not be repeated here.

[0112] In one implementation, it may further include storing data prefetched from the storage unit using a prefetch request queue into a prefetch buffer.

[0113] Combination Figure 2 As shown, data prefetched using the prefetch request queue, if in the next-level storage, is copied from that storage to the prefetch buffer. Then, during data retrieval, it is copied from the prefetch buffer to the cache. Conversely, if the data prefetched using the prefetch request queue is in primary storage, it needs to be copied from primary storage to the next-level storage first, and then copied from the next-level storage to the prefetch buffer during prefetching. The address flag of the data in the prefetch buffer can be set to the prefetch state. If the address to be accessed accesses the cache, the cache determines that there is a cache miss for the data to be read corresponding to the accessed address and generates a data retrieval request containing the data to be read from the accessed address. If the data to be read exists in the prefetch buffer, the data corresponding to the data retrieval request is copied from the prefetch buffer or migrated to the cache.

[0114] In one implementation, it may further include: generating a data acquisition request, which is used to acquire data directly from the storage unit.

[0115] If the address to be accessed accesses the cache, and the cache determines that the data to be read corresponding to the accessed address is missing from the cache, and the prefetch buffer also does not contain the data to be read, then a data retrieval request containing the data to be read can be directly generated to retrieve the data from the storage unit. That is, it can correspond to... Figure 2 Data can be retrieved directly from the next level of storage via the cache, or directly from the main storage via the cache.

[0116] In one implementation, after updating the prefetch request queue, the method further includes deduplicating the prefetch request queue. Deduplicating the prefetch request queue may include:

[0117] Step S701: Compare the updated prefetch request queue with the previous prefetch request queue, and perform deduplication on duplicate data; and / or

[0118] Step S702: Compare the updated prefetch request queue with the data in the prefetch buffer, and perform deduplication on duplicate data.

[0119] One deduplication method involves updating the prefetch request queue, comparing it with the earlier prefetch request queue, and then sequentially accessing the next level of storage for data prefetching. If duplicate data addresses are found, they can be removed from the updated prefetch request queue to complete deduplication. Since there may be multiple prefetch request queues (e.g., 8, 16, etc.), deduplication is also performed by comparing each prefetch request queue with others.

[0120] Another deduplication method involves comparing the updated prefetch request queue with the data in the prefetch buffer after updating the prefetch request queue. If duplicate data addresses are found, they can be removed from the updated prefetch request queue to complete the deduplication.

[0121] In addition, after updating the prefetch request queue, the updated prefetch request queue can be compared with the data in the cache. If duplicate data addresses are found, they can be removed from the updated prefetch request queue to complete deduplication.

[0122] Figure 4 This is a flowchart illustrating a data prefetching method according to another embodiment of this application. It includes the following processes:

[0123] start.

[0124] A cache miss has been detected.

[0125] When a cache miss occurs, prefetching is performed. Prefetching includes calculating the prefetch step size. The specific calculation process is the same as in the previous embodiment and will not be repeated here.

[0126] The calculated prefetched stride is sent to the stride queue.

[0127] In the stride queue, determine whether the prefetched stride has been hit.

[0128] On the one hand, if the pre-fetched step is hit, the cumulative number of occurrences of that pre-fetched step is adjusted. It is adjusted from M times to M+1 times. M is a positive integer.

[0129] Determine if the cumulative occurrence count exceeds a threshold. If it does, adjust the prefetch level from N times to N+1 times, where N is a positive integer. If the cumulative occurrence count does not exceed the threshold, retain N times as the prefetch level.

[0130] On the other hand, if the prefetch step is not hit, the prefetch step is written to the prefetch queue. In the prefetch queue, the cumulative occurrence count is set to 0, and the prefetch degree is set to 1.

[0131] The prefetch request is sent to the prefetch queue. Data prefetching then occurs based on the prefetch queue. After data is prefetched, the data obtained from the prefetch request queue is written to the prefetch buffer. The prefetching process ends.

[0132] Corresponding to the application scenarios and methods provided in the embodiments of this application, the embodiments of this application also provide a data prefetching apparatus. For example... Figure 5 The diagram shown is a structural block diagram of a data prefetching apparatus according to an embodiment of this application. The data prefetching apparatus may include:

[0133] The prefetch stride determination module 501 is used to update the prefetch request queue using the prefetch stride. The prefetch request queue is used to prefetch data from the storage unit.

[0134] The prefetch request queue update module 502 is used to update the prefetch request queue using the prefetch step size. The prefetch request queue is used to prefetch data from the storage unit.

[0135] In one embodiment, the prefetch stride determination module 501 may include:

[0136] The address identifier status acquisition submodule is used to obtain the address identifier status of adjacent addresses using the memory access address mapping table. The address identifier status includes whether the address has been accessed or not.

[0137] The prefetch stride determination submodule is used to determine the prefetch stride based on the stride interval between the neighboring addresses of the visited state and the address to be visited.

[0138] In one embodiment, it may further include a prefetch degree determination module, which is used to obtain the cumulative number of occurrences of the prefetch step and determine the prefetch degree, which is used to characterize the number of prefetch addresses selected using the prefetch step.

[0139] The prefetch request queue update module 502 is also used to update the prefetch request queue using the prefetch step size and prefetch degree.

[0140] In one implementation, the prefetching degree determination module may further include:

[0141] The existing prefetch degree acquisition submodule is used to acquire the existing prefetch degree N, where N is a positive integer;

[0142] The first prefetch degree determination execution submodule is used to determine N+a as the prefetch degree when the cumulative number of occurrences of the prefetch step is not less than the corresponding number threshold, where a is a natural number.

[0143] The second prefetch degree determination execution submodule is used to determine N as the prefetch degree when the cumulative number of prefetch steps is less than the corresponding number threshold.

[0144] In one implementation, the prefetching degree determination module may further include:

[0145] The prefetch stride adoption status acquisition submodule is used to obtain the prefetch stride adoption status of the memory access address mapping table using the stride queue list. The adoption status includes whether it is not adopted or has been adopted.

[0146] The first prefetch step count determination submodule is used to set the prefetch step count to 0 when the adoption status is not adopted.

[0147] The second prefetch step count determination submodule is used to set the prefetch step count from M to M+1 when the adoption status is adopted, where M is an integer not less than 0.

[0148] In one embodiment, a prefetching degree dynamic adjustment module may also be included. This module can be used to dynamically adjust the prefetching degree of the prefetching step and / or the cumulative number of occurrences of the prefetching step based on at least one of the adoption of data prefetching results and historical duration.

[0149] In one implementation, a prefetch buffer may also be included. The prefetch buffer is used to store data prefetched from the storage unit using a prefetch request queue.

[0150] In one embodiment, a data acquisition request generation module may be included, which is used to generate a data acquisition request and copy or migrate the data corresponding to the data acquisition request from the prefetch buffer to the cache.

[0151] In one implementation, the data acquisition request generation module can also be used to: generate a data acquisition request, which is used to directly acquire data from the storage unit.

[0152] In one implementation, a deduplication module may also be included, which is used to deduplicatize the prefetch request queue after updating it.

[0153] The deduplication module may specifically include:

[0154] The first deduplication execution submodule is used to compare the updated prefetch request queue with the previous prefetch request queue to deduplicate duplicate data; and / or

[0155] The second deduplication execution submodule is used to compare the updated prefetch request queue with the data in the prefetch buffer and perform deduplication on duplicate data.

[0156] The functions of each module in each device in the embodiments of this application can be found in the corresponding description in the above method, and they have corresponding beneficial effects, which will not be repeated here.

[0157] Figure 6 This is a block diagram of an electronic device used to implement embodiments of this application. For example... Figure 6 As shown, the electronic device includes a memory 610 and a processor 620. The memory 610 stores a computer program that can run on the processor 620. When the processor 620 executes the computer program, it implements the methods described in the above embodiments. The number of memories 610 and processors 620 can be one or more.

[0158] The electronic device also includes:

[0159] The communication interface 630 is used to communicate with external devices and perform data exchange and transmission.

[0160] If the memory 610, processor 620, and communication interface 630 are implemented independently, they can be interconnected via a bus to communicate with each other. This bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0161] Optionally, in a specific implementation, if the memory 610, processor 620, and communication interface 630 are integrated on a single chip, then the memory 610, processor 620, and communication interface 630 can communicate with each other through an internal interface.

[0162] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method provided in this application.

[0163] This application also provides a chip including a processor for calling and executing instructions stored in a memory, causing a communication device with the chip installed to perform the method provided in this application.

[0164] This application also provides a chip, including: an input interface, an output interface, a processor, and a memory. The input interface, output interface, processor, and memory are connected through an internal connection path. The processor is used to execute code in the memory. When the code is executed, the processor is used to execute the method provided in the application embodiment.

[0165] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0166] Further, optionally, the aforementioned memory may include read-only memory and random access memory. The memory may be volatile memory or non-volatile memory, or may include both. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available. Examples include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Sync Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0167] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0168] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0169] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0170] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0171] The logic and / or steps described in the flowchart or otherwise herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0172] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0173] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0174] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope described in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data prefetching method, characterized in that, include: Obtain the address to be accessed, determine whether there is a cache missing in the data to be read corresponding to the address to be accessed, and if so, determine the prefetch step size by using the access situation of the neighboring addresses of the address to be accessed. The prefetch request queue, which is used to prefetch data from the storage unit, is updated using the prefetch step size. Obtaining the cumulative occurrence count of the prefetch step and determining the prefetch degree includes: obtaining an existing prefetch degree N, where N is a positive integer; if the cumulative occurrence count of the prefetch step is not less than the corresponding count threshold, using N+a as the determined prefetch degree, where a is a natural number; if the cumulative occurrence count of the prefetch step is less than the corresponding count threshold, using N as the determined prefetch degree; the prefetch degree is used to characterize the number of prefetch addresses selected using the prefetch step. The prefetch request queue is updated using the prefetch step size and the prefetch degree.

2. The method according to claim 1, characterized in that, The step of determining the prefetch stride based on the access status of the neighboring addresses of the address to be accessed includes: obtaining the address identifier status of the neighboring addresses using a memory access address mapping table, wherein the address identifier status includes an accessed state or an unaccessed state; and determining the prefetch stride based on the stride interval between the neighboring addresses in the accessed state and the address to be accessed.

3. The method according to claim 1, characterized in that, The step of obtaining the cumulative number of occurrences of the prefetched step includes: The prefetch step size of the memory access address mapping table is obtained using the step size queue list, where the step size includes whether it is not used or has been used. If the adoption condition is not adopted, the cumulative number of occurrences of the pre-fetched step size is set to 0; If the adoption condition is adopted, the cumulative number of occurrences of the pre-fetched step size is set from M to M+1, where M is an integer not less than 0.

4. The method according to claim 1, characterized in that, It also includes: dynamically adjusting the prefetching degree of the prefetching step using the results of the data prefetching; The process of prefetching the prefetch step size includes: The prefetching degree of the prefetching step and / or the cumulative number of occurrences of the prefetching step are dynamically adjusted based on at least one of the adoption of the data prefetching results and the historical duration.

5. The method according to claim 1, characterized in that, Also includes: The data prefetched from the storage unit using the prefetch request queue is stored in the prefetch buffer.

6. The method according to claim 5, characterized in that, Also includes: Generate a data retrieval request, and copy or migrate the data corresponding to the data retrieval request from the prefetch buffer to the cache area.

7. The method according to claim 1, characterized in that, Also includes: A data retrieval request is generated, which is used to retrieve data directly from the storage unit.

8. The method according to claim 1, characterized in that, After updating the prefetch request queue, the process also includes deduplicating the prefetch request queue. The process of deduplicating the prefetch request queue includes: Compare the updated prefetch request queue with the previous prefetch request queue to remove duplicate data; and / or The updated prefetch request queue is compared with the data in the prefetch buffer, and duplicate data is deduplicated.

9. A data prefetching apparatus, characterized in that, include: The prefetch stride determination module is used to obtain the address to be accessed, determine whether there is a cache missing in the data to be read corresponding to the address to be accessed, and if so, determine the prefetch stride by using the access situation of the neighboring addresses of the address to be accessed. A prefetch request queue update module is used to update the prefetch request queue using the prefetch step size; the prefetch request queue is used to prefetch data from the storage unit. The prefetching degree determination module is used to obtain the cumulative number of occurrences of the prefetching step and determine the prefetching degree, including: obtaining an existing prefetching degree N, where N is a positive integer; if the cumulative number of occurrences of the prefetching step is not less than the corresponding number threshold, using N+a as the determined prefetching degree, where a is a natural number; if the cumulative number of occurrences of the prefetching step is less than the corresponding number threshold, using N as the determined prefetching degree; the prefetching degree is used to characterize the number of prefetch addresses selected using the prefetching step; The prefetch request queue update module is further configured to update the prefetch request queue using the prefetch step size and the prefetch degree.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor, when executing the computer program, implements the method of any one of claims 1-8.

11. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of any one of claims 1-8.

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