Method and apparatus for setting cache

Abstract

Embodiments of the present specification provide a method and device for setting cache, wherein the method for setting cache comprises: setting a corresponding cache partition for each flash memory partition of a solid state disk; recording hit information of a read request in evicted data of the cache partition and hit information in the evicted data; using the hit information and read delay of the flash memory partition corresponding to the cache partition, estimating read performance gain brought by a first capacity added to the cache partition, and estimating read performance loss brought by a second capacity reduced from the cache partition; determining a cache partition that needs to be expanded and a cache partition that needs to be reduced based on the read performance gain and the read performance loss of each cache partition; reducing the second capacity from the cache partition that needs to be reduced, and adding the first capacity to the cache partition that needs to be expanded. The capacity of each cache partition is adjusted through the hit information, thereby reducing the access delay of the solid state disk.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, and in particular to a method for setting up a cache. Background Technology

[0002] Solid-state drives (SSDs) are the mainstream storage devices. Thanks to advancements in multi-level cell (MLC) technology, the storage density of flash-based SSDs has rapidly increased. In particular, quad-level cell (QLC) flash-based SSDs have become one of the mainstream storage devices. QLC SSDs are suitable for read-intensive scenarios, such as machine learning, big data analytics, and NoSQL databases. Therefore, optimizing the read performance of QLC SSDs is especially important. Summary of the Invention

[0003] In view of this, embodiments of this specification provide a method for setting a cache. One or more embodiments of this specification also relate to an apparatus for setting a cache, a computing device, a computer-readable storage medium, and a computer program, to address the technical deficiencies existing in the prior art.

[0004] According to a first aspect of the embodiments of this specification, a method for setting a cache is provided, comprising:

[0005] Configure corresponding cache partitions for each of the multiple flash partitions on the solid-state drive;

[0006] Record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data;

[0007] Using the hit information and the read latency of the flash partition corresponding to the cache partition, the read performance gain brought by the first capacity when the cache partition is increased by a first capacity is estimated, and the read performance loss brought by the second capacity when the cache partition is reduced by a second capacity is estimated.

[0008] Based on the read performance gains and losses of each cache partition, determine the cache partitions that need to be expanded and the cache partitions that need to be shrunk.

[0009] Reduce the second capacity in the cache partition that needs to be reduced in size, and increase the first capacity in the cache partition that needs to be expanded.

[0010] According to a second aspect of the embodiments of this specification, an apparatus for setting a cache is provided, comprising:

[0011] The cache partition module is configured as multiple flash partitions of the solid-state drive, with each partition having its own corresponding cache partition.

[0012] The information recording module is configured to record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data;

[0013] The performance calculation module is configured to use the hit information and the read latency of the flash partition corresponding to the cache partition to estimate the read performance gain brought by the first capacity when the cache partition is increased by a first capacity, and to estimate the read performance loss brought by the second capacity when the cache partition is reduced by a second capacity.

[0014] The partition determination module is configured to determine which cache partitions need to be expanded and which need to be shrunk based on the read performance gains and read performance losses of each cache partition.

[0015] The partition adjustment module is configured to reduce the second capacity in cache partitions that need to be scaled down, and increase the first capacity in cache partitions that need to be scaled up.

[0016] According to a third aspect of the embodiments of this specification, a computing device is provided, comprising:

[0017] Memory and processor;

[0018] The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the above-described method for setting a cache.

[0019] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed by a processor, implement the steps of the method for setting a cache described above.

[0020] According to a fifth aspect of the embodiments of this specification, a computer program is provided, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described method for setting a cache.

[0021] This specification provides a method and apparatus for setting up a cache. The method includes: setting up corresponding cache partitions for multiple flash memory partitions of a solid-state drive; recording the hit information of read requests in the data to be evicted and the hit information in the evicted data of the cache partitions; using the hit information and the read latency of the flash memory partitions corresponding to the cache partitions, estimating the read performance gain brought by increasing the capacity of the cache partitions by a first capacity, and estimating the read performance loss brought by reducing the capacity of the cache partitions by a second capacity; determining the cache partitions that need to be expanded and the cache partitions that need to be reduced in size based on the read performance gain and the read performance loss corresponding to each cache partition; reducing the second capacity in the cache partitions that need to be reduced in size, and increasing the first capacity in the cache partitions that need to be expanded in size. As can be seen, this method addresses the significant differences in read latency due to the different flash page types of multiple flash partitions in a solid-state drive. By setting up cache partitions corresponding to the flash partitions and recording the hit information of read requests in the data to be evicted and the hit information in the evicted data of each cache partition, the method estimates the read performance gains corresponding to expansion and the read performance losses corresponding to reduction based on the hit information and the read latency of the flash partitions. In turn, it can adjust the capacity of each cache partition according to the gains and losses, thereby reducing the access latency of the solid-state drive and improving read performance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the storage structure of a method for setting a cache according to an embodiment of this specification;

[0023] Figure 2 This is a flowchart illustrating a method for setting a cache according to one embodiment of this specification;

[0024] Figure 3 This is a schematic diagram of a cache partition for a method of setting up a cache according to an embodiment of this specification;

[0025] Figure 4 This is a flowchart illustrating the process of setting a cache according to one embodiment of this specification;

[0026] Figure 5 This is a schematic diagram of a device for setting a cache according to one embodiment of this specification;

[0027] Figure 6 This is a structural block diagram of a computing device provided in one embodiment of this specification. Detailed Implementation

[0028] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0029] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a,” “described,” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0030] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0031] First, the terms and concepts used in one or more embodiments of this specification will be explained.

[0032] SSD: Solid State Drive.

[0033] SLC: Single-Level Cell.

[0034] MLC: Multi-Level Cell.

[0035] TLC: Triple-Level Cell.

[0036] QLC: Quad-Level Cell, a four-level storage unit.

[0037] P / E Cycle: Program / Erase Cycle, read / write cycle.

[0038] Flash memory is a type of non-volatile memory that can be erased or written multiple times during operation.

[0039] Flash Page: The basic unit of read and write operations on a solid-state drive.

[0040] NAND flash memory is a non-volatile storage technology that retains data even after power is lost.

[0041] Cache: refers to a storage device that enables high-speed data exchange; it acts as a buffer between the flash memory within a solid-state drive and the external environment.

[0042] Solid State Drive (SSD): Also known as an electronic hard drive or solid-state disk, it is a hard drive composed of a control unit and solid-state storage units (DRAM or FLASH chips).

[0043] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory.

[0044] Gray code: In the encoding of a set of numbers, if any two adjacent codes differ by only one bit, then this encoding is called Gray code.

[0045] SLC, MLC, TLC, and QLC are all multi-level storage cell forms of flash memory. Taking QLC flash memory as an example, a QLC flash cell has 16 different states, each corresponding to a voltage range. These 16 states are encoded into 4 bits using Gray Code. Gray Code ensures that adjacent states differ by exactly 1 bit, so voltage shifts generally only result in a 1-bit error, facilitating error correction. Therefore, QLC-based solid-state drives are suitable for read-intensive scenarios such as machine learning, big data analytics, and NoSQL databases. Due to the requirements of NAND flash memory programming steps, the widely used Gray Code is currently unbalanced Gray Code, meaning different pages have different numbers of read voltage levels. For example, in 1-2-6-6 Gray Code, the least significant bit of the flash cell corresponds to only one read voltage level, while the most significant bit corresponds to six read voltage levels. The read latency of the corresponding flash page is positively correlated with the number of read voltage levels; therefore, the read latency differences among the four different flash pages within a QLC solid-state drive are significant. In tests of some products, the four types of QLC flash memory had roughly the same number of pages, but their read latency varied by 1.6 to 4.8 times. This significant difference in read latency between QLC flash memory pages provides considerable room for optimization of QLC SSD read performance.

[0046] Current research on the differences in read performance of flash memory pages in SSDs is limited. One approach involves dynamically identifying data read frequency during operation and migrating frequently accessed data to lower-latency flash memory pages. However, these strategies require statistical analysis of hot and cold data, introducing additional computational overhead. More importantly, adjusting the distribution of data across different types of flash memory pages necessitates additional data migration, effectively increasing the data write volume of the SSD. For high-capacity SSDs based on QLC flash memory, the write amplification overhead introduced by this method is unacceptable due to the extremely poor durability of flash memory cells. Another approach is to maintain a separate queue for each type of flash memory page, placing eligible pages to be migrated into different queues based on read frequency during garbage collection and wear leveling operations. While this strategy avoids write amplification, it still incurs the overhead of hot and cold page identification. Furthermore, data migration only occurs during garbage collection, resulting in a low trigger frequency for read-heavy workloads and limited effectiveness. All these approaches optimize read performance by optimizing flash memory data layout, specifically migrating frequently accessed data to lower-latency pages. These methods have two problems: the overhead of hot and cold data statistics and the additional write amplification caused by data migration. Currently, there is no algorithm that optimizes QLC flash page read performance by combining it with on-disk data caching.

[0047] Based on this, this specification provides a method for setting a cache, and also relates to an apparatus for setting a cache, a computing device, and a computer-readable storage medium, which will be described in detail in the following embodiments.

[0048] See Figure 1 , Figure 1 The diagram illustrates a storage structure for a method of setting up a cache according to an embodiment of this specification. Specifically, it includes a cache and flash memory. The cache includes a read cache and a write cache; the read cache is used for reading data, and the write cache is used for writing data. The flash memory includes a first flash block, a second flash block, a third flash block, and an nth flash block. Further, each flash block includes a first type flash page, a second type flash page, a third type flash page, and a fourth type flash page.

[0049] Within the read cache, four cache partitions are defined, corresponding to different flash page types: the first cache partition, the second cache partition, the third cache partition, and the fourth cache partition. These four partitions cache data for flash pages of types 1, 2, 3, and 4, respectively. Two data structures are defined for each cache partition: a second storage area and a first storage area. The second storage area, located at the end of each cache partition, contains a fixed amount of cached data and is part of the cache partition, including cached data awaiting eviction. The first storage area, located outside each cache partition, is a data structure that stores only metadata. It stores the metadata of the most recently evicted fixed number of data items from the cache partition, occupying minimal storage space.

[0050] This embodiment of the specification sets up a cache partition corresponding to the flash memory partition and records the hit information of each partition. The capacity of each cache partition is then adjusted based on the hit information to reduce the access latency of the solid-state drive.

[0051] See Figure 2 , Figure 2 A flowchart of a method for setting a cache according to an embodiment of this specification is shown, specifically including the following steps.

[0052] Step 202: Set up corresponding cache partitions for each of the multiple flash partitions of the solid-state drive.

[0053] Flash memory can be classified as three-level, four-level, or multi-level storage units. A cache partition can be understood as a partition obtained by dividing a whole cache area.

[0054] In practical applications, flash memory can be QLC flash memory. Each QLC flash memory cell can store 4 bits of information, and each bit belongs to a flash page. There are four types of flash pages in QLC flash memory: High Latency Page (HL Page), Medium-High Latency Page (MHL Page), Medium-Low Latency Page (MLL Page), and Low Latency Page (LL Page). Corresponding to the four types of QLC flash pages, the solid-state drive's data read cache is divided into four partitions, with each partition used to cache only one type of flash page data.

[0055] For example, if a solid-state drive (SSD) uses QLC flash memory and has a cache size of 40GB, then the cache can be divided into four partitions, corresponding to high-latency pages, medium-high-latency pages, medium-low-latency pages, and low-latency pages in the QLC flash memory.

[0056] This specification describes an example of a solid-state drive (SSD) with multiple flash memory partitions, each with a corresponding cache partition. This allows for subsequent calculations of the benefits of adjusting the capacity of the four partitions and the making of capacity adjustment decisions. This provides a fundamental basis for improving the read and write performance of the SSD.

[0057] The specific method for dividing the cache partitions provided in the embodiments of this specification is not limited. For example, in order to ensure that the initial cache partitions corresponding to multiple flash memory partitions of the solid-state drive have the same performance, the cache partitions can be initialized by allocating capacity equally. Specifically, setting corresponding cache partitions for multiple flash memory partitions of the solid-state drive includes: setting cache partitions of the same capacity for multiple flash memory partitions of the solid-state drive according to the principle of one-to-one correspondence; initializing each cache partition; and initializing the hit information of each cache partition.

[0058] The one-to-one correspondence principle can be understood as one flash memory partition corresponding to one cache partition. Hit information can be the number of hits.

[0059] In the above embodiments, to ensure that the initial cache partitions corresponding to multiple flash memory partitions of the solid-state drive have the same performance, an average distribution of the cache is adopted. In practical applications, this can be flexibly configured as needed, and the method provided in this specification does not impose any limitations on this. Furthermore, during the initialization of each cache partition, the read cache can be partitioned and formatted. Taking the four flash memory page types of a QLC solid-state drive as an example, the read cache can be correspondingly divided into four cache partitions. See [link to documentation]. Figure 3 , Figure 3This diagram illustrates a cache partitioning method for setting up a cache. Each cache partition stores data in the form of a linked list, ordered from most frequently used data to least frequently used data. Evicted data is replaced by nodes. The last segment of each partition is labeled as the second storage area. An additional first storage area is maintained for each partition. Specifically, two data structures can be defined: the second storage area and the first storage area. The second storage area includes a fixed number of data entries at the end of each cache partition, and is part of the cache partition. The first storage area includes a data structure maintained outside each cache partition that stores only metadata, such as the metadata of the most recently evicted fixed number of data entries from the cache partition (e.g., LPN, logical page number). Four sets of hit count counters for the second and first storage areas are initialized. The second storage area is part of the cache partition and does not occupy additional DRAM space; the first storage area only stores metadata and occupies very little space.

[0060] For example, if the cache size corresponding to the solid-state drive is 40GB, then the cache is divided into four partitions, corresponding to high-latency pages, medium-high-latency pages, medium-low-latency pages, and low-latency pages in the QLC flash memory, respectively. That is, the initial size of each cache partition is 10GB. The area of ​​the three data nodes at the end of each cache partition is set as the second storage area. The data structure maintained outside each cache partition, which only stores metadata, also has a capacity of three data nodes and is set as the first storage area. And the hit information of each cache partition is initialized, that is, the hit count is set to zero.

[0061] The above embodiment involves multiple flash memory partitions of a solid-state drive, each with a cache partition of the same capacity. This ensures that the initial performance of the cache partitions corresponding to each flash memory partition is the same, thereby improving the accuracy of subsequent revenue calculations.

[0062] Step 204: Record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data.

[0063] The read request is a request to access the flash memory and read data from it. The read request will first access the faster cache; if the data is not found in the cache, it will then access the flash memory.

[0064] This specification's embodiments record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data, enabling subsequent steps to calculate read performance gains and losses based on the hit information.

[0065] In one possible implementation, the record read request includes hit information in the cache partition's pending data and hit information in the already evicted data, including:

[0066] The system records the number of times read requests hit the first storage area of ​​the cache partition, and the number of times read requests hit the second storage area of ​​the cache partition. The first storage area is a storage area of ​​a first size located outside the cache partition and is used to store the identifier of the data evicted from the corresponding cache partition. The second storage area is a storage area of ​​a second size located at the dequeue end of the cache partition. The cache partition is a queue for evicting data according to the Least Recently Used algorithm.

[0067] The first capacity can be the same as or different from the second capacity.

[0068] In practical applications, by counting the read hits of the second storage area, the hit count loss caused by reducing the partition capacity by a fixed size can be estimated; conversely, by counting the read hits of the first storage area, the hit count increase caused by increasing the partition capacity by a fixed size can be estimated. As described in the above embodiments, the first storage area corresponds to the first storage area, and the second storage area corresponds to the second storage area. The second storage area includes a fixed number of data at the end of each cache partition and is part of the cache partition. The first storage area includes a data structure maintained outside each cache partition that stores only metadata, storing metadata of the most recently evicted fixed number of data from the cache partition. The metadata can be logical page numbers. The second storage area is part of the cache partition and does not occupy additional DRAM space; the first storage area only stores metadata and occupies very little space. During operation, the hit counts of the second storage area and the first storage area for each cache partition are counted, for example, during normal read operations on a QLC solid-state drive. When a read request hits the second storage area of ​​the cache partition, the result can be returned directly to the driver layer, and the hit count of the second storage area can be maintained by incrementing the hit count of the second storage area by 1; when a read request hits the first storage area, the hit count of the first storage area can be maintained by incrementing the hit count of the first storage area by 1.

[0069] For example, the last three data nodes of each cache partition are designated as the second storage area. A data structure maintaining only metadata outside each cache partition, also with a capacity of three data nodes, is designated as the first storage area. The hit information for each cache partition is initialized, i.e., the hit count is set to zero. If the data corresponding to a read request exists in the second storage area, the hit count for that second storage area is incremented by one.

[0070] For example, suppose the cache currently contains empty data, and the cache capacity is 3 data nodes. The first access to data marked 1 results in a cache miss because the cache is empty; simultaneously, this data is read from flash memory into the cache. The data in the cache becomes 1. The second access to data marked 1 results in a cache hit because the data already exists in the cache. The third, fourth, and fifth accesses access data marked 2, 3, and 4 respectively, so these data are read from flash memory into the cache, making the cache data marked 2, 3, and 4. The sixth access to data marked 1 results in a cache miss because the current cache data already contains data marked 2, 3, and 4. Therefore, the hit count for the second storage area is 1. For the first storage area, after the cache becomes filled with data marked 2, 3, and 4, since data marked 1 was just evicted, metadata for data marked 1 is added to the first storage area, indicating that data marked 1 was evicted from the cache. If a subsequent read request accesses data marked 1, the hit count for the first storage area is incremented.

[0071] This specification's embodiments estimate the hit count loss caused by reducing the capacity of the second storage area by a fixed amount by statistically analyzing the read hit count. Similarly, it estimates the hit count increase caused by increasing the capacity of the first storage area by a fixed amount by statistically analyzing the read hit count. This simulation calculates the benefits of increasing the cache partition's capacity or the losses of reducing its capacity, thus providing a basis for adjusting the cache partition.

[0072] The metadata of the most recently evicted fixed number of data items is stored in the cache partition. This metadata can be obtained from the evicted data, and the specific implementation method is described below.

[0073] The embodiments in this specification also include:

[0074] In the case of evicting data from the cache partition, the metadata of the evicted data is stored in the first storage area. If the metadata of the data to be read in the read request is the same as the metadata stored in the first storage area, it is determined that the read request has hit the first storage area.

[0075] In this context, evicting data can be understood as deleting data from the cache.

[0076] In practical applications, the data in the cache includes the data ontology and metadata. When the cache partition evicts data, the data ontology is discarded and the metadata is stored in the first storage area.

[0077] For example, the last three data nodes of each cache partition are designated as the second storage area, while a data structure maintaining only metadata outside each cache partition, also with a capacity of three data nodes, is designated as the first storage area. If data A is evicted from the last three data nodes of a cache partition, the data itself of data A is discarded, and the metadata of data A is stored in the first storage area.

[0078] For example, following the above embodiment, after the cache becomes data marked as 2, 3 and 4, since the data marked as 1 was just evicted, the metadata of the data marked as 1 is added to the first storage area, which means that the data marked as 1 has been evicted from the cache.

[0079] The embodiments in this specification store only metadata in the first storage area, which can achieve the effect of simulating increased capacity with a small amount of space and reduce the cost of resource usage.

[0080] When the metadata of the data requested by the read request is data metadata in the first storage area, only the hit count is counted, instead of reading data from the first storage area. Details are as follows.

[0081] The embodiments in this specification also include:

[0082] If the read request is hit in the first storage area, the data to be read is read from the flash partition corresponding to the cache partition of the first storage area.

[0083] The data to be read can be the data that the read request wants to read.

[0084] In practical applications, the first storage area simulates the cache space, rather than the actual cached data. Since the first storage area only contains metadata, the data still needs to be accessed from flash memory; therefore, the first storage area cannot serve read requests. In other words, if a read request "hits" the first storage area, it's actually a metadata hit, so the data still needs to be read from flash memory.

[0085] For example, the cache is currently empty, and its capacity is 3 data nodes. The first access to data marked 1 results in a cache miss because the cache is empty; simultaneously, this data is read from flash memory into the cache. The data in the cache becomes 1. The second access to data marked 1 results in a cache hit because the data already exists in the cache. Subsequent accesses, the third, fourth, and fifth, access data marked 2, 3, and 4 respectively. These data will then be read from flash memory into the cache, and the data in the cache will then be marked 2, 3, and 4.

[0086] In this embodiment, only metadata is stored in the first storage area, which can achieve the effect of simulating increased capacity with a small amount of space. Furthermore, data can be retrieved from the flash memory based on read requests without affecting normal read operations, thus avoiding the problem of being unable to read data.

[0087] Step 206: Using the hit information and the read latency of the flash memory partition corresponding to the cache partition, estimate the read performance gain brought by the first capacity when the cache partition is increased by the first capacity, and estimate the read performance loss brought by the second capacity when the cache partition is reduced by the second capacity.

[0088] Among them, read latency can be the read latency of flash memory.

[0089] Read performance gains refer to the improvement in read performance when the cache is expanded. Read performance losses refer to the reduction in read performance when the cache is shrunk. Read performance can be understood as the ability to provide read services, which can be represented by various metrics, such as the response time of read requests, or the percentage of read requests accessing low-latency memory pages, etc. Representing read performance by read request response time, read performance gains can be seen as the response time saved when the cache is expanded because read requests hit the cache and avoid accessing flash memory. Read performance losses can be seen as the response time consumed when the cache is shrunk because read requests miss the cache and need to access flash memory.

[0090] In practical applications, the read latency of any type of QLC flash page can be a known quantity. During operation, the number of hits in the second memory area and the number of hits in the first memory area of ​​each cache partition are counted, and based on this, the performance loss caused by reducing the capacity of each partition by a fixed size and the performance gain caused by increasing the capacity by a fixed size are calculated.

[0091] For example, if the cache size corresponding to the solid-state drive is 40GB, then this cache is divided into four partitions, corresponding to high-latency pages, medium-high-latency pages, medium-low-latency pages, and low-latency pages in the QLC flash memory, respectively. That is, the initial size of each cache partition is 10GB. The last three data nodes of each cache partition are set as the second storage area. A data structure maintaining only metadata outside each cache partition, also with a capacity of three data nodes, is set as the first storage area. Within one period, the number of hits in the second storage area of ​​cache partition C is 17, while the number of hits in the first storage area of ​​cache partition C is 10. If the read latency M of the flash memory partition corresponding to cache partition C is M, then the read performance gain is 10M, and the read performance loss is 17M.

[0092] The embodiments in this specification utilize statistical data from the second and first storage areas to periodically calculate the capacity adjustment benefits of the four partitions during runtime, thereby enabling capacity adjustment decisions to be made based on these benefits.

[0093] After calculating the benefits, it is necessary to determine which cache partitions to adjust. The specific implementation method is as follows.

[0094] Step 208: Based on the read performance gains and read performance losses of each cache partition, determine the cache partitions that need to be expanded and the cache partitions that need to be shrunk.

[0095] Here, "shrinking capacity" can be understood as reducing the capacity, while "expanding capacity" can be understood as increasing the capacity.

[0096] Specifically, determining which cache partitions need to be expanded and which need to be scaled down based on the read performance gains and losses corresponding to each cache partition includes:

[0097] Compare the read performance gains of each cache partition, and select the cache partition that needs to be expanded based on the comparison results;

[0098] Compare the read performance losses of each cache partition, and select the cache partition that needs to be scaled down based on the comparison results, wherein the read performance gain of the cache partition that needs to be scaled up is greater than the read performance loss of the cache partition that needs to be scaled down.

[0099] In practical applications, based on the hit counts of the second and first storage areas in the previous cycle, and combined with the corresponding flash page read latency, the expansion gains and shrinkage losses for each type of cache partition are calculated. Capacity adjustment decisions are then made accordingly.

[0100] For example, if the cache size corresponding to the solid-state drive is 40GB, then the cache is divided into four partitions, corresponding to high-latency pages, medium-high-latency pages, medium-low-latency pages, and low-latency pages in the QLC flash memory, respectively. That is, the initial size of each cache partition is 10GB. The last three data nodes of each cache partition are set as the second storage area. A data structure maintaining only metadata outside each cache partition, also with a capacity of three data nodes, is set as the first storage area. Within one period, the number of hits in the second storage area of ​​cache partition C is 17, while the number of hits in the first storage area of ​​cache partition C is 10. If the read latency of the flash memory partition corresponding to cache partition C is M, then the read performance gain is 10M, and the read performance loss is 17M. The number of hits in the second storage area of ​​cache partition C1 is 12, while the number of hits in the first storage area of ​​cache partition C1 is 19. If the read latency of the flash memory partition corresponding to cache partition C1 is M, then the read performance gain is 19M, and the read performance loss is 12M. The hit count for the second storage area in cache partition C2 is 56, while the hit count for the first storage area in cache partition C2 is 32. If the read latency of the flash partition corresponding to cache partition C2 is M, then the read performance gain is 32M, and the read performance loss is 56M. The hit count for the second storage area in cache partition C3 is 96, while the hit count for the first storage area in cache partition C3 is 8. If the read latency of the flash partition corresponding to cache partition C3 is M, then the read performance gain is 8M, and the read performance loss is 96M. Based on the read performance gain, determine which cache partitions need to be expanded; based on the read performance loss, determine which cache partitions need to be scaled down.

[0101] The embodiments in this specification compare the read performance gains corresponding to each cache partition and select the cache partition that needs to be expanded based on the comparison results; compare the read performance losses corresponding to each cache partition and select the cache partition that needs to be shrunk based on the comparison results, which can improve the degree of performance improvement.

[0102] Preferably, the step of selecting the cache partition that needs to be expanded based on the comparison result includes:

[0103] Based on the comparison results, the cache partition with the greatest read performance benefit is selected as the cache partition that needs to be expanded.

[0104] The step of selecting the cache partition that needs to be scaled down based on the comparison results includes:

[0105] Based on the comparison results, the cache partition with the least read performance loss is selected as the cache partition that needs to be reduced in size.

[0106] In practical applications, the partition with the least loss can be reduced in size, while the partition with the greatest benefit can be increased in size.

[0107] For example, if the cache size corresponding to the solid-state drive is 40GB, then the cache is divided into four partitions, corresponding to high-latency pages, medium-high-latency pages, medium-low-latency pages, and low-latency pages in the QLC flash memory, respectively. That is, the initial size of each cache partition is 10GB. The last three data nodes of each cache partition are set as the second storage area. A data structure maintaining only metadata outside each cache partition, also with a capacity of three data nodes, is set as the first storage area. Within one period, the number of hits in the second storage area of ​​cache partition C is 17, while the number of hits in the first storage area of ​​cache partition C is 10. If the read latency of the flash memory partition corresponding to cache partition C is M, then the read performance gain is 10M, and the read performance loss is 17M. The number of hits in the second storage area of ​​cache partition C1 is 12, while the number of hits in the first storage area of ​​cache partition C1 is 19. If the read latency of the flash memory partition corresponding to cache partition C1 is M, then the read performance gain is 19M, and the read performance loss is 12M. The hit count for the second storage area in cache partition C2 is 56, while the hit count for the first storage area in cache partition C2 is 32. If the read latency of the flash partition corresponding to cache partition C2 is M, then the read performance gain is 32M, and the read performance loss is 56M. The hit count for the second storage area in cache partition C3 is 96, while the hit count for the first storage area in cache partition C3 is 8. If the read latency of the flash partition corresponding to cache partition C3 is M, then the read performance gain is 8M, and the read performance loss is 96M. Select the partition with the greatest performance gain: cache partition C2; select the partition with the smallest performance loss: cache partition C1. Use cache partition C1 as the partition to be shrunk, and use cache partition C2 as the partition to be expanded.

[0108] The embodiments in this specification reduce the partition size with the least loss and increase the partition size with the greatest benefit, so that the performance improvement can achieve a better effect.

[0109] Step 210: Reduce the second capacity in the cache partition that needs to be reduced in size, and increase the first capacity in the cache partition that needs to be expanded.

[0110] In practical applications, during system operation, based on the hit count statistics of the second and first storage areas, the performance gains and losses of the four cache partitions are periodically calculated, and the partition x with the smallest performance loss and the partition y with the largest performance gain are selected. The capacity of partition x is then transferred to partition y.

[0111] Continuing with the previous example, within one period, the number of hits in the second storage area of ​​cache partition C is 17, while the number of hits in the first storage area of ​​cache partition C is 10. If the read latency of the flash partition corresponding to cache partition C is M, then the read performance gain is 10M, and the read performance loss is 17M. The number of hits in the second storage area of ​​cache partition C1 is 12, while the number of hits in the first storage area of ​​cache partition C1 is 19. If the read latency of the flash partition corresponding to cache partition C1 is M, then the read performance gain is 19M, and the read performance loss is 12M. The number of hits in the second storage area of ​​cache partition C2 is 56, while the number of hits in the first storage area of ​​cache partition C2 is 32. If the read latency of the flash partition corresponding to cache partition C2 is M, then the read performance gain is 32M, and the read performance loss is 56M. The number of hits in the second storage area of ​​cache partition C3 is 96, while the number of hits in the first storage area of ​​cache partition C3 is 8. If the read latency M of the flash partition corresponding to cache partition C3, then the read performance gain is 8M and the read performance loss is 96M. Select the partition with the greatest performance gain: cache partition C2, and select the partition with the smallest performance loss: cache partition C1. Use cache partition C1 as the partition to be shrunk, and cache partition C2 as the partition to be expanded. Then, reduce the capacity of cache partition C1 by a second size, and increase the capacity of cache partition C2 by a first size.

[0112] For example, the hit count of the second storage area in cache partition C1 is 12, while the hit count of the first storage area in cache partition C1 is 19. If the read latency of the flash partition corresponding to cache partition C1 is M, then the read performance gain is 19M, and the read performance loss is 12M. The hit count of the second storage area in cache partition C2 is 56, while the hit count of the first storage area in cache partition C2 is 32. If the read latency of the flash partition corresponding to cache partition C2 is M, then the read performance gain is 32M, and the read performance loss is 56M. The hit count of the second storage area in cache partition C3 is 96, while the hit count of the first storage area in cache partition C3 is 88. If the read latency of the flash partition corresponding to cache partition C3 is M, then the read performance gain is 88M, and the read performance loss is 96M. The partition with the greatest performance gain is cache partition C3, and the partition with the smallest performance loss is also cache partition C3. Cache partition C3 is selected as the partition to be shrunk, and cache partition C3 is selected as the partition to be expanded; no adjustments are made.

[0113] The embodiments in this specification reduce the second capacity in the cache partition that needs to be shrunk and increase the first capacity in the cache partition that needs to be expanded, which can increase the hit rate and thus reduce the latency of reading data.

[0114] In one possible implementation, reducing the second capacity in the cache partition that needs to be scaled down and increasing the first capacity in the cache partition that needs to be scaled up includes:

[0115] In response to the cache partition that needs to be expanded receiving a read request, it is determined whether the read request has read the corresponding data from the cache partition that needs to be expanded;

[0116] If not, reduce the preset unit capacity in the cache partition that needs to be reduced, where the second capacity is an integer multiple of the preset unit capacity, and the first capacity is equal to the second capacity; and increase the preset unit capacity in the cache partition that needs to be expanded.

[0117] Determine whether the increased capacity of the cache partition that needs to be expanded has reached the second capacity;

[0118] If the desired result is not achieved, return to the step of responding to the read request received by the cache partition that needs to be expanded, and determining whether the read request has retrieved the corresponding data from the cache partition that needs to be expanded.

[0119] The preset unit capacity can be a set unit size, such as a data node, which can be understood as the data of a flash page.

[0120] In practical applications, to avoid performance fluctuations caused by cache capacity adjustments, a gradual adjustment strategy can be adopted. The specific steps are as follows: First, select a shrinking partition x and an expanding partition y, and record the capacity w to be adjusted. During subsequent system read and write operations, if a read miss occurs in the read cache partition y, one data node in x is evicted, providing space for a data node in partition y, and the capacity w to be adjusted is updated to w-1. When the capacity w to be adjusted reaches 0, the capacity adjustment for this cycle ends, and the hit count statistics for the next cycle begin.

[0121] For example, consider cache partition C1 as the partition to be shrunk and cache partition C2 as the partition to be expanded. This requires reducing the capacity of cache partition C1 by three data nodes and increasing the capacity of cache partition C2 by three data nodes. If a cache miss occurs in cache partition C2, delete the capacity of one data node in the first storage area of ​​cache partition C1 and add that data node's capacity to cache partition C2. Continue deleting one data node from the first storage area of ​​cache partition C1 if a cache miss occurs in cache partition C2, until all three data nodes in the first storage area of ​​cache partition C1 are removed and their capacity added to cache partition C2.

[0122] The embodiments in this specification adopt a gradual adjustment strategy to smoothly adjust the partition capacity and avoid introducing cache hit rate jitter during the adjustment process.

[0123] After reducing the second capacity in the cache partition that needs to be scaled down and increasing the first capacity in the cache partition that needs to be scaled up, the method further includes:

[0124] Reset the hit information of the read request in the cache partition, and return to the step of recording the hit information of the read request in the cache partition's pending data and the hit information in the already evicted data.

[0125] Resetting the read request's hit information in the cache partition can be understood as resetting the hit count to zero.

[0126] In practical applications, after one cycle of capacity adjustment is completed, the hit count for the next cycle begins to be counted in order to carry out the capacity adjustment for the next cycle.

[0127] For example, cache partition C1 is designated as the partition to be scaled down, and cache partition C2 is designated as the partition to be scaled up. This requires reducing the capacity of cache partition C1 by three data nodes and increasing the capacity of cache partition C2 by three data nodes. If a cache miss occurs in cache partition C2, the capacity of one data node in the first storage area of ​​cache partition C1 is removed, and the capacity of this one data node is added to cache partition C2. This process continues until all three data nodes in the first storage area of ​​cache partition C1 are removed and their capacities are added to cache partition C2. After adding the capacity of three data nodes to cache partition C2, the hit counts for both the first and second storage areas are reset to zero. The system continues to record the hit information of read requests in the cache partitions' pending-evicting data and the hit information of evicted data.

[0128] It should be noted that the above embodiments can be used simultaneously with existing data layout-based solutions.

[0129] This specification provides a method and apparatus for setting up a cache. The method includes: setting up corresponding cache partitions for multiple flash memory partitions of a solid-state drive; recording hit information of read requests in data to be evicted and hit information in evicted data of the cache partitions; using the hit information and the read latency of the flash memory partitions corresponding to the cache partitions, estimating the read performance gain brought by increasing the capacity of the cache partitions by a first capacity, and estimating the read performance loss brought by reducing the capacity of the cache partitions by a second capacity; determining the cache partitions that need to be expanded and the cache partitions that need to be reduced in size based on the read performance gain and the read performance loss corresponding to each cache partition; reducing the second capacity in the cache partitions that need to be reduced in size, and increasing the first capacity in the cache partitions that need to be expanded in size. By setting up cache partitions corresponding to the flash memory partitions and recording the hit information of each partition, the capacity of each cache partition can be adjusted based on the hit information to reduce the access latency of the solid-state drive.

[0130] The following is in conjunction with the appendix Figure 4 Taking the application of the cache setting method provided in this specification to QLC flash memory as an example, the cache setting method will be further explained. Figure 4 The present specification illustrates a flowchart of a method for setting a cache according to an embodiment, which includes the following steps.

[0131] Step 402: Read cache partition format.

[0132] In practical applications, the read cache first needs to be partitioned and formatted. The QLC SSD's read cache is divided into four cache partitions, with the last segment of each partition designated as the second storage area. For each partition, a separate first storage area is maintained. Four hit counters for the second and first storage areas are initialized.

[0133] Step 404: Count during read operation.

[0134] In practical applications, QLC SSDs perform normal read operations. When a read request hits the second storage area of ​​the cache partition, the result can be directly returned to the upper layer, and the hit count for the corresponding second storage area is maintained (incremented by 1). When a read request hits the first storage area, the hit count for the corresponding first storage area is maintained (incremented by 1), but since the first storage area only contains metadata, the data still needs to be accessed from the flash memory.

[0135] Step 406: Partition capacity adjustment strategy.

[0136] In practical applications, based on the hit counts of the second and first storage areas in the previous cycle, and combined with the corresponding flash page read latency, the expansion gains and shrinkage losses of each type of cache partition are calculated. Based on this, a capacity adjustment decision is made: the partition with the least loss is reduced in size, while the partition with the greatest gain is increased in size.

[0137] Step 408: Gradually adjust the cache partition capacity.

[0138] In practical applications, capacity adjustments are made based on the results of capacity adjustment decisions during subsequent read request executions. If a read request accesses a QLC flash page corresponding to the partition to be expanded and a read request miss occurs, then one cache node of the partition to be scaled down is evicted, thus completing the capacity adjustment of one cache node.

[0139] This embodiment of the specification sets up a cache partition corresponding to the flash memory partition and records the hit information of each partition. The capacity of each cache partition is then adjusted based on the hit information to reduce the access latency of the solid-state drive.

[0140] Corresponding to the above method embodiments, this specification also provides embodiments of a device for setting a cache. Figure 5 A schematic diagram of a device for setting a cache, according to one embodiment of this specification, is shown. Figure 5 As shown, the device includes:

[0141] The cache partition module 502 is configured as multiple flash partitions of the solid-state drive, with corresponding cache partitions set for each.

[0142] Information recording module 504 is configured to record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data;

[0143] The performance calculation module 506 is configured to use the hit information and the read latency of the flash memory partition corresponding to the cache partition to estimate the read performance gain brought by the first capacity when the cache partition is increased by a first capacity, and to estimate the read performance loss brought by the second capacity when the cache partition is reduced by a second capacity.

[0144] The partition determination module 508 is configured to determine the cache partitions that need to be expanded and the cache partitions that need to be shrunk based on the read performance gains and read performance losses of each cache partition.

[0145] The partition adjustment module 510 is configured to reduce the second capacity in the cache partition that needs to be shrunk, and increase the first capacity in the cache partition that needs to be expanded.

[0146] In one possible implementation, the information recording module 504 is further configured as follows:

[0147] The system records the number of times read requests hit the first storage area of ​​the cache partition, and records the number of times read requests hit the second storage area of ​​the cache partition. The first storage area is a storage area of ​​a first size located outside the cache partition and is used to store the identifier of the data evicted from the corresponding cache partition. The second storage area is a storage area of ​​a second size located at the dequeue end of the cache partition. The cache partition is a queue for evicting data according to the Least Recently Used algorithm.

[0148] The step of reducing the second capacity in the cache partition that needs to be scaled down includes:

[0149] Reduce the second capacity located in the second storage area in the cache partition that needs to be scaled down.

[0150] In one possible implementation, the information recording module 504 is further configured as follows:

[0151] In the case of evicting data from the cache partition, the metadata of the evicted data is stored in the first storage area. If the metadata of the data to be read in the read request is the same as the metadata stored in the first storage area, it is determined that the read request has hit the first storage area.

[0152] In one possible implementation, the information recording module 504 is further configured as follows:

[0153] If the read request is hit in the first storage area, the data to be read is read from the flash partition corresponding to the cache partition of the first storage area.

[0154] In one possible implementation, the partition determination module 508 is also configured as follows:

[0155] Compare the read performance gains of each cache partition, and select the cache partition that needs to be expanded based on the comparison results;

[0156] Compare the read performance losses of each cache partition, and select the cache partition that needs to be scaled down based on the comparison results, wherein the read performance gain of the cache partition that needs to be scaled up is greater than the read performance loss of the cache partition that needs to be scaled down.

[0157] In one possible implementation, the partition determination module 508 is also configured as follows:

[0158] Based on the comparison results, the cache partition with the greatest read performance benefit is selected as the cache partition that needs to be expanded.

[0159] The step of selecting the cache partition that needs to be scaled down based on the comparison results includes:

[0160] Based on the comparison results, the cache partition with the least read performance loss is selected as the cache partition that needs to be reduced in size.

[0161] In one possible implementation, the partition adjustment module 510 is also configured as follows:

[0162] In response to the cache partition that needs to be expanded receiving a read request, it is determined whether the read request has read the corresponding data from the cache partition that needs to be expanded;

[0163] If not, reduce the preset unit capacity in the cache partition that needs to be reduced, where the second capacity is an integer multiple of the preset unit capacity, and the first capacity is equal to the second capacity; and increase the preset unit capacity in the cache partition that needs to be expanded.

[0164] Determine whether the increased capacity of the cache partition that needs to be expanded has reached the second capacity;

[0165] If not, return to the step of responding to the read request received by the cache partition that needs to be expanded, and determining whether the read request has read the corresponding data from the cache partition that needs to be expanded.

[0166] In one possible implementation, the cache partitioning module 502 is also configured as follows:

[0167] Following the principle of one-to-one correspondence, cache partitions of the same capacity are set up for the multiple flash partitions of the solid-state drive;

[0168] Initialize each cache partition and initialize the hit information for each cache partition;

[0169] After reducing the second capacity in the cache partition that needs to be scaled down and increasing the first capacity in the cache partition that needs to be scaled up, the method further includes:

[0170] Reset the hit information of the read request in the cache partition, and return to the step of recording the hit information of the read request in the cache partition's pending data and the hit information in the already evicted data.

[0171] This specification provides a method and apparatus for setting up a cache. The apparatus for setting up the cache includes: setting up corresponding cache partitions for multiple flash memory partitions of a solid-state drive; recording hit information of read requests in data to be evicted and hit information in evicted data of the cache partitions; using the hit information and the read latency of the flash memory partitions corresponding to the cache partitions, estimating the read performance gain brought by increasing the capacity of the cache partitions by a first capacity, and estimating the read performance loss brought by reducing the capacity of the cache partitions by a second capacity; determining the cache partitions that need to be expanded and the cache partitions that need to be reduced in size based on the read performance gain and read performance loss corresponding to each cache partition; reducing the second capacity in the cache partitions that need to be reduced in size, and increasing the first capacity in the cache partitions that need to be expanded in size. By setting up cache partitions corresponding to the flash memory partitions and recording the hit information of each partition, the capacity of each cache partition can be adjusted based on the hit information to reduce the access latency of the solid-state drive.

[0172] The above is an illustrative scheme of a cache setting device according to this embodiment. It should be noted that the technical solution of this cache setting device and the technical solution of the cache setting method described above belong to the same concept. For details not described in detail in the technical solution of the cache setting device, please refer to the description of the technical solution of the cache setting method described above.

[0173] Figure 6 A structural block diagram of a computing device 600 according to one embodiment of this specification is shown. The components of the computing device 600 include, but are not limited to, a memory 610 and a processor 620. The processor 620 is connected to the memory 610 via a bus 630, and a database 650 is used to store data.

[0174] The computing device 600 also includes an access device 640, which enables the computing device 600 to communicate via one or more networks 660. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. The access device 640 may include one or more of any type of wired or wireless network interface (e.g., a network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Wi-MAX (Worldwide Interoperability for Microwave Access) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, and so on.

[0175] In one embodiment of this application, the aforementioned components of the computing device 600 and Figure 6 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 6 The block diagram of the computing device shown is for illustrative purposes only and is not intended to limit the scope of this application. Those skilled in the art can add or replace other components as needed.

[0176] The computing device 600 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 600 can also be a mobile or stationary server.

[0177] The processor 620 is configured to execute the following computer-executable instructions, which, when executed by the processor, implement the steps of the above-described method for setting the cache.

[0178] The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the above-described method for setting a cache belong to the same concept. For details not described in detail in the technical solution of the computing device, please refer to the description of the technical solution of the above-described method for setting a cache.

[0179] An embodiment of this specification also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the above-described method for setting a cache.

[0180] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium and the technical solution of the above-described method for setting a cache belong to the same concept. For details not described in detail in the technical solution of the storage medium, please refer to the description of the technical solution of the above-described method for setting a cache.

[0181] An embodiment of this specification also provides a computer program, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described method for setting a cache.

[0182] The above is an illustrative example of a computer program according to this embodiment. It should be noted that the technical solution of this computer program and the technical solution of the above-described method for setting a cache belong to the same concept. Details not described in detail in the computer program's technical solution can be found in the description of the technical solution of the above-described method for setting a cache.

[0183] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0184] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0185] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0186] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0187] The preferred embodiments disclosed above are merely illustrative of this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. A method for setting up a cache, comprising: Configure corresponding cache partitions for each of the multiple flash partitions on the solid-state drive; The record read request hit information in the cache partition's pending data and hit information in the cache partition's evicted data includes: recording the number of hits of the read request in the first storage area of ​​the cache partition, and recording the number of hits of the read request in the second storage area of ​​the cache partition. The first storage area is a storage area of ​​a first capacity located outside the cache partition and used to store the identifier of the data evicted from the corresponding cache partition. The second storage area is a storage area of ​​a second capacity located at the dequeue end of the cache partition. The cache partition is a queue for evicting data according to the Least Recently Used algorithm. Using the number of hits in the first storage area, the number of hits in the second storage area, and the read latency of the flash memory partition corresponding to the cache partition, the read performance gain brought by the first capacity when the first storage area is increased to the cache partition is estimated, and the read performance loss brought by the second capacity when the second storage area is reduced to the cache partition is estimated. Based on the read performance gains and losses of each cache partition, determine the cache partitions that need to be expanded and the cache partitions that need to be shrunk. Reduce the second capacity in the cache partition that needs to be reduced in size, and increase the first capacity in the cache partition that needs to be expanded.

2. The method according to claim 1, wherein reducing the second capacity in the cache partition that needs to be scaled down includes: Reduce the second capacity located in the second storage area in the cache partition that needs to be scaled down.

3. The method according to claim 2, further comprising: In the case of evicting data from the cache partition, the metadata of the evicted data is stored in the first storage area. If the metadata of the data to be read in the read request is the same as the metadata stored in the first storage area, it is determined that the read request has hit the first storage area.

4. The method according to claim 3, further comprising: If the read request is hit in the first storage area, the data to be read is read from the flash partition corresponding to the cache partition of the first storage area.

5. The method according to claim 1, wherein determining the cache partitions that need to be expanded and the cache partitions that need to be scaled down based on the read performance gains and read performance losses corresponding to each cache partition includes: Compare the read performance gains of each cache partition, and select the cache partition that needs to be expanded based on the comparison results; Compare the read performance losses of each cache partition, and select the cache partition that needs to be scaled down based on the comparison results, wherein the read performance gain of the cache partition that needs to be scaled up is greater than the read performance loss of the cache partition that needs to be scaled down.

6. The method according to claim 5, wherein selecting the cache partition that needs to be expanded based on the comparison result includes: Based on the comparison results, the cache partition with the greatest read performance benefit is selected as the cache partition that needs to be expanded. The step of selecting the cache partition that needs to be scaled down based on the comparison results includes: Based on the comparison results, the cache partition with the least read performance loss is selected as the cache partition that needs to be reduced in size.

7. The method according to claim 1, wherein reducing the second capacity in the cache partition that needs to be scaled down and increasing the first capacity in the cache partition that needs to be scaled up comprises: In response to the cache partition that needs to be expanded receiving a read request, it is determined whether the read request has read the corresponding data from the cache partition that needs to be expanded; If not, reduce the preset unit capacity in the cache partition that needs to be reduced, where the second capacity is an integer multiple of the preset unit capacity, and the first capacity is equal to the second capacity; and increase the preset unit capacity in the cache partition that needs to be expanded. Determine whether the increased capacity of the cache partition that needs to be expanded has reached the second capacity; If not, return to the step of responding to the read request received by the cache partition that needs to be expanded, and determining whether the read request has read the corresponding data from the cache partition that needs to be expanded.

8. The method according to claim 1, wherein the plurality of flash memory partitions of the solid-state drive are respectively configured with corresponding cache partitions, including: Following the principle of one-to-one correspondence, cache partitions of the same capacity are set up for the multiple flash partitions of the solid-state drive; Initialize each cache partition and initialize the hit information for each cache partition; After reducing the second capacity in the cache partition that needs to be scaled down and increasing the first capacity in the cache partition that needs to be scaled up, the method further includes: Reset the hit information of the read request in the cache partition, and return to the step of recording the hit information of the read request in the cache partition's pending data and the hit information in the already evicted data.

9. A buffer setting device, comprising: The cache partition module is configured as multiple flash partitions of the solid-state drive, with each partition having its own corresponding cache partition. The information recording module is configured to record the hit information of read requests in the cache partition's data to be evicted and the hit information in the evicted data; The information recording module is further configured to record the number of times a read request hits the first storage area of ​​the cache partition, and to record the number of times a read request hits the second storage area of ​​the cache partition. The first storage area is a storage area of ​​a first capacity located outside the cache partition and used to store the identifier of data evicted from the corresponding cache partition. The second storage area is a storage area of ​​a second capacity located at the dequeue end of the cache partition. The cache partition is a queue for evicting data according to the Least Recently Used algorithm. The performance calculation module is configured to use the number of hits in the first storage area, the number of hits in the second storage area, and the read latency of the flash memory partition corresponding to the cache partition to estimate the read performance gain brought by the first capacity when the first storage area is increased to the cache partition, and to estimate the read performance loss brought by the second capacity when the second storage area is reduced to the cache partition. The partition determination module is configured to determine which cache partitions need to be expanded and which need to be shrunk based on the read performance gains and read performance losses of each cache partition. The partition adjustment module is configured to reduce the second capacity in cache partitions that need to be scaled down, and increase the first capacity in cache partitions that need to be scaled up.

10. A computing device, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the method for setting a cache as described in any one of claims 1 to 8.

11. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the method for setting a cache as described in any one of claims 1 to 8.

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