A non-aligned transmission network interface architecture for network-on-chip slave devices

Abstract

The application relates to a non-aligned transmission network interface architecture for a network-on-chip slave device, mainly comprising an asynchronous bus bridge, a non-aligned protocol transmission conversion (data splicing and splitting) module, a channel converter, a request FIFO and an ID latch, wherein the non-aligned protocol conversion module can solve the problem that the address alignment rules of the slave device IP core and the address alignment rules of the network-on-chip interface protocol do not match, and special module design is carried out for all address offsets, so that the data transmission delay is reduced and the throughput is increased; the asynchronous bus bridge can synchronize data and is isolated from the data processing part at the back end, so that flow control / correction / packet filtering and the like functions can be added on the bus bridge; the ID lock and the request FIFO can complete the processing of different ID Outstanding transmissions and support the related slave device IP connected with the AXI-FULL bus.

Description

Technical Field

[0001] This invention relates to a communication method between an on-chip network and a slave device, and more particularly to a non-aligned transmission network interface architecture for on-chip network slave devices. Background Technology

[0002] With the development of digital integrated circuits, System-on-Chip (SoC, which integrates multiple functional modules onto a single silicon chip) has become almost a necessary solution for realizing high-performance systems. Manufacturers are continuously increasing the scale of SoCs to meet users' demands for product performance. However, due to limitations such as manufacturing processes, Moore's Law (the rule that the number of transistors that can be placed on an integrated circuit doubles approximately every 24 months) is gradually becoming ineffective. This makes the cost and development cycle of scaling up integrated circuits on a single silicon chip extremely high.

[0003] The future of integrated circuits will move towards multi-die integration, which involves interconnecting and assembling multiple functionally distinct, verified, and unpackaged chip components, and then packaging them into a single chip within a single package, thus forming a network on package (NoP). These dies can be manufactured using different processes and come from different manufacturers, thereby significantly shortening and reducing development cycles and complexity.

[0004] When designing the slave device interface of NoP, the address alignment rules of some slave device IP cores are different from those of the NoP protocol, which causes the software to incur additional overhead for packet splitting, affecting the efficiency of data transmission.

[0005] In NoP, main devices such as DSP and AI chips have a high frequency of random read and write operations on DDR memory, often involving read and write operations at the word level. For DDR memory, the full bus width of the IP core needs to be used to achieve its maximum efficiency. Therefore, splitting and splicing the data at the hardware level is a more reasonable solution. Summary of the Invention

[0006] To address the above issues, a non-aligned transmission network interface architecture for on-chip network slave devices is proposed. This architecture mainly consists of five parts: an asynchronous bus bridge, a non-aligned protocol transmission conversion (data splicing and splitting) module, a channel converter (packet encoder and packet decoder), a request FIFO, and an ID latch. The asynchronous bus bridge module is mainly responsible for signal transmission in the asynchronous clock domain. The non-aligned protocol transmission conversion (data splicing and splitting) module mainly completes the splicing and splitting of data in the case of address non-alignment. The channel converter is used to pack and unpack network data packets. The request FIFO is used to store data for requesting channels. The ID latch is used to implement outstanding transmission of different IDs.

[0007] like Figure 1 As shown, the NoD-Router (NoD's router node) has two ports: a CDI data input port and a CDO data output port. Each port includes a clock signal, a data signal, and Valid and Ready handshake signals.

[0008] The signals from the CDO port of the NoD-Router are transmitted to the CDI interface of the Channel Converter via the Async Bridge module in the Slave Interface, and then enter the Write Channel Converter. The Write Channel Converter is connected to the Packet Decoder, Spliter / Merger, and the write channel of the target bus (Slave IP bus) (e.g., AXI's W and AW channels). When decoding the packet header, it compares the Transfer ID (TID) with the corresponding bit in the ID latch. If the corresponding bit in the ID latch is 1, it indicates that the ID transmission is preempted. At this time, the Write Channel Converter pauses the pipeline, waiting for the ID latch to unlock (i.e., the previous corresponding ID transmission is complete), and then proceeds with the transmission of this related ID, while simultaneously sending request information (including information from the header micro-chip and part of the body micro-chip) to the request FIFO. The data splitter / merger primarily splices / splits data based on the starting address and length to complete the adaptation of unaligned transmission.

[0009] The signals of the CDI port of the NoD-Router are transmitted through the CDO channel of the Channel Converter via the Async Bridge module in the Slave Interface. The CDO channel of the Channel Converter is connected to the read / response channel (e.g., AXI's R, AR, and B channels) of the target bus (slave device IP bus) in the Read / Response Channel Converter, and to the Spliter / Merger and Packet Encoder. When sending a read / write response packet, the request information corresponding to the ID (including information from the header fragment and part of the body fragment) is extracted from the FIFO, then reassembled into the header fragment and part of the body fragment, and the ID latch is released (the corresponding bit is set to 0). Attached Figure Description

[0010] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0011] Figure 1 This is a flowchart of an unaligned transmission network interface for on-chip network slave devices according to the present invention; Figure 2 This is a flowchart illustrating a typical application scenario of the non-aligned network transmission interface of the device, as described in this invention. Figure 3 This is a schematic diagram illustrating data splicing under several different address offsets relative to the alignment position in this invention; Figure 4 This is a schematic diagram of the integration scheme of the data splicing / splitting module in this invention. Detailed Implementation

[0012] The following description, in conjunction with the accompanying drawings, illustrates examples of the present invention. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0013] This invention proposes an unaligned transmission network interface architecture for on-chip network slave devices. This architecture mainly consists of five parts: an asynchronous bus bridge, an unaligned protocol transmission conversion (data splicing and splitting) module, a channel converter (packet encoder and packet decoder), a request FIFO, and an ID latch. The asynchronous bus bridge module is mainly responsible for signal transmission in the asynchronous clock domain. The unaligned protocol transmission conversion (data splicing and splitting) module mainly completes the splicing and splitting of data in the case of address non-alignment. The channel converter is used to pack and unpack network data packets. The request FIFO is used to store data for requesting channels. The ID latch is used to implement outstanding transmission of different IDs.

[0014] like Figure 1 As shown, the NoD-Router (NoD's router node) has two ports: a CDI data input port and a CDO data output port. Each port includes a clock signal, a data signal, and Valid and Ready handshake signals.

[0015] The signals from the CDO port of the NoD-Router are transmitted to the CDI interface of the Channel Converter via the Async Bridge module in the Slave Interface, and then enter the Write Channel Converter. The Write Channel Converter is connected to the Packet Decoder, Spliter / Merger, and the write channel of the target bus (Slave IP bus) (e.g., AXI's W and AW channels). When decoding the packet header, it compares the Transfer ID (TID) with the corresponding bit in the ID latch. If the corresponding bit in the ID latch is 1, it indicates that the ID transmission is preempted. At this time, the Write Channel Converter pauses the pipeline, waiting for the ID latch to unlock (i.e., the previous corresponding ID transmission is complete), and then proceeds with the transmission of this related ID, while simultaneously sending request information (including information from the header micro-chip and part of the body micro-chip) to the request FIFO. The data splitter / merger primarily splices / splits data based on the starting address and length to complete the adaptation of unaligned transmission.

[0016] The signals of the CDI port of the NoD-Router are transmitted through the CDO channel of the Channel Converter via the Async Bridge module in the Slave Interface. The CDO channel of the Channel Converter is connected to the read / response channel (e.g., AXI's R, AR, and B channels) of the target bus (slave device IP bus) in the Read / Response Channel Converter, and to the Spliter / Merger and Packet Encoder. When sending a read / write response packet, the request information corresponding to the ID (including information from the header fragment and part of the body fragment) is extracted from the FIFO, then reassembled into the header fragment and part of the body fragment, and the ID latch is released (the corresponding bit is set to 0).

[0017] A typical application is connecting related slave device IPs to the AXI-FULL bus. Figure 2 This demonstrates a typical application scenario for this slave device IP, where the DSP and AI chips exchange data via DDR. The on-chip network bus protocol bandwidth is 128 bits, while the DDR IP core's AXI bus data width is 256 bits, requiring support for unaligned transmission of single words (32 bits). Figure 3 This demonstrates data concatenation under several different address offsets relative to the alignment position. Since the DDR IP core's AXI bus data width is 256 bits, there are a total of 8 different data concatenation / splitting methods. For each possible data concatenation / splitting method between the on-chip network and the target bus (slave device IP bus protocol), a corresponding concatenation / splitting module needs to be designed. During connection, the bus bundle containing data is sent to the corresponding concatenation / splitting unit via a MUX using the address offset relative to the alignment position. After concatenation / splitting, a DEMUX returns the bus bundle containing data. Figure 4 As shown, this integrated scheme for data splicing / splitting modules is designed specifically for splicing modules based on different address offsets. Compared with the scheme that splits all data packets into the smallest transmission units, it reduces data transmission latency and increases throughput.

[0018] Assuming the ID width in the AXI bus bundle is 4 bits, then due to the ID latch, the DSP and AI can use 16 transfer IDs (TIDs) to interact with the DDR simultaneously without causing blockage of the slave device interface. The cache consistency is maintained by the DDR controller IP.

Claims

1. A non-aligned transmission network interface architecture for on-chip network slave devices, characterized in that: The unaligned transmission network interface for on-chip network slave devices consists of an asynchronous bus bridge, an unaligned data splicing and splitting module, a channel converter, a request FIFO, and an ID latch. The asynchronous bus bridge module is used for signal transmission in the asynchronous clock domain. The unaligned data splicing and splitting module sends the bus bundle containing data to the corresponding splicer / splitter via a MUX through the offset of the address relative to the alignment position. After splicing / splitting is completed, a DEMUX returns the bus bundle containing data, thus completing the splicing and splitting of data in the case of address non-alignment. The channel converter includes a write channel conversion module and a read / response channel conversion module. The write channel conversion module is connected to a packet decoder, a data splicer / splitter, and a write channel of the target bus. The read / response channel conversion module is connected to a packet encoder, a data splicer / splitter, and a read / response channel of the target bus. The channel converter is used to pack and unpack network data packets. The request FIFO is used to store data from the request channel; The ID latch is used to record the occupancy status of each transmission ID, so as to ensure that multiple Outstanding transmissions with different IDs do not block each other.

2. The unaligned transmission network interface architecture for on-chip network slave devices according to claim 1, characterized in that: The ID latch is used for transmission synchronization between the write channel conversion module and the read / response channel conversion module to support outstanding transmission.

3. The unaligned transmission network interface architecture for on-chip network slave devices according to claim 2, characterized in that: When the packet encoder sends a read / write response packet, it extracts the request information corresponding to the ID from the request FIFO and releases the ID latch. When the packet decoder decodes the packet header, it compares the transmitted ID with the corresponding bit in the ID latch. If the corresponding bit in the ID latch is 1, it means that the ID transmission is occupied.

4. The unaligned transmission network interface architecture for on-chip network slave devices according to claim 1, characterized in that: The network transmission interface integrates modules for splicing / splitting unaligned data, designed separately for different address offsets; and for each possible data splicing / splitting method between the on-chip network and the target bus, a corresponding splicing / splitting module is designed.

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