一种基于FPGA实现eSPI通信方法、系统、设备及介质
By replacing the SPI bus with eSPI instructions on the FPGA to achieve eSPI communication, the high cost and low efficiency problems in the BMC design phase are solved, the verification efficiency is improved, and the communication functions of the FPGA are expanded.
CN115827543BActive Publication Date: 2026-07-17SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2022-11-18
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
During the BMC design phase, eSPI bus functional verification requires a dedicated master module, resulting in high development costs and low efficiency.
Method used
By replacing the SPI bus module on the FPGA with eSPI commands and sending and receiving data through the SPI bus on the FPGA, the eSPI communication protocol is simulated, and the master function of the eSPI bus is realized.
Benefits of technology
It reduces verification costs during the BMC design phase, improves development efficiency, and expands communication capabilities for FPGAs that do not support eSPI functionality.
✦ Generated by Eureka AI based on patent content.
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Figure CN115827543B_ABST
Abstract
本发明属于计算机领域，具体涉及一种基于FPGA实现eSPI通信方法、系统、设备及可读存储介质。方法包括：基于eSPI通信协议将FPGA上的SPI总线的发送数据替换为eSPI指令，并将eSPI指令通过FPGA上SPI总线发送到从端；响应于从端发送反馈数据，通过FPGA上的SPI总线接收所述反馈数据，并基于eSPI通信协议对反馈数据进行解析得到eSPI指令对应的数据。通过本发明提出的一种基于FPGA实现eSPI通信方法，利用现有的FPGA上的SPI总线模块的IP核实现eSPI总线主端的功能，用于BMC设计之初的eSPI功能的验证，有效降低了BMC设计阶段的验证成本，充分利用现有条件，提升开发效率。基于FPGA实现的eSPI总线的主端功能可以单独对不支持eSPI功能的FPGA的通信功能进行拓展，具有广泛的应用价值。
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