Implementation method and device of hardware pause mechanism in FPGA configuration process

Abstract

The application provides a method and device for implementing a hardware pause mechanism in an FPGA configuration process. The method comprises the following steps: firstly, a first bit stream is parsed at a slave interface (SI) end to obtain a pause position in the first bit stream; then, a corresponding pause frame is added at the pause position in the first bit stream to obtain a second bit stream; then, the second bit stream is stored in a first-in-first-out (FIFO) data buffer at the SI end; after that, when a master interface (MI) end reads the second bit stream from the FIFO, if a pause frame is read out, the pause time indicated by the pause frame is loaded into a counter, and a countdown for a pause process is started; the MI end stops reading data from the FIFO and sending data out until the pause process ends. In this way, the current configuration process can be paused in the FPGA configuration process, and the subsequent configuration process can be continued after the previous configuration process ends.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit design technology, and in particular to a method and apparatus for implementing a hardware pause mechanism during FPGA configuration. Background Technology

[0002] Currently, when using Field Programmable Gate Array (FPGA) chips, Electronic Design Automation (EDA) tools first convert the user's design file into a bitstream file, and then download it into the FPGA chip to complete the implementation of the design function. This process is called the FPGA configuration process.

[0003] However, during FPGA configuration, certain timing requirements necessitate a pause in some configuration steps to allow the preceding configuration process to complete before proceeding. Traditionally, this pause was not possible. If the previous configuration step was incomplete, the only way to achieve a delay was to insert redundant, invalid configuration frames. Summary of the Invention

[0004] This invention describes a method and apparatus for implementing a hardware pause mechanism during FPGA configuration, which can solve the above-mentioned technical problems.

[0005] According to the first aspect, a method for implementing a hardware pause mechanism during FPGA configuration is provided.

[0006] The method includes:

[0007] The slave interface SI parses the first bitstream to obtain the pause positions in the first bitstream; the SI adds a corresponding pause frame to the pause position in the first bitstream to obtain the second bitstream; the SI stores the second bitstream in a first-in-first-out (FIFO) data buffer; when the host interface MI reads the second bitstream from the FIFO, if a pause frame is read, the pause time indicated by the pause frame is loaded into a counter, and a countdown for the pause process begins; the MI stops reading data from the FIFO and sending data until the pause process ends.

[0008] In some embodiments, before parsing the first bit stream at the slave interface SI terminal, the method further includes: the SI terminal obtaining the first bit stream from the configuration bus, wherein the first bit stream is obtained by converting a user design file using an electronic automation design (EDA) tool.

[0009] In some embodiments, during the pause process, the SI terminal continues to store data into the FIFO until the FIFO is full.

[0010] In some embodiments, upon the termination of the pause process, the MI terminal continues to read the second bit stream from the FIFO.

[0011] In some embodiments, if a non-pause frame is read, the non-pause frame is transmitted to a field-programmable gate array (FPGA) chip to configure the FPGA chip.

[0012] According to the second aspect, an implementation device for a hardware pause mechanism during FPGA configuration is provided.

[0013] The device includes:

[0014] The first bitstream parsing module is used to parse the first bitstream through the slave interface SI to obtain the pause positions in the first bitstream; the second bitstream acquisition module is used to add corresponding pause frames to the pause positions in the first bitstream through the SI to obtain the second bitstream; the data buffer storage module is used to store the second bitstream into a first-in-first-out (FIFO) data buffer through the SI; the second bitstream reading module is used to load the pause time indicated by the pause frame into a counter when the host interface MI reads the second bitstream from the FIFO, and start a countdown for the pause process; and to stop reading data from the FIFO and sending data through the MI until the pause process ends.

[0015] In some embodiments, the apparatus further includes:

[0016] The first bit stream acquisition module is used to acquire the first bit stream from the configuration bus through the SI terminal. The first bit stream is obtained by converting the user design file using an electronic automation design (EDA) tool.

[0017] In some embodiments, the second bitstream reading module is further configured to:

[0018] During the pause, data continues to be stored in the FIFO through the SI terminal until the FIFO is full.

[0019] In some embodiments, the second bitstream reading module is further configured to:

[0020] Once the pause process ends, the second bit stream continues to be read from the FIFO via the MI terminal.

[0021] In some embodiments, the second bitstream reading module is further configured to:

[0022] If a non-pause frame is read, the non-pause frame is transmitted to the Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

[0023] In the methods and apparatus provided in the embodiments of this specification, by adding pause frames to the configuration file bitstream and controlling the pause process through a counter during the bitstream reading process, it is possible to pause the FPGA configuration process for a period of time until the previous configuration process is completed before continuing the subsequent configuration, thus meeting the timing requirements of certain configuration processes. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This diagram illustrates a flowchart of a method for implementing a hardware pause mechanism during FPGA configuration, as provided in an embodiment of this specification.

[0026] Figure 2 This diagram illustrates the implementation method of a hardware pause mechanism during FPGA configuration provided in an embodiment of this specification.

[0027] Figure 3 This diagram illustrates the structure of an implementation device for a hardware pause mechanism during FPGA configuration, as provided in an embodiment of this specification. Detailed Implementation

[0028] The solution provided in this specification will now be described with reference to the accompanying drawings.

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0030] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0031] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0033] Figure 1 This document illustrates a flowchart of a method for implementing a hardware pause mechanism during FPGA configuration, as provided in an embodiment of this specification. Figure 1 As shown, the method includes the following steps:

[0034] In step S110, the slave interface SI (Slave Interface) parses the first bit stream to obtain the pause positions in the first bit stream.

[0035] In some embodiments, prior to this step, the method further includes: the SI end obtaining a first bit stream from the configuration bus, the first bit stream being obtained by converting a user design file using an electronic automation design (EDA) tool.

[0036] In some embodiments, the SI end has several positions in the first bitstream that require pausing, and the subsequent configuration process can only continue after a specified pausing time.

[0037] In some more specific embodiments, the configuration process of an FPGA chip manufactured by Xilinx is used as an example to illustrate the composition of the first bit stream. The configuration data is composed of frames, which are the smallest addressable units in the configuration data. The frames are 1 bit wide and the length is equal to the height of the chip used.

[0038] For example, the configuration file .bit, i.e., the bitstream file, is in binary format and contains header redundancy information, configuration data stream, and tail redundancy information.

[0039] The length of the header redundancy information is uncertain, approximately 72 bytes. The second part is the configuration data stream, which begins with 0xFF FF FF FF AA 99 55 66. For the specific format and meaning of the configuration data stream, please refer to the FPGA parameter literature.

[0040] The final part is the tail redundancy information, consisting of 16 32-bit no-operation instructions: 0x20 00 0000. These no-operation instructions indicate that a no-operation is to be performed. This part of the information does not need to be loaded into the FPGA.

[0041] For example, these no-operation instructions in the first bitstream are the positions where a pause is required.

[0042] In step S120, the SI end adds a corresponding pause frame at the pause position in the first bit stream to obtain the second bit stream.

[0043] In some embodiments, the parsed pause positions are marked with pause frames, including the pause position and pause time, thereby converting the first bitstream into a second bitstream. The second bitstream then contains data frames and pause frames.

[0044] For example, the format of the pause frame is not limited; it only needs to indicate the corresponding pause time.

[0045] In step S130, the SI end stores the second bit stream into the first-in-first-out (FIFO) data buffer.

[0046] In some embodiments, before storing the second bit stream into the FIFO, the SI end first sends a write operation request to the FIFO, and then sends the second bit stream after receiving a response message from the FIFO indicating that writing is allowed.

[0047] In step S140, when the Master Interface (MI) reads the second bit stream from the FIFO, if a pause frame is read, the pause time indicated by the pause frame is loaded into the counter, and a countdown for the pause process begins; the MI stops reading data from the FIFO and sending data until the pause process ends.

[0048] In some embodiments, this step includes: during the pause process, the SI continues to store data into the FIFO until the FIFO storage space is full.

[0049] In some embodiments, this step includes: when the pause process ends, the MI end continues to read the second bit stream from the FIFO.

[0050] In some embodiments, this step further includes: if the read-out frame is a non-pause frame, transmitting the non-pause frame to the field-programmable gate array (FPGA) chip to configure the FPGA chip.

[0051] For example, the bit width of this counter is not limited and can be set according to actual needs.

[0052] Figure 2 This diagram illustrates the principle of a hardware pause mechanism implementation method during FPGA configuration, as provided in an embodiment of this specification. The following further details this method in conjunction with the attached diagram. Figure 2 The present invention is described below.

[0053] The SI (System Injection) terminal receives the first bitstream wdata, obtained from the user design file converted using EDA tools, from the configuration bus. After parsing the first bitstream and adding a pause frame (frame parse), it obtains the second bitstream data+addr, where addr represents the pause frame position. The SI terminal sends a write operation request wr_req_n to the FIFO (FIFO File System), and then, based on the FIFO's response message indicating that writing is allowed, begins writing the second bitstream into the FIFO.

[0054] The MI (Management Entity) first sends a read operation request `rd_req_n` to the FIFO (FIFO Component Object). Then, based on the FIFO's response indicating permission to read, it reads the second bitstream stored in the FIFO. According to the FIFO's first-in, first-out (FIFO) characteristic, the bitstream that was stored first is read from the MI first. Following the order in which the second bitstream was stored in the FIFO, when a data frame (`data`) is read, the MI directly sends the `data` frame out to configure the FPGA. When a pause frame (`addr`) is read, the MI loads the pause frame into a counter and starts a countdown. When the countdown ends, the pause process ends, and the MI continues reading the second bitstream from the FIFO.

[0055] During the pause, the SI (System Injection) continues to send bit streams to the FIFO until the FIFO is full. The MI (System Injection) stops reading data from the FIFO and sending data to the FPGA until the pause ends.

[0056] Corresponding to the method provided by the present invention, the present invention also provides an apparatus. Figure 3 This diagram illustrates the structure of a device for implementing a hardware pause mechanism during FPGA configuration, as provided in an embodiment of this specification. Figure 3 As shown, the device S300 includes:

[0057] The first bitstream parsing module S320 is used to parse the first bitstream through the slave interface SI to obtain the pause positions in the first bitstream.

[0058] The second bitstream acquisition module S330 is used to add corresponding pause frames at the pause positions in the first bitstream through the SI terminal to obtain the second bitstream.

[0059] The data buffer storage module S340 is used to store the second bit stream into the first-in-first-out (FIFO) data buffer via the SI terminal.

[0060] The second bitstream reading module S350 is used to load the pause time indicated by the pause frame into a counter when the host interface MI reads the second bitstream from the FIFO and reads a pause frame, and to start a countdown for the pause process; and to stop reading data from the FIFO and sending data out through the MI until the pause process ends.

[0061] In some embodiments, the device S300 further includes:

[0062] The first bit stream acquisition module S310 is used to acquire the first bit stream from the configuration bus through the SI terminal. The first bit stream is obtained by converting the user design file using an electronic automation design (EDA) tool.

[0063] In some embodiments, the second bit stream reading module S350 can also be used to: when the pause process ends, the MI end continues to read the second bit stream from the FIFO.

[0064] In some embodiments, the second bitstream reading module S350 can also be used to: if the read frame is a non-pause frame, transmit the non-pause frame to the field-programmable gate array (FPGA) chip to configure the FPGA chip.

[0065] It needs to be explained that, for Figure 3 For a description of the apparatus, see also the description of the aforementioned method.

[0066] According to another embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed in a computer, causes the computer to perform a combination Figure 1 The method described.

[0067] According to another embodiment, a computing device is also provided, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, it implements a combination... Figure 1 The methods described herein. Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.

[0068] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for implementing a hardware pause mechanism during FPGA configuration, characterized in that, The method includes: The slave interface SI parses the first bit stream to obtain the pause position in the first bit stream; the pause position is the position where the no-operation instruction is located in the first bit stream; The SI end adds a corresponding pause frame at the pause position in the first bitstream to obtain a second bitstream; the pause frame is a frame used to mark the parsed pause position; the pause frame includes a pause position and a pause time; The SI terminal stores the second bit stream into a first-in-first-out (FIFO) data buffer. When the host interface MI reads the second bit stream from the FIFO, if a pause frame is read, the pause time indicated by the pause frame is loaded into a counter, and a countdown for the pause process begins; the MI stops reading data from the FIFO and sending data until the pause process ends.

2. The method according to claim 1, wherein, Before parsing the first bit stream at the slave interface SI, the method further includes: The SI terminal obtains the first bit stream from the configuration bus, which is obtained by converting the user design file using an electronic automation design (EDA) tool.

3. The method according to claim 1, characterized in that, The method further includes: During the pause, the SI terminal continues to store data into the FIFO until the FIFO is full.

4. The method according to claim 1, characterized in that, The method further includes: Once the pause process ends, the MI terminal continues to read the second bit stream from the FIFO.

5. The method according to claim 1, characterized in that, The method further includes: If a non-pause frame is read, the non-pause frame is transmitted to the Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

6. An apparatus for implementing a hardware pause mechanism during FPGA configuration, characterized in that, The device includes: The first bitstream parsing module is used to parse the first bitstream through the slave interface SI terminal to obtain the pause position in the first bitstream; the pause position is the position where the no-operation instruction is located in the first bitstream; The second bitstream acquisition module is used to add corresponding pause frames to the pause positions in the first bitstream through the SI terminal to obtain a second bitstream; the pause frame is a frame used to mark the parsed pause positions; the pause frame includes a pause position and a pause time; The data buffer storage module is used to store the second bit stream into a first-in-first-out (FIFO) data buffer through the SI terminal; The second bitstream reading module is used to load the pause time indicated by the pause frame into a counter when the host interface MI terminal reads the second bitstream from the FIFO, and start a countdown for the pause process if the read frame is a pause frame; and to stop reading data from the FIFO and sending data out through the MI terminal until the pause process ends.

7. The apparatus according to claim 6, wherein, The device further includes: The first bit stream acquisition module is used to acquire the first bit stream from the configuration bus through the SI terminal. The first bit stream is obtained by converting the user design file using an electronic automation design (EDA) tool.

8. The apparatus according to claim 6, wherein the second bitstream reading module is further configured to: During the pause, data continues to be stored in the FIFO through the SI terminal until the FIFO is full.

9. The apparatus according to claim 6, wherein the second bitstream reading module is further configured to: Once the pause process ends, the second bit stream continues to be read from the FIFO via the MI terminal.

10. The apparatus according to claim 6, wherein the second bitstream reading module is further configured to: If a non-pause frame is read, the non-pause frame is transmitted to the Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

Images