Memory device capable of repairing defective word lines

Abstract

Embodiments of the invention provide a memory device, comprising: a plurality of word lines grouped into a plurality of word line groups; and a plurality of redundant word lines grouped into M redundant word line groups; and a memory control circuit connected to the word line groups and the redundant word line groups and configured to replace a plurality of defective word line groups of the plurality of word line groups by selecting from the redundant word line groups, wherein each of the plurality of defective word line groups includes at least one defective word line, all M redundant word line groups are available for repairing word line groups during a wafer stage, wherein M is an integer greater than 2, and N of the M redundant word line groups are available for repairing word line groups during the wafer stage, during a package stage, and during a post-package stage, wherein N is an integer less than M.

Description

Technical Field

[0001] This invention relates to a memory device capable of repairing defective word lines. Background Technology

[0002] Typically, for memory devices such as dynamic random-access memory (DRAM) or other similar devices, the memory device may undergo multiple stages during which each defective word line (WL) can be repaired by replacing defective word lines (WLs) with redundant word lines (RWLs). A first repair operation can be performed during the wafer stage. During the wafer stage, before the wafer is diced into dies that are subsequently packaged, defective WLs can be repaired using RWLs. Several defective WLs can be repaired using RWLs. After the die containing the memory device has been packaged, the memory device may undergo a second repair operation during the packaging stage, where one or more defective WLs can be repaired using RWLs before the memory device is shipped to the supplier. For example, for memory devices such as fourth-generation dual data rate (DDR4) synchronous DRAM, a third repair operation, including hard post-package repair (hppr) and / or soft post-package repair (sppr), may occur during the post-package stage as defined in standards such as those of the Joint Electron Device Engineering Council (JEDEC) to allow the memory device to be repaired after it has been used by the user.

[0003] Since at least three repair operations may occur in at least three different stages—the wafer stage, the packaging stage, and the post-packaging stage—it is necessary to allocate the RWL (Repair Workflow) to perform the repair operations during each stage. Conventionally, this is done by dividing the RWL into three non-overlapping portions, each dedicated to one of the three stages.

[0004] Figure 1 An example of using 16 rows of RWL to repair defective WL is shown, and such RWL is divided into three regions 101 to 103. RWL#0 to RWL#12 in the first region 101 are allocated specifically for repairing defective WL during the wafer stage, RWL#13 to RWL#14 in the second region 102 are allocated specifically for repairing defective WL during the packaging stage, and RWL#15 in the third region 103 is allocated specifically for repairing defective WL in the post-packaging stage.

[0005] However, the repair scheme described above may not be the most efficient solution to achieve high levels of RWL utilization. A more flexible approach, designed to improve RWL utilization and reduce hardware costs, would be to divide the RWL into three non-overlapping regions, each assigned to one of the three phases. Summary of the Invention

[0006] This invention provides a memory device capable of repairing defective word lines.

[0007] This invention provides a memory device comprising, but not limited to: a plurality of word lines grouped into a plurality of WL groups; a plurality of redundant word lines grouped into M RWL groups; and a memory control circuit connected to the WL groups and the RWL groups and configured to replace a plurality of defective WL groups of the plurality of WL groups by selecting from the RWL groups, wherein each of the plurality of defective WL groups includes at least one defective word line, all M RWL groups can be used to repair WL groups during the wafer stage, where M is an integer greater than 2, and N of the M RWL groups can be used to repair WL groups during the wafer stage, during the packaging stage, and during the post-packaging stage, where N is an integer less than M. Attached Figure Description

[0008] Figure 1 The WL repair solution is shown;

[0009] Figure 2 A data storage device with multiple databases is shown;

[0010] Figure 3 This demonstrates using RWL to repair WL;

[0011] Figure 4 A block diagram of a memory device is shown;

[0012] Figure 5 This demonstrates the repair procedure for the memory device during the wafer stage;

[0013] Figure 6 This demonstrates the repair procedure for the memory device during the packaging stage;

[0014] Figure 7 A hardware diagram of a memory device with other details is shown;

[0015] Figure 8 The algorithm implemented via a memory device is shown.

[0016] Explanation of icon numbers

[0017] 101, 102, 103: Areas;

[0018] 301: RWL;

[0019] 302: WL;

[0020] 401: RWL Group;

[0021] 402: WL Group;

[0022] 500: Memory device;

[0023] 510: Connection interface;

[0024] 530: Memory control circuit;

[0025] 550: Memory array;

[0026] 570: Fuse trigger controller;

[0027] 701, 702, 703, 801, 803: Fuse group;

[0028] 704: Comparator circuit;

[0029] 705, 805: Availability check logic;

[0030] 706: WL / RWL selection logic;

[0031] 707: Receive address;

[0032] S501, S502, S503, S504, S505, S506, S507, S601, S602, S603, S604, S605, S606, S607, S801, S802, S803, S804, S805, S806, S807, S808, S809, S810, S811, S812, S813, S814, S815, S816, S817, S818, S819, S820, S821, S822, S823: Steps. Detailed Implementation

[0033] Reference will now be made in detail to present exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0034] To increase the availability of redundant word lines (RWLs) for word line (WL) repair at each of the three stages as previously described, within a reasonable hardware cost, embodiments of the present invention provide a memory device and a method for repairing a memory device. In these embodiments, M RWL groups are configured to potentially repair defective WL groups in the memory bank during each of the three stages. During the wafer stage, all M RWL groups are available for repairing defective WL groups, where M can be any integer greater than or equal to 3. Of the M RWL groups, N RWL groups can be flexibly allocated for repairing defective WL groups during the packaging and post-packaging stages, where N is an integer and a subset of M. In other words, in these embodiments, N of the M RWL groups are available for repairing defective WL groups during all three stages, rather than having a fixed region specifically allocated for repairing defective WL groups during each of the three stages. Therefore, the utilization of the M RWL groups is improved. It is worth noting that post-packaging repair can include hard-packaging repair (hppr) and soft-packaging repair (sppr), but for the purposes of this embodiment of the invention, it is assumed that hppr and sppr are the same.

[0035] refer to Figure 2 Memory devices such as DDR3 or DDR4 DRAM may typically contain, for example, no more than eight memory libraries, libraries 0 through 7. For instance, such as... Figure 3 As shown, the memory library may contain multiple RWL 301s allocated for repairing WL 302s in the library. The multiple RWL 301s may be grouped into multiple RWL groups. For example... Figure 3 As shown, RWL group 401 is used to replace WL group 402, and the number of WL in WL group 402 can be the same as the number of RWL in RWL group 401.

[0036] Figure 4 A hardware block diagram of an exemplary memory device 500, such as DRAM or other similar memory devices, is shown. The memory device 500 includes, but is not limited to, memory control circuitry 530 electrically connected to a connection interface 510, and has, for example, memory control circuitry 530, such as memory control circuitry 540, a memory control circuitry 550, a memory control circuitry 560, a memory control circuitry 570, a memory control circuitry 580, a memory control circuitry 590, a memory control circuitry 50 ... Figure 2 The memory array 550 of the multiple memory banks shown is a memory bank array and a fuse control 570.

[0037] In one embodiment, memory control circuitry 530 may be configured to receive external commands (e.g., activation commands, write commands, etc.) to access memory array 550 via connection interface 510. Memory array 550 may include one or more memory banks, each having multiple WLs, multiple RWLs, and multiple fuse groups. Multiple WLs are grouped into multiple WL groups, and multiple RWLs are grouped into multiple RWL groups, wherein each WL group and each RWL group has the same number of WLs and RWLs. Multiple fuse groups are used to record the addresses of defective WL groups during the wafer stage, packaging stage, and post-packaging stage. RWL groups are used to repair (replace) defective WL groups. Specifically, when any WL group containing defective WLs (hereinafter referred to as a "defective WL group") is found during the three stages, the address of the defective WL group is recorded in one of the fuse groups. Then, if the address of the defective WL group recorded in the fuse group is accessed via an external command, the corresponding RWL group is selected to replace the defective WL group.

[0038] In one embodiment, each memory bank of the memory array 550 includes multiple WL groups, M RWL groups indexed from #0 to #M-1, and M+K+L fuse groups indexed from #0 to #M+K+L-1, where M≥3, K≥1, and L≥1. Each fuse group includes multiple fuses for recording the addresses of defective WL groups and recording the availability of the fuse group. A fuse-breaking controller 570 is connected to the memory control circuitry 530 and the memory array 550 to receive the addresses of defective WL groups and defective RWL groups. The fuse-breaking controller 570 is configured to record the addresses of defective WL groups by blowing the fuses of the fuse group. The fuse-breaking controller 570 is also configured to mark fuse groups that have already been used to record the addresses of defective WL groups or fuse groups corresponding to defective RWL groups as unavailable. In one embodiment, each of the fuse groups may include at least one fuse dedicated to recording the availability of the fuse group, and the fuse-breaking controller 570 may be configured to blow the fuse dedicated to recording availability in order to mark the fuse group as unavailable. In other embodiments, the fuse group may also be marked as unavailable using different techniques, and the invention is not limited thereto.

[0039] In the M+K+L fuse groups, M fuse components indexed from #0 to #M-1 form a first fuse group, K fuse components indexed from #M to #M+K-1 form a second fuse group, and L fuse components indexed from #M+K to #M+K+L-1 form a third fuse group. The first fuse group is specifically used to record the addresses of defective WL groups during the wafer stage, the second fuse group is specifically used to record the addresses of defective WL groups during the packaging stage, and the third fuse group is specifically used to record the addresses of defective WL groups during the post-packaging stage. In an alternative embodiment, the second and third fuse groups, dedicated to packaging repair and post-packaging repair, can be shared by more than one library. In this alternative embodiment, in addition to the fuses recording the addresses of defective WL groups, each of these fuse groups can be considered as an additional fuse recording library information of the repaired defective WL groups.

[0040] Each fuse group in the first fuse group is pre-configured to correspond to one of the M RWL groups. For example, fuse group #0 corresponds to RWL group #0, fuse group #1 corresponds to RWL group #1, and so on. In other words, all M RWL groups are pre-configured to be used to replace defective WL groups during the wafer stage.

[0041] In this embodiment, an RWL group with N highest index numbers (hereinafter referred to as the "last N RWL groups") can be configured to replace defective WL groups during the packaging and post-packaging stages, where N ≥ L + K. In other words, the total number of fuse groups in the second and third fuse groups will be less than or equal to N.

[0042] The memory control circuit 530 coordinates between the connection interface 510, the memory array 550, and the fuse trigger controller 570 to perform various functions related to embodiments of the present invention.

[0043] Through such Figures 5 to 6 The following exemplary embodiments shown further illustrate Figure 4 Repair operation of memory device 500. Figure 5 The repair procedure for memory device 500 during the wafer stage is shown. Figure 6 The repair procedure for memory device 500 during the packaging stage is shown.

[0044] refer to Figure 4 and Figure 5In step S501, a test is initiated to identify defective WL groups and defective RWL groups. In step S502, defective RWL groups are marked as unavailable. Specifically, the fuse-breaking controller 570 can be configured to select a fuse group corresponding to the first fuse group of defective RWL groups and mark the selected fuse group as unavailable. In step S503, the number of available RWL groups is compared with the number of defective WL groups. If the number of available RWL groups is less than the number of defective WL groups, then in step S504, the memory device 500 is discarded. If the number of available RWL groups is greater than or equal to the number of defective WL groups, then in step S505, the fuse-breaking controller 570 can be configured to select a fuse group corresponding to the first fuse group of available RWL groups, record the addresses of the remaining defective WL groups in the selected fuse group, and mark the selected fuse group as unavailable. In this embodiment, the fuse group with the lowest index number is selected in step S505. In step S506, it is determined whether the addresses of all defective WL groups have been recorded. If not, the procedure continues from step S505. If yes, wafer repair is complete in step S507.

[0045] Referring to the cycle of steps S505 to S506, in this embodiment, the fuse groups of the first fuse group are selected in ascending order, starting with the fuse group with the lowest index number. In an alternative embodiment, the fuse groups of the first fuse group can be selected in any predetermined order. For example, the fuse groups of the first fuse group can be selected in descending order, starting with the fuse group with the highest index number; in this instance, the fuse group with the highest index number is selected in step S505.

[0046] refer to Figure 4 and Figure 6In step S601, a test is initiated to identify defective WL groups. In step S602, the number of defective WL groups identified in step S601 is compared with the number of fuse groups in the second fuse group. Specifically, it is determined whether the number of defective WL groups identified in step S601 is less than or equal to K. If the number of defective WL groups is greater than K, then in step S603, the memory device 500 is discarded. If the number of defective WL groups is less than or equal to K, then in step S604, the fuse-breaking controller 570 can be configured to select a fuse group in the second fuse group and record the addresses of the remaining defective WL groups identified in step S601 in the selected fuse group. In this embodiment, the fuse group with the highest index number is selected in step S604. In step S605, it is determined whether the addresses of all defective WL groups have been recorded. If not, then the procedure continues from step S604. If so, then in step S606, a final test is performed to determine if there are enough usable RWL groups in the last N RWL groups to replace the defective WL group recorded in the second fuse group. If the final test passes, then in step S607, the package repair is complete. If the final test fails, then in step S603, the memory device 500 is discarded.

[0047] Finally, when the user uses the memory device 500 during the post-packaging stage, the user can record the address of the defective WL group in the fuse group of the third fuse group.

[0048] Figure 7 Showing other details Figure 4 Hardware diagram of memory device 500. (Reference) Figure 4 and Figure 7 Each memory bank in memory array 550 includes three fuse group groups 701 to 703 for recording the addresses of defective WL groups during the three repair phases. The first fuse group group 701 contains M fuse groups, the second fuse group group 702 contains K fuse groups, and the third fuse group group 703 contains L fuse groups. In this embodiment, it is assumed that M = 16, K = 2, and L = 1. That is, the first fuse group group 701 contains sixteen fuse groups #0 to #15, the second fuse group group 702 contains two fuse groups #16 to #17, and the third fuse group group 703 contains one fuse group #18.

[0049] Fuse groups 701 to 703 are pre-configured to be used by fuse-breaking controller 570 to record the addresses of defective WL groups during different repair stages. Specifically, fuse-breaking controller 570 is configured to blow fuse groups of first fuse group 701 to record the addresses of defective WL groups during the wafer stage; blow fuse groups of second fuse group 702 to record the addresses of defective WL groups during the packaging stage; and blow fuse groups of third fuse group 703 to record the addresses of defective WL groups during the post-packaging stage. Blown fuse groups are then marked as unusable.

[0050] Each fuse group in the first fuse group 701 is pre-configured to correspond to one of the M RWL groups. When accessing the address of a defective WL group recorded in fuse groups #0 to #15, the memory control circuit 530 will select the corresponding RWL to replace the defective WL group.

[0051] Each fuse group in the second fuse group 702 and the third fuse group 703 is not pre-configured to correspond to any RWL group. When accessing the address of a defective WL group recorded in fuse groups #16 to #18, the memory control circuit 530 will, according to Figure 8 Steps S803 to S820 of the method described herein involve selecting one of the last N RWL groups (i.e., RWL group #13 to RWL group #15) to replace the defective WL group.

[0052] Refer again Figure 4 and Figure 7 The memory control circuit 503 includes a comparator circuit 704 and WL / RWL selection logic 706. The comparator circuit 704 includes multiple comparators, each connected to one of fuse groups #0 to #18, to compare the receive address 707 of a WL being accessed by an external command with an address recorded in the connected fuse group to determine if the receive address matches an address recorded in the connected fuse group. The comparison result is transmitted to the WL / RWL selection logic 706, which determines whether the accessed WL should be selected normally or whether an RWL should be selected to replace the accessed WL. Specifically, if the receive address 707 matches an address recorded in one of fuse groups #0 to #18, then an RWL will be selected to replace the accessed WL. For example, if receive address 707 matches an address recorded in fuse group #0, then the RWL of RWL group #0 is selected to replace the WL of the corresponding receive address. If receive address 707 does not match any address recorded in fuse groups #0 to #18, then the WL of the corresponding receive address is normally selected. Figure 8The algorithm shown is used to describe other details.

[0053] In one embodiment, the memory control circuit 503 may further include availability check logic 805 connected to the fuse groups with the N highest index numbers (hereinafter referred to as the "last N fuse groups") of the first fuse group 701. The availability check logic 705 is configured to check the availability of the last N fuse groups and output availability information to the connection interface 510 for external access. In this embodiment, the availability check logic 705 is connected to the last three fuse groups #13 to #15 and performs logic to check the availability of RWL groups #13 to #15 as available.

[0054] In an embodiment where post-packaging repair is not required, availability check logic 705 can perform OR logic to identify the presence of any available RWL groups, thereby quickly identifying whether memory device 500 supports post-packaging repair functionality. In other words, the output of availability check logic 705 can be used to quickly classify whether memory device 500 supports post-packaging repair guaranteed by the JEDEC DDR4 standard.

[0055] Figure 8 The detailed algorithm implemented in the WL / RWL selection logic 706 is shown. (See reference...) Figure 4 , Figure 7 as well as Figure 8 In step S801, the memory control circuit 530 receives an external command (e.g., an activation command) to access the memory array 550 via the connection interface 510. In step S802, the comparison circuit 704 compares the address of the received command (hereinafter referred to as the "receive address") with the addresses recorded in fuse groups #0 to #18 to determine whether the receive address matches one of the addresses recorded in fuse groups #0 to #18, and outputs the comparison result (hit signal #0 to hit signal #18) to the WL / RWL selection logic 706. In one embodiment, if the receive address matches an address recorded in fuse groups #0 to #18, the hit signal will be high, and if the receive address does not match any address recorded in fuse groups #0 to #18, the hit signal will be low. In step S803, if the received address matches the address recorded in fuse group #18 of the third fuse group 703 (i.e., the hit signal #18 is high), then the algorithm continues to step S804; otherwise, the algorithm continues to step S811.

[0056] In step S804, the WL / RWL selection logic 706 checks whether RWL group #15 is available. If so, in step S805, the WL / RWL selection logic 706 selects an RWL from RWL group #15 to replace the WL corresponding to the receive address. If RWL group #15 is unavailable, in step S806, the WL / RWL selection logic 706 checks whether RWL group #14 is available. If so, in step S807, the WL / RWL selection logic 706 selects an RWL from RWL group #14 to replace the WL corresponding to the receive address. If RWL group #14 is unavailable, in step S808, the WL / RWL selection logic 706 checks whether RWL group #13 is available. If so, then in step S809, the WL / RWL selection logic 706 will select the RWL from RWL group #13 to replace the WL corresponding to the receive address. If RWL group #13 is unavailable, then in step S810, the WL / RWL selection logic 706 will disable the WL corresponding to the receive address and will not connect the RWL.

[0057] In step S811, if the received address matches the address recorded in fuse group #17 of the second fuse group 702 (i.e., the hit signal #17 is high), the algorithm continues to step S812; otherwise, the algorithm continues to step S817. It is worth mentioning that in this embodiment, since the fuse groups used to record the addresses of defective WL groups in the loop from steps S604 to S605 are selected in the order of first selecting the fuse group with the highest number, when fuse group #17 is used, it means that at least one RWL group is needed for encapsulation repair, and at the same time, one RWL group needs to be reserved to ensure repair after encapsulation. Therefore, in step S812, the WL / RWL selection logic 706 checks whether there are two or more available RWL groups #13 to #15. If not, then in step S813, the WL / RWL selection logic 706 will deactivate the WL corresponding to the address of the received command and will not activate the RWL. If two or more of RWL groups #13 to #15 are available, then in step S814, the WL / RWL selection logic 706 checks whether RWL group #13 is available. If so, then in step S815, the WL / RWL selection logic 706 will select an RWL from RWL group #13 to replace the WL corresponding to the receive address; otherwise, in step S816, the WL / RWL selection logic 706 will select an RWL from RWL group #14 to replace the WL corresponding to the receive address.

[0058] In step S817, if the received address matches the address recorded in fuse group #16 of the second fuse group 702 (i.e., the hit signal #16 is high), the algorithm continues to step S818; otherwise, the algorithm continues to step S821. It is worth mentioning that in this embodiment, since the fuse groups used to record the addresses of defective WL groups in the loop from steps S604 to S605 are selected in the order of first selecting the fuse group with the highest number, when fuse group #16 is used, it means that at least two RWL groups are needed for encapsulation repair, and one RWL group needs to be reserved to ensure repair after encapsulation. Therefore, in step S818, the WL / RWL selection logic 706 checks whether all three RWL groups #13 to RWL group #15 are available. If so, then in step S820, the WL / RWL selection logic 706 will select the RWL in RWL group #14 to replace the WL corresponding to the receiving address; otherwise, in step S819, the WL / RWL selection logic 706 will disable the WL corresponding to the receiving address and will not connect the RWL.

[0059] In step S821, if the receive address matches any address recorded in fuse group #0 to fuse group #15 of the first fuse group 701 (e.g., any one of the match signals #0 to #15 is high), then in step S822, the WL / RWL selection logic 706 will select the RWL from the corresponding RWL group to replace the WL corresponding to the receive address. For example, if the receive address matches an address recorded in fuse group #0, then the memory control circuit 530 will select the RWL from RWL group #0 to replace the WL corresponding to the receive address. In step S823, since the receive address does not match any address recorded in fuse group #0 to fuse group #18, the memory control circuit 530 will normally select the WL corresponding to the receive address.

[0060] The following summarizes the procedures for repairing defective WL groups in a memory device during different stages of an embodiment of the invention. During the wafer stage, a test is first initiated to identify defective WL groups and defective RWL groups. Next, the memory device's fuse-breaking controller can be configured to mark all defective RWL groups as unusable. Then, if the number of identified usable RWL groups is less than the number of defective WL groups, the memory device is discarded. If the number of identified usable RWL groups is greater than or equal to the number of defective WL groups, the addresses of the defective WL groups are recorded in the fuse group of a first fuse group.

[0061] During the packaging phase, tests are initiated to identify defective WL groups. If the number of defective WL groups exceeds K, the memory device is discarded. Otherwise, the addresses of the defective WL groups are recorded in the fuse group of the second fuse group. A final test is then performed to confirm whether each defective WL group recorded in the fuse group can be properly repaired by the RWL group.

[0062] During the post-packaging stage, the user can record the address of the defective WL group in the fuse group of the third fuse group.

[0063] It is worth mentioning that each fuse group in the first fuse group is pre-configured as one of the corresponding RWL groups, and the fuse groups of the first fuse group are selected sequentially in a predetermined order to record the defective WL groups identified during the wafer stage. In other words, RWL groups are selected sequentially to replace defective WL groups in a predetermined order in order to maximize the availability of the last N RWL groups during the wafer stage.

[0064] When accessing an address in the fuse group of the second fuse group and the third fuse group, select the last N RWL groups to replace the defective WL group corresponding to the accessed address.

[0065] In view of the foregoing description, embodiments of the present invention are suitable for use in memory devices and are able to repair defective WL groups in a cost-effective manner by increasing the availability of RWL groups at each of the three stages at each of the wafer stage, packaging stage, and post-packaging stage, with reasonable hardware costs.

[0066] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the inventive embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that this invention cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: Multiple character lines are grouped into multiple character line groups; Multiple redundant word lines are grouped into M redundant word line groups; A memory control circuit is connected to the plurality of word line groups and the M redundant word line groups and configured to replace a plurality of defective word line groups of the plurality of word line groups by selecting from the M redundant word line groups; as well as Multiple fuse groups, each of which includes multiple fuses, for recording the address of one of the multiple defective word line groups and recording the availability of the fuse group, wherein... Each of the plurality of defective word line groups includes at least one defective word line. All of the M redundant word line groups can be used to repair the plurality of word line groups during the wafer stage, where M is an integer greater than 2, and N of the M redundant word line groups can be used to repair the plurality of word line groups during the wafer stage, the packaging stage, and the post-packaging stage, where N is an integer less than M. The plurality of fuse groups constitute a first fuse group, a second fuse group, and a third fuse group. The fuse groups in the first fuse group are specifically used to record the addresses of defect word line groups during the wafer stage, the fuse groups in the second fuse group are specifically used to record the addresses of defect word line groups during the packaging stage, and the fuse groups in the third fuse group are specifically used to record the group addresses of defect word line groups during the post-packaging stage.

2. The memory device according to claim 1, wherein the memory control circuitry is further configured to: Receive external commands that access word lines via the connection interface. Determine whether the address of the accessed word line matches the address recorded in the plurality of fuse groups, and If the address of the accessed word line matches the address recorded in the plurality of fuse groups, then a redundant word line is selected to replace the accessed word line.

3. The memory device according to claim 2, further comprising: A fuse-breaking controller, connected to the memory control circuit and configured to record the addresses of the plurality of defective word line groups by blowing the fuses of available fuse groups, and to mark the blown fuse groups as unavailable.

4. The memory device of claim 3, wherein each of the plurality of fuse groups further includes a fuse dedicated to recording the availability of the plurality of fuse groups, and the fuse-breaking controller is configured to blow the fuse to mark the fuse group including the fuse as unavailable.

5. The memory device of claim 1, wherein the first fuse group comprises M fuse groups, and each fuse group in the first fuse group is pre-configured to correspond to one of the M redundant word line groups.

6. The memory device of claim 1, wherein each of the second fuse group and the third fuse group further includes a fuse for recording memory library information of the plurality of defective word line groups recorded in the fuse group.

7. The memory device of claim 1, wherein the total number of the second fuse groups plus the total number of the third fuse groups is less than or equal to N.

8. The memory device of claim 1, wherein the memory control circuitry is further configured to repair the plurality of defective word line groups during the wafer stage, comprising: Identify the defective word line groups and the defective redundant word line groups among the plurality of word line groups. Mark multiple fuse groups in the first fuse group corresponding to the defective redundant word line group as unavailable, and Record the addresses of the remaining defective word line groups in the available fuse groups of the first fuse group.

9. The memory device of claim 8, wherein recording the address of the remaining defective word line group in the available fuse group of the first fuse group comprises: The address of the remaining defective word line group is recorded in the fuse group with the lowest index number in the first fuse group group.

10. The memory device of claim 8, wherein recording the address of the remaining defective word line group in the available fuse group of the first fuse group comprises: The address of the remaining defective word line group is recorded in the fuse group with an index number determined according to a predetermined order in the first fuse group group.

11. The memory device of claim 1, wherein the memory control circuitry is further configured to repair the plurality of defective word line groups during the packaging stage, comprising: Identify the multiple defective character line groups; as well as Record the addresses of the remaining defective word line groups in the available fuse group of the second fuse group.

12. The memory device of claim 11, wherein recording the address of the remaining defective word line group in the available fuse group of the second fuse group comprises: The address of the remaining defective word line group is recorded in the fuse group with the highest index number in the second fuse group.

13. The memory device of claim 2, wherein the memory control circuitry includes a plurality of comparators, each of the plurality of comparators being configured to compare the address of the accessed word line with an address recorded in one of the plurality of fuse groups to produce a comparison result.

14. The memory device of claim 13, wherein the memory control circuitry further includes selection logic configured to receive the comparison results of the plurality of comparators to determine whether the accessed word line should be normally connected or a redundant word line should be connected.

15. The memory device of claim 5, wherein the memory control circuitry further includes availability checking logic connected to the last N fuse groups of the first fuse group and outputs availability information of the last N fuse groups of the first fuse group.

16. The memory device of claim 15, wherein the availability information of the last N fuse groups of the first fuse group is used to classify whether the memory device supports post-packaging repair guaranteed by the JEDEC DDR4 standard.

17. The memory device of claim 1, wherein the wafer stage occurs when the memory device is in a wafer that has not been diced into dies.

18. The memory device of claim 1, wherein the packaging stage occurs after the wafer stage and during the packaging of the memory device before it is shipped to the supplier.

19. The memory device of claim 1, wherein the post-packaging stage occurs after the packaging stage when the memory device is being used by a consumer.

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