A sub-threshold SRAM read-write assist circuit

Abstract

The present disclosure provides a sub-threshold SRAM read-write assist circuit, comprising: a charge pump circuit composed of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a first capacitor, for generating a higher level higher than a power supply voltage at an output node; an under-voltage circuit composed of a third PMOS transistor, for generating an intermediate level lower than the power supply voltage at the output node; and a pulse generation circuit composed of a fourth PMOS transistor and a second NMOS transistor, for generating a word line pulse. The assist circuit of the present disclosure spontaneously regulates the word line level according to the read-write cycle, raises the word line level in the write cycle, and reduces the word line level in the read cycle, so as to improve the read-write capability.

Description

Technical Field

[0001] This disclosure relates to the field of memory access technology, and specifically to a subthreshold SRAM read / write auxiliary circuit. Background Technology

[0002] As the cell supply voltage decreases, the read stability and write capability of SRAM (Static Random Access Memory) decline. This necessitates auxiliary techniques to optimize read and write operations separately, with modifying the word line voltage being a common optimization method. Lowering the word line voltage helps reduce read corruption errors but negatively impacts write capability; raising the word line voltage improves write capability but weakens read stability. Therefore, a separate read / write word line control circuit needs to be designed to break the constraint between read / write auxiliary circuits, determine the read / write cycle, and automatically adjust the word line voltage to decrease or increase. Furthermore, the two sets of read / write auxiliary circuits should be combined into a single circuit to reduce area overhead. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address the aforementioned issues, this disclosure provides a subthreshold SRAM read / write auxiliary circuit, which at least partially solves the technical problems of decreased read stability and write capability in traditional SRAM circuits.

[0005] (II) Technical Solution

[0006] This disclosure provides a subthreshold SRAM read / write auxiliary circuit, comprising: a charge pump circuit, consisting of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a first capacitor, for generating a higher level at the output node than the power supply voltage; an undervoltage circuit, consisting of a third PMOS transistor, for generating an intermediate level at the output node below the power supply voltage; and a pulse generation circuit, consisting of a fourth PMOS transistor and a second NMOS transistor, for generating word line pulses.

[0007] Furthermore, the gate of the first PMOS transistor is connected to the auxiliary enable signal, and the drain of the first PMOS transistor is connected to the positive plate of the first capacitor; the drains of the second PMOS transistor and the first NMOS transistor are both connected to the negative plate of the first capacitor, and the gates of the second PMOS transistor and the first NMOS transistor are both connected to the inverse signal of the auxiliary enable signal.

[0008] Furthermore, the source of the third PMOS transistor is connected to the output word line of the capacitor, and the gate of the third PMOS transistor is connected to the enable signal of the auxiliary circuit.

[0009] Furthermore, the source of the fourth PMOS transistor is connected to the positive plate of the first capacitor, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are both connected to the output word line, and the gate of the fourth PMOS transistor and the gate of the second NMOS transistor are both connected to the input pulse signal.

[0010] Furthermore, the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the power supply, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the ground of the power supply; the drain of the third PMOS transistor is connected to the ground.

[0011] Furthermore, when no read / write operation is performed, the input pulse signal is at a high level, and the auxiliary circuit enable signal is at a low level. At this time, the first PMOS transistor is turned on, charging the positive plate of the first capacitor to a high level; the second PMOS transistor is turned off, and the first NMOS transistor is turned on, discharging the negative plate of the first capacitor to a low level, thus forming an initial voltage difference between the positive and negative plates of the first capacitor.

[0012] Furthermore, when a read operation is performed, the input pulse signal is at a low level, the auxiliary circuit enable signal is at a low level, at this time, the undervoltage circuit is turned on, the first PMOS transistor is turned on, the fourth PMOS transistor is turned on, the second NMOS transistor is turned off, the third PMOS transistor is turned on, and the word line output voltage is the intermediate level VL after being divided by the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor.

[0013] Furthermore, during a write operation, the input pulse signal is low, and the auxiliary circuit enable signal is high. At this time, the charge pump circuit performs a level boost, the undervoltage circuit is ineffective, the first PMOS transistor is off, the second PMOS transistor is on, the third PMOS transistor is off, the fourth PMOS transistor is on, the first NMOS transistor is off, the second NMOS transistor is off, the second PMOS transistor charges the negative plate of the first capacitor to a high level, and the voltage of the positive plate of the first capacitor is boosted to a higher level than the power supply voltage. The higher level is transmitted to the output word line through the fourth PMOS transistor, and the output voltage of the output word line is a higher level.

[0014] (III) Beneficial Effects

[0015] The subthreshold SRAM read / write auxiliary circuit disclosed herein spontaneously adjusts the word line level according to the read / write cycle, raising the word line level during the write cycle and lowering the word line level during the read cycle to improve read / write capabilities. Specifically, during read operations, the first, fourth, and third PMOS transistors are turned on, with the third PMOS transistor pulling the word line voltage down to an intermediate level, which helps improve the read capability of the memory cell. During write operations, the second PMOS transistor is turned on, activating the charge pump circuit to generate a higher level, which is then transmitted to the word line through the fourth PMOS transistor, thus improving the write capability of the memory cell. This disclosure can improve the read / write capability of the memory cell and ensure stable read / write operations for subthreshold SRAM. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 The circuit structure diagram of a subthreshold SRAM read / write auxiliary circuit provided in this disclosure;

[0018] Figure 2 The present disclosure provides a schematic diagram of the working principle of a subthreshold SRAM read / write auxiliary circuit. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] like Figure 1 As shown, this disclosure discloses a subthreshold SRAM read / write auxiliary circuit, which includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first capacitor CAP1.

[0022] The charge pump circuit consists of a first PMOS transistor MP1, a second PMOS transistor MP2, a first capacitor CAP1, and a first NMOS transistor MN1. The sources of both PMOS transistors MP1 and MP2 are connected to the positive terminal VDD of the power supply. The gate of MP1 is connected to the auxiliary enable signal AE. The drain of MP1 is connected to the positive plate N2 of the first capacitor CAP1. The drains of both MP2 and MN1 are connected to the negative plate N1 of the first capacitor CAP1. The gates of both MP2 and MN1 are connected to the inverted auxiliary enable signal AEN. The output voltage N2 of the charge pump circuit is controlled by the auxiliary enable signal AE and its inverted counterpart AEN to be either high or higher.

[0023] The undervoltage circuit is composed of a third PMOS transistor, MP3. The gate of MP3 is connected to the auxiliary enable signal AE, the source is connected to the output word line WL, and the drain is connected to the power supply ground line GND. The undervoltage circuit is activated by the auxiliary enable signal AE, and the output word line voltage WL is an intermediate level between high and low.

[0024] The pulse generation circuit consists of a fourth PMOS transistor MP4 and a second NMOS transistor MN2. The gates of both PMOS transistor MP4 and MN2 are connected to the input pulse signal PWL. The source of PMOS transistor MP4 is connected to the positive plate N2 of the first capacitor. The drains of both PMOS transistor MP4 and MN2 are connected to the output word line WL. The source of MN2 is connected to the power supply ground GND. The input pulse signal PWL controls the toggling of the output word line. When PWL is low, the output word line voltage is the intermediate level VL determined by the auxiliary enable signal AE. Figure 2 The signal VL) or higher level VH) Figure 2 The signal VH in the input pulse signal PWL is high; when the input pulse signal PWL is high, the output word line voltage is low.

[0025] Its working principle is as follows: During periods without read / write operations: the input pulse signal is high, the auxiliary circuit enable signal is low, the charge pump circuit does not perform level boosting, the undervoltage circuit is ineffective, and the output word line voltage is directly controlled and generated by the pulse generation circuit. Specifically, the second NMOS transistor MN2 is turned on, the fourth PMOS transistor MP4 is turned off, and the third PMOS transistor MP3 is bypassed by the second NMOS transistor MN2, resulting in a low output word line WL. Simultaneously, the first PMOS transistor MP1 is turned on, charging the positive plate N2 of the first capacitor CAP1 to a high level VDD; the second PMOS transistor MP2 is turned off, and the first NMOS transistor MN1 is turned on, discharging the negative plate of the first capacitor to a low level GND, thus forming an initial voltage difference ΔVi = VDD - GND between the two plates of the first capacitor.

[0026] When performing a read operation: the input pulse signal is low and the auxiliary circuit enable signal is low. At this time, the undervoltage circuit is turned on, the first PMOS transistor MP1 is turned on, the fourth PMOS transistor MP4 is turned on, the second NMOS transistor MN2 is turned off, the third PMOS transistor MP3 is turned on, and the output word line voltage is the intermediate level VL after being divided by the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3.

[0027] During a write operation: the input pulse signal is low, and the auxiliary enable signal is high. At this time, the charge pump circuit raises the voltage level. The first PMOS transistor MP1 is off, the second PMOS transistor MP2 is on, and the first NMOS transistor MN1 is off. The second PMOS transistor MP2 charges the negative plate N1 of the first capacitor CAP1 to a high level VDD. Since the voltage difference across the capacitor cannot change abruptly, ΔVi = V(N2) - V(N1) = VDD - GND, the voltage at the positive plate of the first capacitor is raised to a higher level than the power supply voltage, i.e., V(N2) = ΔVi + V(N1) = 2VDD - GND. The fourth PMOS transistor MP4 is on, the second NMOS transistor MN2 is off, and the third PMOS transistor MP3 is off. The V(N2) level is transmitted to the output word line through the second PMOS transistor MP2, and the output word line output voltage is a higher level VH = 2VDD - GND.

[0028] In summary, the specific functions of the subthreshold SRAM read / write auxiliary circuit disclosed herein are as follows: During periods when no read / write operations are performed, the charge pump circuit and undervoltage circuit in the auxiliary circuit are disabled, and the pulse generation circuit outputs a low-level word line voltage to ensure that the memory cell does not experience erroneous reads or writes; during read operations, the undervoltage circuit in the auxiliary circuit is activated, and the undervoltage circuit and pulse generation circuit jointly control the output word line voltage, which is an intermediate level VL between the power supply voltage VDD and the power supply ground GND; during write operations, the charge pump circuit in the auxiliary circuit raises the level, and the charge pump circuit and pulse generation circuit jointly control the output word line voltage, which is a higher level than the power supply voltage VDD, where the higher level is VH = 2VDD - GND. This disclosure spontaneously adjusts the word line WL level according to the read / write cycle, lowering the word line level during the read cycle and raising the word line level during the write cycle to improve read and write capabilities.

[0029] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A subthreshold SRAM read / write auxiliary circuit, characterized in that, include: The charge pump circuit, consisting of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a first capacitor, is used to generate a higher level than the power supply voltage at the output node. The undervoltage circuit, consisting of a third PMOS transistor, is used to generate an intermediate level at the output node that is lower than the supply voltage. The pulse generation circuit, composed of a fourth PMOS transistor and a second NMOS transistor, is used to generate word line pulses. The gate of the first PMOS transistor is connected to the auxiliary enable signal, and the drain of the first PMOS transistor is connected to the positive plate of the first capacitor; the drains of the second PMOS transistor and the first NMOS transistor are both connected to the negative plate of the first capacitor, and the gates of the second PMOS transistor and the first NMOS transistor are both connected to the inverse signal of the auxiliary enable signal. The source of the third PMOS transistor is connected to the output word line, and the gate of the third PMOS transistor is connected to the auxiliary enable signal. The source of the fourth PMOS transistor is connected to the positive plate of the first capacitor, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are both connected to the output word line, and the gate of the fourth PMOS transistor and the gate of the second NMOS transistor are both connected to the input pulse signal. During periods when no read or write operations are performed, the input pulse signal is at a high level, and the voltage of the output word line is at a low level. When a read operation is performed, the input pulse signal is at a low level and the auxiliary enable signal is at a low level, and the voltage of the output word line is at an intermediate level; When a write operation is performed, the input pulse signal is at a low level and the auxiliary enable signal is at a high level, and the voltage of the output word line is at an even higher level.

2. The subthreshold SRAM read / write auxiliary circuit according to claim 1, characterized in that, The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the power supply, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the ground of the power supply; the drain of the third PMOS transistor is connected to the ground.

3. The subthreshold SRAM read / write auxiliary circuit according to claim 2, characterized in that, When no read / write operation is performed, the input pulse signal is at a high level and the auxiliary enable signal is at a low level. At this time, the first PMOS transistor is turned on, charging the positive plate of the first capacitor to a high level; the second PMOS transistor is turned off, and the first NMOS transistor is turned on, discharging the negative plate of the first capacitor to a low level, thus forming an initial voltage difference between the positive and negative plates of the first capacitor.

4. The subthreshold SRAM read / write auxiliary circuit according to claim 3, characterized in that, When a read operation is performed, the input pulse signal is at a low level, the auxiliary enable signal is at a low level, the undervoltage circuit is turned on, the first PMOS transistor is turned on, the fourth PMOS transistor is turned on, the second NMOS transistor is turned off, the third PMOS transistor is turned on, and the word line output voltage is the intermediate level VL after being divided by the first PMOS transistor, the fourth PMOS transistor, and the third PMOS transistor.

5. The subthreshold SRAM read / write auxiliary circuit according to claim 4, characterized in that, During a write operation, the input pulse signal is low, and the auxiliary enable signal is high. At this time, the charge pump circuit performs a level boost, the undervoltage circuit is disabled, the first PMOS transistor is off, the second PMOS transistor is on, the third PMOS transistor is off, the fourth PMOS transistor is on, the first NMOS transistor is off, the second NMOS transistor is off, the second PMOS transistor charges the negative plate of the first capacitor to a high level, and the voltage of the positive plate of the first capacitor is boosted to a higher level than the power supply voltage. This higher level is transmitted to the output word line through the fourth PMOS transistor, and the output voltage of the output word line is at a higher level.

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