A multi-chip packaging method

Abstract

The application discloses a kind of multi-chip packaging methods, it is related to chip packaging technical field;To solve the problem that mold sealing material cannot completely fill and lead to mold sealing cavity exists;Specifically including the following steps: wafer one is passed through thinning and slicing to obtain chip one;After sticking DAF bonding material on the one side of chip one, two chips one are pasted on the substrate at one time;Wafer two is passed through thinning and slicing to obtain chip two;After sticking DAF bonding material on the one side of chip two, it is pasted on the chip one on the substrate;Bonding and mold sealing are carried out to overall structure;The pitch of two chip one is minimum cutting unit.The chip and chip of the application do not exist cavity problem, so that the width size of substrate is reduced, material loss is reduced, there is no bridge hole structure when packaging, solve the process flow complex in the prior art, product volume is large, not easy to carry and the mold sealing cavity problem when multiple chip packaging, improve product reliability.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a multi-chip packaging method. Background Technology

[0002] eMCP is a type of hybrid multi-chip packaging that vertically stacks various memory chips of different sizes within a plastic package. This method reduces package size and increases integration density, and is currently commonly used in mobile electronic products such as mobile phones and watches. Figure 2-4 As shown, the current eMCP packaging solution follows the conventional wafer cutting and surface mount process, and is packaged through stacking, bonding and molding processes. During the molding process, due to the presence of the bridge structure, it is necessary to test various types of molding filling materials. The best material is selected for production through DOE experiments. Under normal circumstances, it is necessary to use molding materials with ultrafine particles (10-20um) to fill the bridge structure.

[0003] However, filling bridge voids has two drawbacks: 1) it requires the use of ultrafine particle molding materials, which are expensive; 2) if the bridge void structure is particularly narrow, such as a length exceeding 1000µm and a width less than 200µm, with an aspect ratio exceeding 5:1, even using ultrafine particle molding materials cannot achieve 100% void-free results. Figure 5 As shown in the diagram, the eMCP 254ball package contains a controller chip, a flash memory chip, and a RAM chip. The RAM chip's size is limited by the chip and package dimensions. Furthermore, because the RAM chip covers the top of two LPDDR4X chips, a bridge-like structure is formed in a certain space. This structure is typically around 5000*200*80um in length, width, and height, making it extremely difficult to fill during the molding process. Therefore, due to the complex structure in existing technologies, the molding material cannot completely fill the gaps, and the internal molding voids lead to reduced product reliability. To address this, we propose a multi-chip packaging method. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a multi-chip packaging method.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A multi-chip packaging method includes the following steps: S1: The material wafer is thinned and diced to obtain chip one; S2: After attaching DAF adhesive material to one side of chip one, attach both chips one to the substrate at once; S3: The second material wafer is thinned and diced to obtain the second chip; S4: After attaching DAF adhesive material to one side of chip two, attach it to chip one on the substrate; S5: Bond and mold the overall structure.

[0006] Preferably, the overall size of the two chips is the smallest cutting unit.

[0007] Preferably, the spacing between the two chips is 0.

[0008] Preferably, the molding filler material for the two chips is a conventional particle.

[0009] Preferably, the size of the conventional particles is 50-80 μm.

[0010] Preferably, one of the two chips is of the same type.

[0011] Preferably, the two chips are processed as a whole by cutting, mounting and packaging them.

[0012] Preferably, the encapsulation method includes encapsulating 2D, 4D, 6D, and 8D structures.

[0013] Preferably, the packaging method is applicable to both eMCP type products and MCP type products.

[0014] The beneficial effects of this invention are as follows: This invention eliminates the gap between two chips, thus preventing voids between them. This reduces the width of the substrate, minimizing material loss, and eliminates bridge structures during packaging. It solves the problems of complex processes, large finished product size, poor portability, and voids in the molding of multiple chips in existing technologies, thereby improving product reliability.

[0015] This invention eliminates the need for expensive ultrafine particle molding materials, allowing the use of conventional molding materials to meet requirements, thus reducing material waste and lowering costs; it also eliminates the need for high-precision surface mount technology (SMT) equipment and processes, improving production efficiency and reducing production costs.

[0016] This invention cuts, mounts, and packages two chips as a whole, eliminating the need to cut the wafer into individual chips. This simplifies the wafer cutting process, improves the production efficiency of cutting and mounting, and thus increases packaging efficiency. The minimum packaging area of ​​the two chips can be further reduced, decreasing the amount of packaging material used, lowering production costs, and making the wafer more portable.

[0017] This invention provides a multi-chip packaging method applicable to 2D, 4D, 6D, and 8D packaging, and is not limited to the packaging of eMCP type products, but also includes the packaging of MCP type products, thus expanding the scope of application and making it easy to promote. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a multi-chip packaging method proposed in this invention. Figure 2 This is a schematic diagram of the first step of an existing eMCP packaging solution; Figure 3 This is a schematic diagram of the second step of an existing eMCP packaging solution; Figure 4 This is a top view of a packaged product using an existing eMCP packaging solution; Figure 5 This is a schematic diagram of the internal molding voids of a product using an existing eMCP packaging solution; Figure 6 This is a schematic diagram of S1 and S2 of a multi-chip packaging method proposed in this invention; Figure 7 This is a schematic diagram of S3 and S4 of a multi-chip packaging method proposed in this invention; Figure 8 This is a top view schematic diagram of a packaged product based on a multi-chip packaging method proposed in this invention; Figure 9 This is a schematic diagram of Embodiment 4 of a multi-chip packaging method proposed in this invention.

[0019] In the diagram: 1. Wafer 1, 2. Chip 1, 3. Substrate, 4. Wafer 2, 5. Chip 2. Detailed Implementation

[0020] The technical solution of this patent will be further described in detail below with reference to specific embodiments.

[0021] The embodiments of this patent are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this patent, and should not be construed as limiting this patent.

[0022] Example 1:

[0023] A multi-chip packaging method, such as Figure 1 and Figure 6-8 As shown, it includes the following steps: S1: The material wafer 1 is thinned and diced to obtain chip 2; S2: After attaching DAF adhesive material to one side of chip 2, attach both chips 2 to the substrate 3 at once; S3: The material wafer 24 is thinned and diced to obtain chip 25; S4: After attaching DAF adhesive material to one side of chip 25, attach it to chip 2 on substrate 3; S5: Bond and mold the overall structure.

[0024] The overall size of the two chips 2 is the smallest cutting unit.

[0025] The molding filler material for the two chips can be made of conventional particles (50-80um), without the need to use ultrafine particles (10-20um) to fill the mold, thus reducing the packaging cost.

[0026] The two chips 2 are of the same type. In this invention, the two chips 2 are cut, mounted and packaged as a whole.

[0027] In this embodiment, the present invention does not have a bridge structure during packaging, and there are no voids between chips; it does not require expensive ultra-fine particle molding materials, and conventional molding materials can meet the requirements; it does not require high-precision chip mounting equipment and modes, which improves production efficiency and reduces production costs; it simplifies the wafer-to-1 dicing process and improves the production efficiency of dicing and chip mounting by about 30%.

[0028] This invention eliminates the need to cut all wafer 1 into individual chips, improving the efficiency of cutting and die bonding, thereby increasing packaging efficiency; the minimum package area can be further reduced, reducing the amount of packaging material used, lowering production costs, and making it easy to carry; there is no need to worry about incomplete encapsulation between the two chips 2, resulting in better reliability; even if one of the two chips is defective, it can still be downgraded after packaging, without wasting chips.

[0029] This invention solves the problem of cavity in the mold when packaging multiple chips, and can also significantly improve the production efficiency of the packaging process.

[0030] Example 2:

[0031] A multi-chip packaging method, such as Figure 1 As shown, this embodiment makes the following additions based on embodiment 1: the multi-chip packaging method includes, but is not limited to, 2D packaging, and can also be used in packaging structures with more stacked chips, such as 4D, 6D, 8D packaging, etc.

[0032] In use, the multi-chip packaging method of this application can be applied to 2D, 4D, 6D, 8D packaging, etc., expanding its scope of application and making it easy to promote.

[0033] Example 3:

[0034] A multi-chip packaging method, such as Figure 1 As shown, this embodiment makes the following improvements based on embodiment 1: The multi-chip packaging method includes, but is not limited to, the packaging of eMCP type products, and can also be used for multi-chip MCP packaging, such as SSD chip packaging, which generally has 2, 4 or 8 chips inside, and can be carried out in the mode of packaging 2 chips at the same time.

[0035] This embodiment is not limited to the packaging of eMCP type products, but also includes the packaging of MCP type products, further expanding the scope of application and making it easy to promote.

[0036] Example 4:

[0037] A multi-chip packaging method, such as Figure 9 As shown, in order to reduce the width of the substrate 3, this embodiment makes the following improvements based on embodiment 1: there is no gap between the two chips 2, preferably, the spacing between the two chips 2 is 0, which can reduce the width of the substrate 3 and reduce costs.

[0038] In this embodiment, when the spacing between the two chips 2 is 0, the width of the substrate 3 can be reduced, thus lowering the cost.

[0039] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-chip packaging method, characterized in that, Includes the following steps: S1: The material wafer 1 (1) is thinned and diced to obtain chip 1 (2). S2: After attaching DAF adhesive material to one side of chip 1 (2), attach both chips 1 (2) to the substrate (3) at once; S3: The material wafer 2 (4) is thinned and diced to obtain chip 2 (5); S4: After attaching DAF adhesive material to one side of chip two (5), attach it to chip one (2) on the substrate (3); S5: Bond and mold the overall structure; The overall size of the two chips (2) is the smallest cutting unit; The spacing between the two chips (2) is 0; The molding filler material for the two chips (2) is made of conventional particles; The size of the conventional particles is 50-80 μm; The two chips (2) are of the same type.

2. The multi-chip packaging method according to claim 1, characterized in that, The two chips (2) are processed as follows: the two chips (2) are cut, mounted and packaged as a whole.

3. The multi-chip packaging method according to claim 1, characterized in that, The encapsulation method includes encapsulating 2D, 4D, 6D, and 8D structures.

4. The multi-chip packaging method according to claim 3, characterized in that, The packaging method is applicable to both eMCP type products and MCP type products.

Images