An electronic chip 3D packaging method and chip package

Abstract

The application provides an electronic chip 3D packaging method and a chip package. The top electrode of an upper chip group is extended to the bottom of a lower chip through an additive manufacturing method, and a first target electrode of each chip of the upper chip group is connected. The second target electrode at the bottom of the upper chip group is connected with the third target electrode at the bottom of the lower chip through the additive manufacturing method. The upper chip group and the lower chip are filled with glue for packaging to obtain the chip package. The redistribution layer is directly made through a metallization interconnection process, the interconnection of a carrier plate is avoided, a hot welding process such as soldering ball is not used, the production efficiency and the process quality are greatly improved, the process difficulty and the manufacturing cost are reduced, and the reliability of the product is ensured.

Description

Technical Field

[0001] This application relates to the field of chip 3D packaging technology, and in particular to a method for 3D packaging of electronic chips and a chip package. Background Technology

[0002] A chip is a general term for semiconductor components, also known as an integrated circuit (IC). With the development of integrated circuit technology, the package size of electronic chips is becoming increasingly miniaturized. 3D packaging is an inevitable trend. First, as chips become increasingly complex, the contradiction between chip area, yield, and complex processes becomes difficult to reconcile, necessitating the breakdown of large chips into smaller ones. Second, 3D packaging can utilize mature processes to implement functional modules that do not require the most advanced technology, thereby reducing costs.

[0003] Currently, the most advanced packaging technology in the field of electronic chip packaging is 3D packaging technology. Its process methods mostly use multilayer silicon substrates as the redistribution layer of the circuit, and the electrodes are soldered onto the circuit board using a solder ball process. The multi-point soldering technology is difficult, costly, and its reliability needs to be improved. Summary of the Invention

[0004] In view of the aforementioned problems, this application is made to provide an electronic chip 3D packaging method and chip package that overcomes or at least partially solves the aforementioned problems, comprising:

[0005] A 3D packaging method for electronic chips is disclosed for packaging an upper chipset and a lower chipset. The upper chipset comprises at least two chips, and electrodes are disposed at its top and bottom. An electrode is disposed at the bottom of the lower chipset. The method includes the following steps:

[0006] The top electrode of the upper chip group is extended to the bottom of the lower chip group by additive manufacturing, and the first target electrodes of each chip in the upper chip group are connected.

[0007] The second target electrode at the bottom of the upper chip assembly is connected to the third target electrode at the bottom of the lower chip assembly using additive manufacturing.

[0008] The upper chipset and the lower chipset are encapsulated with potting compound to obtain a chip package.

[0009] Further, the upper chipset includes two parallel-arranged first chips and second chips; the top of the first chip, the top of the second chip, and the bottom of the lower chip are respectively provided with a first electrode, a second electrode, a third electrode, and a fourth electrode, and the bottoms of the first chip and the second chip are respectively provided with a fifth electrode, a sixth electrode, a seventh electrode, an eighth electrode, a ninth electrode, and a tenth electrode; the step of extending the top electrode of the upper chipset to the bottom of the lower chip using additive manufacturing includes:

[0010] The third electrode of the first chip and the first electrode of the second chip are connected by additive manufacturing, and the fourth electrode of the first chip and the second electrode of the second chip are connected by additive manufacturing.

[0011] The first and second electrodes of the first chip, and the third and fourth electrodes of the second chip are extended to a preset plane by additive manufacturing; wherein the preset plane is lower than the bottom electrode of the lower chip.

[0012] Further, the step of extending the first and second electrodes of the first chip, and the third and fourth electrodes of the second chip to a predetermined plane by additive manufacturing includes:

[0013] The first electrode and the second electrode of the first chip are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the first conductive post and the second conductive post.

[0014] The third and fourth electrodes of the second chip are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the third conductive post and the fourth conductive post.

[0015] Furthermore, the step of connecting the first target electrodes of each chip in the upper-layer chipset includes:

[0016] The ninth electrode of the first chip and the sixth electrode of the second chip are connected by additive manufacturing, and the fifth electrode of the first chip and the eighth electrode of the second chip are connected to form a first interconnection path.

[0017] The eighth and tenth electrodes of the first chip are connected by additive manufacturing, and the eighth and tenth electrodes of the second chip are also connected.

[0018] Furthermore, the step of connecting the second target electrode of the upper-layer chipset to the third target electrode of the lower-layer chip using additive manufacturing includes:

[0019] The sixth and seventh electrodes of the first chip are connected to the first and second electrodes of the lower chip respectively by additive manufacturing, and the ninth and tenth electrodes of the second chip are connected to the third and fourth electrodes of the lower chip respectively.

[0020] The second and fourth electrodes of the lower-layer chip are connected by additive manufacturing to form a second interconnect path.

[0021] Further, the step of potting and encapsulating the upper chipset and the lower chipset to obtain a chip package includes:

[0022] The first interconnection path and the second interconnection path are extended to the preset plane by additive manufacturing.

[0023] The upper chipset and the lower chipset are encapsulated with encapsulating adhesive to a height not higher than the preset plane, and the encapsulating adhesive is dried to obtain the chip package.

[0024] Further, the step of extending the first interconnect path and the second interconnect path to the preset plane respectively by additive manufacturing includes:

[0025] A fifth conductive pillar is fabricated on the surface of the first interconnect path using additive manufacturing.

[0026] A sixth conductive pillar is fabricated on the surface of the second interconnection path using additive manufacturing; wherein the fifth and sixth conductive pillars extend to the preset plane respectively.

[0027] Furthermore, it also includes:

[0028] A first extended circuit, a second extended circuit, a third extended circuit, a fourth extended circuit, a fifth extended circuit, and a sixth extended circuit are respectively fabricated on the preset plane using additive manufacturing. The first extended circuit is connected to the first conductive post, the second extended circuit is connected to the second conductive post, the third extended circuit is connected to the third conductive post, the fourth extended circuit is connected to the fourth conductive post, the fifth extended circuit is connected to the fifth conductive post, and the sixth extended circuit is connected to the sixth conductive post.

[0029] Furthermore, the additive manufacturing method includes one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.

[0030] To achieve this, this application also provides a chip package prepared according to the above-described 3D packaging method for electronic chips, comprising an upper chip assembly, a lower chip, and an encapsulating adhesive layer, wherein the encapsulating adhesive layer encapsulates the upper chip assembly and the lower chip, and the upper chip assembly and the lower chip are interconnected and extend to the surface of the encapsulating adhesive layer.

[0031] This application has the following advantages:

[0032] In the embodiments of this application, in response to the technical problem of "high difficulty in multi-point soldering" in the prior art, this application provides a solution that avoids thermal soldering processes such as solder balls. Specifically, it involves: extending the top electrode of the upper chipset to the bottom of the lower chipset using additive manufacturing, and connecting the first target electrodes of each chip in the upper chipset; connecting the second target electrode at the bottom of the upper chipset to the third target electrode at the bottom of the lower chipset using additive manufacturing; and encapsulating the upper chipset and the lower chipset with potting resin to obtain a chip package. By directly performing a metallization interconnect process to create a redistribution layer, the use of a carrier board interconnect is avoided, and thermal soldering processes such as solder balls are not used, which greatly improves production efficiency and process quality, reduces process difficulty and manufacturing costs, and ensures product reliability. Attached Figure Description

[0033] To more clearly illustrate the technical solution of this application, the drawings used in the description of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a flowchart illustrating the steps of a 3D packaging method for an electronic chip according to an embodiment of this application;

[0035] Figure 2 This is a schematic flowchart of an embodiment of an electronic chip 3D packaging method provided in this application;

[0036] Figure 3 This is a schematic diagram of the internal structure of a chip package provided in an embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the internal structure of a chip package provided in an embodiment of this application.

[0038] The reference numerals in the accompanying drawings are as follows:

[0039] 110, First chip; 120, Second chip; 130, First interconnect path; 210, Lower-level chip; 220, Second interconnect path; 310, First conductive post; 320, Second conductive post; 330, Third conductive post; 340, Fourth conductive post; 350, Fifth conductive post; 360, Sixth conductive post; 410, First expansion circuit; 420, Second expansion circuit; 430, Third expansion circuit; 440, Fourth expansion circuit; 450, Fifth expansion circuit; 460, Sixth expansion circuit. Detailed Implementation

[0040] To make the objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0041] It should be noted that, in any embodiment of this application, the electronic chip 3D packaging method is used to package an upper chipset and a lower chip 210. The upper chipset includes at least two chips, and electrodes are respectively disposed at the top and bottom of the upper chipset. Electrodes are disposed at the bottom of the lower chip 210. As an example, the upper chipset includes two parallel first chips 110 and second chips 120. The top of the first chip 110, the top of the second chip 120, and the bottom of the lower chip 210 are respectively provided with four electrodes arranged in two columns and two rows, from top to bottom and from left to right: first electrode, second electrode, third electrode, and fourth electrode. The bottoms of the first chip 110 and the second chip 120 are respectively provided with six electrodes arranged in two columns and three rows, from top to bottom and from left to right: fifth electrode, sixth electrode, seventh electrode, eighth electrode, ninth electrode, and tenth electrode.

[0042] Reference Figure 1-2 This application illustrates an embodiment of a 3D packaging method for an electronic chip, the method comprising:

[0043] S110. The top electrode of the upper chip group is extended to the bottom of the lower chip 210 by additive manufacturing, and the first target electrodes of each chip in the upper chip group are connected.

[0044] S120. The second target electrode at the bottom of the upper chip assembly is connected to the third target electrode at the bottom of the lower chip 210 by additive manufacturing.

[0045] S130. The upper chipset and the lower chip 210 are encapsulated with potting compound to obtain a chip package.

[0046] In the embodiments of this application, in contrast to the technical problem of "high difficulty in multi-point soldering" in the prior art, this application provides a solution that avoids thermal soldering processes such as solder balls. Specifically, the top electrode of the upper chip group is extended to the bottom of the lower chip 210 through additive manufacturing, and the first target electrodes of each chip in the upper chip group are connected; the second target electrode at the bottom of the upper chip group is connected to the third target electrode at the bottom of the lower chip 210 through additive manufacturing; the upper chip group and the lower chip 210 are encapsulated with potting compound to obtain a chip package. By directly performing a metallization interconnect process to redistribute the layer, the use of a carrier board interconnect is avoided, and thermal soldering processes such as solder balls are not used, which greatly improves production efficiency and process quality, reduces process difficulty and manufacturing cost, and ensures product reliability.

[0047] The following will further describe an electronic chip 3D packaging method in this exemplary embodiment.

[0048] As described in step S110, the top electrode of the upper chip group is extended to the bottom of the lower chip 210 by additive manufacturing, and the first target electrodes of each chip in the upper chip group are connected.

[0049] In one embodiment of the present invention, the specific process of "extending the top electrode of the upper chip group to the bottom of the lower chip 210 by additive manufacturing" described in step S110 can be further explained in conjunction with the following description.

[0050] As described in the following steps, the third electrode of the first chip 110 and the first electrode of the second chip 120 are connected by additive manufacturing, and the fourth electrode of the first chip 110 and the second electrode of the second chip 120 are connected.

[0051] As described in the following steps, the first and second electrodes of the first chip 110, and the third and fourth electrodes of the second chip 120 are extended to a preset plane by additive manufacturing; wherein the preset plane is lower than the bottom electrode of the lower chip 210.

[0052] It should be noted that additive manufacturing (AM), also known as 3D printing, is a manufacturing technology that uses digital model files as a basis and employs software and CNC systems to deposit specialized metallic, non-metallic, or medical / biological materials layer by layer through methods such as extrusion, sintering, melting, photopolymerization, and spraying to create physical objects. Specifically, the additive manufacturing methods involved in this application can be one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.

[0053] In one specific implementation, the first chip 110 and the second chip 120 are arranged at intervals on a first carrier board, with the top electrodes of each upper chip group facing upwards, and a first encapsulating adhesive layer is laid on the periphery of the upper chip group, such that the first encapsulating adhesive layer is not higher than the top electrode of the upper chip group.

[0054] The first encapsulating layer is made of an encapsulating adhesive, specifically, one or more of epoxy resin, silicone, PI (Polyimide) resin, PE (Polyethylene) resin, and PT (Phenolic Triazine) resin. The first encapsulating layer formed after curing has good insulation and sealing properties, providing protection and preventing the product from getting damp.

[0055] In one specific implementation, a photosensitive material is coated on the surface of the first encapsulating adhesive layer, and then exposed and developed to expose the first target area on the surface of each of the first encapsulating adhesive layers. The photosensitive material that has undergone photopolymerization is cured to form a first photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the first target area) is washed away. The photosensitive material includes one or more of the following: photoresist (including positive and negative photoresist), photosensitive polyimide resin, photosensitive sol-gel or mixtures or compositions thereof, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, which has good photosensitivity properties.

[0056] The third electrode of the first chip 110 and the first electrode of the second chip 120 are connected and made conductive on the surface of the first target area by additive manufacturing, and the fourth electrode of the first chip 110 and the second electrode of the second chip 120 are connected and made conductive. Finally, the first photosensitive material layer is removed by adhesive remover.

[0057] In one embodiment of the present invention, the specific process of "extending the first electrode and the second electrode of the first chip 110, and the third electrode and the fourth electrode of the second chip 120 to a preset plane by additive manufacturing" can be further described in conjunction with the following description.

[0058] As described in the following steps, the first electrode and the second electrode of the first chip 110 are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the first conductive post 310 and the second conductive post 320.

[0059] As described in the following steps, the third electrode and the fourth electrode of the second chip 120 are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the third conductive post 330 and the fourth conductive post 340.

[0060] In one specific implementation, four longitudinally extending through-holes are formed inside the first encapsulating adhesive layer, and the through-holes are respectively located on both sides of the upper chip assembly. Specifically, a photosensitive material is coated on the surface of the first encapsulating adhesive layer, and then exposed and developed to expose the second target area on the surface of each of the first encapsulating adhesive layers. The photosensitive material that has undergone photopolymerization is cured to form a second photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the second target area) is washed away.

[0061] A first conductive post 310, a second conductive post 320, a third conductive post 330, and a fourth conductive post 340 extending longitudinally are respectively fabricated on the surface of the second target area by additive manufacturing, such that the top of the conductive post extends to the preset height.

[0062] By using additive manufacturing, the first electrode and the second electrode of the first chip 110 are connected and made conductive to the first conductive post 310 and the second conductive post 320, respectively, on the surface of the second target area, and the third electrode and the fourth electrode of the second chip 120 are connected and made conductive to the third conductive post 330 and the fourth conductive post 340, respectively.

[0063] Finally, the second photosensitive material layer is removed using a remover.

[0064] In one specific implementation, encapsulating adhesive is poured onto the surface of the first encapsulating adhesive layer, causing the encapsulating adhesive to submerge the upper chipset, forming a protective layer to prevent the product from getting damp.

[0065] In one embodiment of the present invention, the specific process of "connecting the first target electrodes of each chip in the upper-layer chipset" described in step S110 can be further explained in conjunction with the following description.

[0066] As described in the following steps, the ninth electrode of the first chip 110 and the sixth electrode of the second chip 120 are connected by additive manufacturing, and the fifth electrode of the first chip 110 and the eighth electrode of the second chip 120 are connected to form a first interconnection path 130.

[0067] As described in the following steps, the eighth and tenth electrodes of the first chip 110 are connected by additive manufacturing, and the eighth and tenth electrodes of the second chip 120 are connected.

[0068] In one specific implementation, the upper-layer chipset is flipped onto a second carrier tape, and the first carrier tape is removed, exposing the bottom electrodes and conductive pillars of the upper-layer chipset. A photosensitive material is coated on the surface of the first encapsulating adhesive layer, and then exposed and developed to expose a third target region on the surface of the first encapsulating adhesive layer. The photosensitive material that has undergone photopolymerization is cured to form a third photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the third target region) is washed away.

[0069] The ninth electrode of the first chip 110 and the sixth electrode of the second chip 120 are connected and made conductive on the surface of the third target region by additive manufacturing, and the fifth electrode of the first chip 110 and the eighth electrode of the second chip 120 are connected to form the first interconnection path 130.

[0070] The third photosensitive material layer is then removed using a remover.

[0071] In one specific implementation, a fifth conductive pillar 350 is fabricated on the surface of the first interconnect path 130 using additive manufacturing, extending the fifth conductive pillar 350 to a first preset plane. The method of fabricating the fifth conductive pillar 350 is the same as that of fabricating the first conductive pillar 310, etc., and will not be described again here. Then, all the previously fabricated conductive pillars, as well as the electrodes that are not connected to the bottom of the first chip 110 and the second chip 120, are extended vertically to the first preset plane using additive manufacturing. Finally, encapsulating adhesive is poured in until the top of the extended electrodes is just exposed, and after drying, a second encapsulating adhesive layer is formed.

[0072] In one specific implementation, a photosensitive material is coated on the surface of the second encapsulating adhesive layer, and then exposed and developed to expose the fourth target area on the surface of the second encapsulating adhesive layer. The photosensitive material that has undergone photopolymerization is cured to form a fourth photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the fourth target area) is washed away.

[0073] The eighth and tenth electrodes of the first chip 110 are connected and made conductive on the surface of the fourth target region by additive manufacturing, and the eighth and tenth electrodes of the second chip 120 are also connected and made conductive.

[0074] The fourth photosensitive material layer is then removed using a remover.

[0075] In one specific implementation, all previously prepared conductive pillars, as well as the electrodes not connected to the bottom of the first chip 110 and the second chip 120, are extended vertically to a second preset plane using additive manufacturing. Finally, encapsulating adhesive is poured in until the tops of the extended electrodes are just exposed, and after drying, a third encapsulating adhesive layer is formed.

[0076] As described in step S120, the second target electrode at the bottom of the upper chip assembly is connected to the third target electrode at the bottom of the lower chip 210 by additive manufacturing.

[0077] In one embodiment of the present invention, the specific process of "connecting the second target electrode at the bottom of the upper chip assembly to the third target electrode at the bottom of the lower chip 210 by additive manufacturing" described in step S120 can be further explained in conjunction with the following description.

[0078] As described in the following steps, the sixth and seventh electrodes of the first chip 110 are connected to the first and second electrodes of the lower chip 210 respectively by additive manufacturing, and the ninth and tenth electrodes of the second chip 120 are connected to the third and fourth electrodes of the lower chip 210 respectively.

[0079] As described in the following steps, the second electrode and the fourth electrode of the lower layer chip 210 are connected by additive manufacturing to form a second interconnect path 220.

[0080] In one specific implementation, the lower chip 210 is placed on the surface of the third encapsulating adhesive layer, with the electrode surface of the lower chip 210 facing upwards. A photosensitive material is coated on the surface of the third encapsulating adhesive layer, and exposure and development are performed to expose the fifth target region on the surface of the third encapsulating adhesive layer. The photosensitive material that has undergone photopolymerization is cured to form a fifth photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the fifth target region) is washed away.

[0081] By using additive manufacturing, the sixth and seventh electrodes of the first chip 110, the ninth and tenth electrodes of the second chip 120, and the five conductive pillars prepared in the above steps are all extended vertically to the plane where the electrodes of the lower chip 210 are located.

[0082] Then, the fifth photosensitive material layer is removed by adhesive remover, and encapsulating adhesive is poured in until the electrode is just exposed. After drying the encapsulating adhesive, a fourth encapsulating adhesive layer is formed.

[0083] In one specific implementation, a photosensitive material is coated on the surface of the fourth encapsulating adhesive layer, and then exposed and developed to expose the sixth target area on the surface of the fourth encapsulating adhesive layer. The photosensitive material that has undergone photopolymerization is cured to form the sixth photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the sixth target area) is washed away.

[0084] By using additive manufacturing, the sixth and seventh electrodes of the first chip 110 are connected and made conductive to the first and second electrodes of the lower chip 210 on the surface of the sixth target region, respectively. The ninth and tenth electrodes of the second chip 120 are connected and made conductive to the third and fourth electrodes of the lower chip 210, respectively. The seventh electrode of the first chip 110 and the tenth electrode of the second chip 120 are connected to form the second interconnection path 220 (equivalent to connecting the second and fourth electrodes of the lower chip 210).

[0085] The sixth photosensitive material layer is then removed using a glue remover.

[0086] In one specific implementation, a sixth conductive post 360 is fabricated on the surface of the second interconnection path 220 using additive manufacturing, extending the sixth conductive post 360 to a second preset plane. The method for fabricating the sixth conductive post 360 is the same as that for fabricating the fifth conductive post 350, and will not be described again here. Then, all the previously fabricated conductive posts are extended vertically to the second preset plane using additive manufacturing.

[0087] It should be noted that the conductive pillars can be made of the same conductive material as the electrodes of the upper chipset or the electrodes of the lower chip 210.

[0088] As described in step S130, the upper chipset and the lower chip 210 are encapsulated with potting compound to obtain a chip package.

[0089] In one specific implementation, encapsulating adhesive is poured onto the surface of the second preset plane until it just exposes the top tip of the extended electrode. The encapsulating adhesive is then dried to form a fifth encapsulating adhesive layer. Specifically, the encapsulating adhesive is dried at 60-160°C to form the fifth encapsulating adhesive layer.

[0090] In one embodiment of this application, it further includes:

[0091] A first extended circuit 410, a second extended circuit 420, a third extended circuit 430, a fourth extended circuit 440, a fifth extended circuit 450, and a sixth extended circuit 460 are respectively fabricated on the preset plane using additive manufacturing. The first extended circuit 410 is connected to the first conductive post 310, the second extended circuit 420 is connected to the second conductive post 320, the third extended circuit 430 is connected to the third conductive post 330, the fourth extended circuit 440 is connected to the fourth conductive post 340, the fifth extended circuit 450 is connected to the fifth conductive post 350, and the sixth extended circuit 460 is connected to the sixth conductive post 360.

[0092] As an example, the thickness of the first expansion circuit 410 is 35-60 micrometers, the thickness of the second expansion circuit 420 is 35-60 micrometers, the thickness of the third expansion circuit 430 is 35-60 micrometers, the thickness of the fourth expansion circuit 440 is 35-60 micrometers, the thickness of the fifth expansion circuit 450 is 35-60 micrometers, and the thickness of the sixth expansion circuit 460 is 35-60 micrometers.

[0093] In one specific implementation, a photosensitive material is coated on the surface of the fifth encapsulating adhesive layer, and then exposed and developed to expose the seventh target area on the surface of the fifth encapsulating adhesive layer. The photosensitive material that has undergone photopolymerization is cured to form the seventh photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the seventh target area) is washed away.

[0094] The first extended circuit 410 corresponding to the first conductive post 310, the second extended circuit 420 corresponding to the second conductive post 320, the third extended circuit 430 corresponding to the third conductive post 330, the fourth extended circuit 440 corresponding to the fourth conductive post 340, the fifth extended circuit 450 corresponding to the fifth conductive post 350, and the sixth extended circuit 460 corresponding to the sixth conductive post 360 are respectively fabricated on the surface of the seventh target area by additive manufacturing.

[0095] The seventh photosensitive material layer is then removed using a remover.

[0096] In one specific embodiment, a 3D packaging method for an electronic chip:

[0097] 1. Arrange the first chip 110 and the second chip 120 in batches on the first carrier board with their upper electrodes facing upwards;

[0098] 2. Fill the electrode positions with encapsulating adhesive;

[0099] 3. Make through holes at the designed locations;

[0100] 4. Metallize the through-hole to obtain a conductive pillar;

[0101] 5. Create a mask and selectively connect metallized electrodes;

[0102] 6. Apply encapsulating adhesive as a protective layer;

[0103] 7. Flip the upper-layer chipset onto the second carrier board;

[0104] 8. Remove the first carrier board to expose the lower electrode and conductive pillars of the upper chipset;

[0105] 9. Make a mask and connect the first layer of electrodes at the bottom of the upper chipset;

[0106] 10. Selectively grow the remaining electrodes to the designed height;

[0107] 11. Fill the encapsulating adhesive to the top of the electrode;

[0108] 12. Make a mask and connect the second layer of electrodes at the bottom of the upper chipset;

[0109] 13. Selectively grow the remaining electrodes to the designed height;

[0110] 14. Fill the encapsulating adhesive to the top of the electrode;

[0111] 15. Place the lower-level chip 210;

[0112] 16. The height of the long electrode is consistent with the electrode height of the lower chip 210;

[0113] 17. Fill the encapsulating adhesive to the top of the electrode;

[0114] 18. Make a mask and metallize the chip electrodes;

[0115] 19. Grow the remaining electrodes to the designed height;

[0116] 20. Fill the encapsulating adhesive to the top of the electrode;

[0117] 21. Make a mask to enlarge the electrode, then cut it into shape;

[0118] 22. Remove the carrier plate; the product is now complete.

[0119] Reference Figure 3-4This illustration shows a chip package prepared according to any of the above-described 3D packaging methods for electronic chips, provided by an embodiment of this application. The package includes an upper chipset, a lower chip 210, and an encapsulating adhesive layer. The encapsulating adhesive layer encapsulates the upper chipset and the lower chip 210, and the upper chipset and the lower chip 210 are interconnected and extend to the surface of the encapsulating adhesive layer. The chip package exhibits high product reliability and high packaging efficiency.

[0120] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0121] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0122] The above provides a detailed description of an electronic chip 3D packaging method and chip package provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A 3D packaging method for electronic chips, used for packaging an upper chipset and a lower chipset, wherein the upper chipset comprises at least two chips, electrodes are respectively disposed at the top and bottom of the upper chipset, and an electrode is disposed at the bottom of the lower chipset, characterized in that, Including the following steps: The top electrode of the upper chip group is extended to the bottom of the lower chip group by additive manufacturing, and the first target electrodes of each chip in the upper chip group are connected. The second target electrode at the bottom of the upper chip assembly is connected to the third target electrode at the bottom of the lower chip assembly using additive manufacturing. The upper chipset and the lower chipset are encapsulated with potting compound to obtain a chip package.

2. The 3D packaging method for electronic chips according to claim 1, characterized in that, The upper-layer chipset includes two parallel chips, a first chip and a second chip; the top of the first chip, the top of the second chip, and the bottom of the lower-layer chip are respectively provided with a first electrode, a second electrode, a third electrode, and a fourth electrode, and the bottom of the first chip and the second chip are respectively provided with a fifth electrode, a sixth electrode, a seventh electrode, an eighth electrode, a ninth electrode, and a tenth electrode. The step of extending the top electrode of the upper chip assembly to the bottom of the lower chip using additive manufacturing includes: The third electrode of the first chip and the first electrode of the second chip are connected by additive manufacturing, and the fourth electrode of the first chip and the second electrode of the second chip are connected by additive manufacturing. The first and second electrodes of the first chip, and the third and fourth electrodes of the second chip are extended to a preset plane by additive manufacturing; wherein the preset plane is lower than the bottom electrode of the lower chip.

3. The 3D packaging method for electronic chips according to claim 2, characterized in that, The step of extending the first and second electrodes of the first chip, and the third and fourth electrodes of the second chip to a predetermined plane by additive manufacturing includes: The first electrode and the second electrode of the first chip are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the first conductive post and the second conductive post. The third and fourth electrodes of the second chip are extended outward in the horizontal direction by additive manufacturing, and the extended ends are extended vertically to the preset plane to obtain the third conductive post and the fourth conductive post.

4. The 3D packaging method for electronic chips according to claim 3, characterized in that, The step of connecting the first target electrodes of each chip in the upper-layer chipset includes: The ninth electrode of the first chip and the sixth electrode of the second chip are connected by additive manufacturing, and the fifth electrode of the first chip and the eighth electrode of the second chip are connected to form a first interconnection path. The eighth and tenth electrodes of the first chip are connected by additive manufacturing, and the eighth and tenth electrodes of the second chip are also connected.

5. The 3D packaging method for electronic chips according to claim 4, characterized in that, The step of connecting the second target electrode of the upper-layer chip assembly to the third target electrode of the lower-layer chip using additive manufacturing includes: The sixth and seventh electrodes of the first chip are connected to the first and second electrodes of the lower chip respectively by additive manufacturing, and the ninth and tenth electrodes of the second chip are connected to the third and fourth electrodes of the lower chip respectively. The second and fourth electrodes of the lower-layer chip are connected by additive manufacturing to form a second interconnect path.

6. The 3D packaging method for electronic chips according to claim 5, characterized in that, The step of potting and encapsulating the upper-layer chipset and the lower-layer chipset to obtain a chip package includes: The first interconnection path and the second interconnection path are extended to the preset plane by additive manufacturing. The upper chipset and the lower chipset are encapsulated with encapsulating adhesive to a height not higher than the preset plane, and the encapsulating adhesive is dried to obtain the chip package.

7. The 3D packaging method for electronic chips according to claim 6, characterized in that, The step of extending the first interconnect path and the second interconnect path to the preset plane by additive manufacturing includes: A fifth conductive pillar is fabricated on the surface of the first interconnect path using additive manufacturing. A sixth conductive pillar is fabricated on the surface of the second interconnection path using additive manufacturing; wherein the fifth and sixth conductive pillars extend to the preset plane respectively.

8. The 3D packaging method for electronic chips according to claim 7, characterized in that, Also includes: A first extended circuit, a second extended circuit, a third extended circuit, a fourth extended circuit, a fifth extended circuit, and a sixth extended circuit are respectively fabricated on the preset plane using additive manufacturing. The first extended circuit is connected to the first conductive post, the second extended circuit is connected to the second conductive post, the third extended circuit is connected to the third conductive post, the fourth extended circuit is connected to the fourth conductive post, the fifth extended circuit is connected to the fifth conductive post, and the sixth extended circuit is connected to the sixth conductive post.

9. The 3D packaging method for electronic chips according to claim 1, characterized in that, The additive manufacturing methods include one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.

10. A chip package prepared by the 3D packaging method for electronic chips according to any one of claims 1-9, characterized in that, It includes an upper chipset, a lower chip, and an encapsulating adhesive layer. The encapsulating adhesive layer encapsulates the upper chipset and the lower chip, and the upper chipset and the lower chip are interconnected and extend to the surface of the encapsulating adhesive layer.

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