Semiconductor devices, methods for manufacturing semiconductor devices, and methods for reusing substrates.

Abstract

This invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a method for reusing a substrate. According to one embodiment, the method for manufacturing a semiconductor device includes the following steps: forming a first film comprising a first element on a first substrate, and forming a second film comprising a semiconductor layer on a second substrate, wherein the semiconductor layer is porousized to become a porous layer. The method further includes the following steps: forming a third film comprising a second element on the second film, and bonding the first substrate and the second substrate such that the first film, the third film, and the second film are sandwiched together. The method further includes the following step: separating the first substrate from the second substrate at the location of the second film.

Description

[0001] [Cross-reference to related applications]

[0002] This application is based on and asserts the priority interest of prior art Japanese Patent Application No. 2021-152458, filed on September 17, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, and a method for reusing a substrate. Background Technology

[0004] When manufacturing semiconductor devices by bonding one substrate to another, these substrates may sometimes need to be separated after bonding. In this case, it is ideal to use a method that can properly separate these substrates. Summary of the Invention

[0005] One embodiment provides a semiconductor device capable of properly separating bonded substrates from each other, a method for manufacturing the semiconductor device, and a method for reusing the substrates.

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes the following steps: forming a first film comprising a first element on a first substrate, forming a second film comprising a semiconductor layer on a second substrate, and perforating the semiconductor layer to become a porous layer. The method further includes the following steps: forming a third film comprising a second element on the second film, and bonding the first substrate and the second substrate such that the first film, the third film, and the second film are sandwiched together. The method further includes the following step: separating the first substrate from the second substrate at the location of the second film.

[0007] According to the aforementioned configuration, a semiconductor device capable of appropriately separating bonded substrates from each other, a method for manufacturing the semiconductor device, and a method for reusing the substrates can be provided. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figures 3(a) to (c) are cross-sectional views (1 / 2) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figures 4(a) to (c) are cross-sectional views (2 / 2) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figures 5(a) and (b) are cross-sectional views (1 / 5) showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0013] Figures 6(a) and (b) are cross-sectional views (2 / 5) showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0014] Figures 7(a) and (b) are cross-sectional views (3 / 5) showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0015] Figures 8(a) and (b) are cross-sectional views (4 / 5) showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0016] Figures 9(a) and (b) are cross-sectional views (5 / 5) showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0017] Figures 10(a) and (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0018] Figures 11(a) to (c) are cross-sectional views showing a method for manufacturing a semiconductor device according to another variation of the first embodiment.

[0019] Figure 12 This is a cross-sectional view showing the structure of a semiconductor device according to another variation of the first embodiment.

[0020] Figures 13(a) to (c) are cross-sectional views (1 / 2) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0021] Figures 14(a) to (c) are cross-sectional views (2 / 2) showing the manufacturing method of the semiconductor device according to the second embodiment.

[0022] Figures 15(a) to (c) are cross-sectional views (1 / 2) showing a method for manufacturing a semiconductor device according to a variation of the second embodiment.

[0023] Figures 16(a) to (c) are cross-sectional views (2 / 2) showing a method for manufacturing a semiconductor device according to a variation of the second embodiment. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1-Figure 2 In section 6, the same symbols are used to mark the same components, and repeated explanations are omitted.

[0025] (First Embodiment) Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1Semiconductor devices, for example, are 3D flash memory.

[0026] Figure 1 The semiconductor device includes a circuit region 1 containing CMOS (Complementary Metal Oxide Semiconductor) circuitry and an array region 2 containing a memory cell array. The memory cell array has multiple memory cells for storing data, and the CMOS circuitry has peripheral circuitry for controlling the operation of the memory cell array. The memory cell array and the CMOS circuitry are examples of the first and second elements. Figure 1 The semiconductor device is manufactured, for example, by bonding a circuit wafer containing circuit region 1 and an array wafer containing array region 2, as described below. The symbol S represents the bonding surface between circuit region 1 and array region 2.

[0027] Figure 1 The diagram illustrates the mutually perpendicular X, Y, and Z directions. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. For example, CMOS region 1 is illustrated in the -Z direction of array region 2, and therefore located below array region 2. Furthermore, the -Z direction may or may not align with the direction of gravity.

[0028] exist Figure 1 In the circuit region 1, there are a substrate 11, a transistor 12, an interlayer insulating film 13, multiple contact plugs 14, a wiring layer 15 containing multiple wirings, a via plug 16, and a metal pad 17. Figure 1 The diagram shows three of a plurality of wirings within wiring layer 15 and three contact plugs 14 disposed on these wirings. Substrate 11 is an example of a first substrate. Interlayer insulating film 13 is an example of a first film.

[0029] exist Figure 1 In the array region 2, there are interlayer insulating film 21, metal pads 22, through-hole plugs 23, wiring layer 24 containing multiple wirings, multiple contact plugs 25, stacked film 26, multiple columnar portions 27, source layer 28 and insulating film 29. Figure 1 The diagram shows one of a plurality of wirings within wiring layer 24, and three contact plugs 25 and three columnar portions 27 disposed on the wiring. The laminated film 26 is an example of a third film.

[0030] Furthermore, such as Figure 1 As shown, the multilayer film 26 includes multiple electrode layers 31 and multiple insulating layers 32. Each columnar portion 27 includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The source layer 28 includes a semiconductor layer 37 and a metal layer 38.

[0031] The following is for reference. Figure 1 The structure of the semiconductor device in this embodiment will be described.

[0032] The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The transistor 12 includes a gate insulating film 12a and a gate electrode 12b sequentially formed on the substrate 11, and a source diffusion layer and a drain diffusion layer (not shown) formed within the substrate 11. The transistor 12, for example, constitutes the CMOS circuit. An interlayer insulating film 13 is formed on the substrate 11 to cover the transistor 12. The interlayer insulating film 13 is, for example, a SiO2 film (silicon oxide film), or a multilayer film comprising a SiO2 film and other insulating films.

[0033] Contact plug 14, wiring layer 15, through-hole plug 16, and metal pad 17 are formed within the interlayer insulating film 13. Specifically, contact plug 14 is disposed on substrate 11 or on gate electrode 12b of transistor 12. Figure 1 In this configuration, contact plugs 14 on substrate 11 are disposed on source and drain diffusion layers (not shown) of transistor 12. Wiring layer 15 is disposed on contact plugs 14, and via plugs 16 are disposed on wiring layer 15. Metal pads 17 are disposed on via plugs 16 above substrate 11. Metal pads 17 are, for example, metal layers containing Cu (copper) layers.

[0034] Interlayer insulating film 21 is formed on interlayer insulating film 13. Interlayer insulating film 21 is, for example, a SiO2 film, or a laminated film containing a SiO2 film and other insulating films.

[0035] Metal pads 22, via plugs 23, wiring layers 24, and contact plugs 25 are formed within the interlayer insulating film 21. Specifically, the metal pads 22 are disposed on metal pads 17 above the substrate 11. The metal pads 22 are, for example, metal layers containing Cu layers. The via plugs 23 are disposed on the metal pads 22, and the wiring layers 24 are disposed on the via plugs 23. Figure 1 The diagram shows one of a plurality of wirings within wiring layer 24, which functions, for example, as a bit line. A contact plug 25 is disposed on wiring layer 24.

[0036] The laminated film 26 is disposed on the interlayer insulating film 21 and includes a plurality of electrode layers 31 and a plurality of insulating layers 32 alternately laminated in the Z direction. The electrode layers 31 are, for example, metal layers containing W (tungsten) layers and function as word lines. The insulating layers 32 are, for example, SiO2 films.

[0037] Each columnar portion 27 is disposed within the stacked film 26 and includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The memory insulating film 33 is formed on the side of the stacked film 26 and has a tubular shape extending in the Z direction. The channel semiconductor layer 34 is formed on the side of the memory insulating film 33 and has a tubular shape extending in the Z direction. The core insulating film 35 and the core semiconductor layer 36 are formed on the side of the channel semiconductor layer 34 and have a rod-like shape extending in the Z direction. Specifically, the core semiconductor layer 36 is disposed on the contact plug 25, and the core insulating film 35 is disposed on the core semiconductor layer 36.

[0038] As described below, the memory insulating film 33 sequentially comprises, for example, a barrier insulating film, a charge storage layer, and a tunnel insulating film. The barrier insulating film is, for example, a SiO2 film. The charge storage layer is, for example, a SiN film (silicon nitride film). The tunnel insulating film is, for example, a SiO2 film or a SiON film (silicon oxynitride film). The channel semiconductor layer 34 is, for example, a polycrystalline silicon layer. The core insulating film 35 is, for example, a SiO2 film. The core semiconductor layer 36 is, for example, a polycrystalline silicon layer. Each memory cell within the memory cell array is composed of the channel semiconductor layer 34, the charge storage layer, the electrode layer 31, etc.

[0039] The channel semiconductor layer 34 and core semiconductor layer 36 within each columnar portion 27 are electrically connected to the metal pad 22 via contact plugs 25, wiring layers 24, and through-hole plugs 23. Therefore, the memory cell array within the array region 2 is electrically connected to the peripheral circuitry within the circuit region 1 via metal pads 22 or 17. This allows the operation of the memory cell array to be controlled via the peripheral circuitry.

[0040] The source layer 28 includes a semiconductor layer 37 and a metal layer 38 sequentially formed on the multilayer film 26 and the pillars 27, serving as a source line. In this embodiment, the channel semiconductor layer 34 of each pillar 27 is exposed from the memory insulating film 33, and the semiconductor layer 37 is formed directly on the channel semiconductor layer 34. Furthermore, the metal layer 38 is formed directly on the semiconductor layer 37. Therefore, the source layer 28 is electrically connected to the channel semiconductor layer 34 and the core semiconductor layer 36 of each pillar 27. The semiconductor layer 37 is, for example, a polysilicon layer. The metal layer 38 includes, for example, a W layer, a Cu layer, or an Al (aluminum) layer.

[0041] An insulating film 29 is formed on the source layer 28. The insulating film 29 is, for example, a SiO2 film.

[0042] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0043] Figure 2The diagram shows three electrode layers 31 and three insulating layers 32 contained within the multilayer film 26, as well as a columnar portion 27 disposed within the multilayer film 26. The memory insulating film 33 within the columnar portion 27, as described above, includes a barrier insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c sequentially formed on the sides of the multilayer film 26. The barrier insulating film 33a is, for example, a SiO2 film. The charge storage layer 33b is, for example, a SiN film. The tunnel insulating film 33c is, for example, a SiO2 film or a SiON film.

[0044] On the other hand, each electrode layer 31 includes a barrier metal layer 31a and an electrode material layer 31b. The barrier metal layer 31a is, for example, a TiN film (titanium nitride film). The electrode material layer 31b is, for example, a W layer. Figure 2 As shown, in this embodiment, each electrode layer 31 is formed on the lower surface of the upper insulating layer 32, the upper surface of the lower insulating layer 32, and the side surface of the barrier insulating film 33a, with the barrier insulating film 39 in between. The barrier insulating film 39 is, for example, an Al2O3 film (alumina film), and together with the barrier insulating film 33a, it functions as a barrier insulating film for each memory cell.

[0045] Figures 3 and 4 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. The semiconductor device of this embodiment is manufactured by bonding a circuit wafer W1 and an array wafer W2. The circuit wafer W1 is used to manufacture circuit region 1, and the array wafer W2 is used to manufacture array region 2.

[0046] First, prepare a substrate 41 for array wafer W2 (Fig. 3(a)). Substrate 41 is, for example, a semiconductor substrate such as a Si substrate. Substrate 41 is an example of a second substrate.

[0047] Next, a semiconductor layer 42 (Fig. 3(a)) is formed on the substrate 41. The semiconductor layer 42 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. In this embodiment, the semiconductor layer 42 contains a high concentration of impurity atoms. These impurity atoms are, for example, H (hydrogen) atoms. The H atom concentration in the semiconductor layer 42 of this embodiment is, for example, 1.0 × 10⁻⁶. 21 / cm 3 That's all. The impurity atom can also be an atom other than H, such as a rare gas atom like He (helium). Semiconductor layer 42 is an example of the first semiconductor layer within the second film.

[0048] Next, a dummy insulating film 43 is formed on the semiconductor layer 42 (Fig. 3(b)). The dummy insulating film 43 is, for example, a SiO2 film, formed by CVD (Chemical Vapor Deposition) or low-temperature free radical oxidation. In this embodiment, the dummy oxide film 43 is formed in contact with the semiconductor layer 42. The dummy insulating film 43 is an example of the first insulating film within the second film.

[0049] Next, a semiconductor layer 44 is formed on the dummy insulating film 43 (Fig. 3(c)). The semiconductor layer 44 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. The semiconductor layer 44 in this embodiment contains a high concentration of impurity atoms. These impurity atoms are, for example, H atoms. The H atom concentration in the semiconductor layer 44 in this embodiment is, for example, 1.0 × 10⁻⁶. 21 / cm 3 That's all. The impurity atom can also be an atom other than H, such as a rare gas atom like He. In this embodiment, the semiconductor layer 44 is formed in contact with the dummy insulating film 43. The semiconductor layer 44 is an example of a second semiconductor layer within a second film.

[0050] Next, a top cover insulating film 45 is formed on the semiconductor layer 44 (FIG. 3(c)). The top cover insulating film 45 includes an insulating film 45a formed on the semiconductor layer 44 and an insulating film 45b formed on the insulating film 45a. The insulating film 45a is, for example, a SiO2 film. The insulating film 45b is, for example, a SiN film. The top cover insulating film 45 is an example of a second insulating film. The insulating film 45a is an example of a third insulating film. The insulating film 45b is an example of a fourth insulating film.

[0051] Next, laser annealing is performed on the array wafer W2 (Fig. 4(a)). As a result, semiconductor layers 42 and 44 are heated and melted. The melting temperature of semiconductor layers 42 and 44 is, for example, 1300°C or higher. Then, semiconductor layers 42 and 44 crystallize, becoming semiconductor layers 42a and 44a respectively (Fig. 4(b)). Semiconductor layers 42a and 44a are, for example, porous semiconductor layers such as porous polycrystalline Si layers. In this embodiment, semiconductor layers 42 and 44 become porous polycrystalline Si layers that are both polycrystalline Si layers and porous layers (porous layers) by becoming porous during crystallization.

[0052] In this embodiment, laser annealing is performed, for example, using UV (ultraviolet) light. This allows semiconductor layers 42 and 44 to become semiconductor layers 42a and 44a, respectively. The intensity of the UV light is set, for example, to 0.3–2.0 J / cm². 2 Alternatively, the laser annealing in this embodiment can also be performed using lasers other than UV light, for example, light with wavelengths below the visible light wavelength can be used.

[0053] The porosity in this embodiment is achieved by the aggregation of impurity atoms within the semiconductor layers 42 and 44, forming numerous bubble-like pores (pores). If the top-cap insulating film 45 is not formed on the semiconductor layer 44, these pores could potentially increase the roughness of the upper surface of the semiconductor layer 44. According to this embodiment, by forming the top-cap insulating film 45 on the semiconductor layer 44 and then performing laser annealing, the increase in roughness of the upper surface of the semiconductor layer 44 can be suppressed. Since the melting point of the SiN film is higher than that of the SiO2 film, the insulating film 45b (SiN film) can effectively suppress the increase in roughness caused by pores. On the other hand, the insulating film 45a (SiO2 film) is effective in adjusting the reflectivity of the laser. Therefore, the top-cap insulating film 45 in this embodiment includes both insulating film 45a and insulating film 45b. If adjusting the reflectivity of the laser is not required, the top-cap insulating film 45 may also include only insulating film 45b.

[0054] The porosity of semiconductor layers 42 and 44 can also be considered through wet processing, such as anodizing. However, wet processing cannot be performed after the top cap insulating film 45 is formed on semiconductor layer 44, and there is a risk of not being able to suppress the increase in roughness. Therefore, the porosity of semiconductor layers 42 and 44 is ideally achieved through laser annealing.

[0055] In this embodiment, both semiconductor layers 42 and 44 are made porous; however, alternatively, only one of semiconductor layers 42 and 44 may be made porous. For example, only semiconductor layer 44 may be made porous by sufficiently heating only semiconductor layer 44. Furthermore, the laser annealing in this embodiment is performed to make the entire semiconductor layer 42 porous; alternatively, only a portion of semiconductor layer 42 may be made porous. Similarly, the laser annealing in this embodiment is performed to make the entire semiconductor layer 44 porous; alternatively, only a portion of semiconductor layer 44 may be made porous. Therefore, in the steps shown in FIG. 4(b), semiconductor layers 42 and 44 may be completely melted, or only a portion of semiconductor layers 42 and 44 may be melted.

[0056] Next, an insulating film 46, a laminated film 26, and an interlayer insulating film 21 are sequentially formed on the top cover insulating film 45 (Fig. 4(c)). The insulating film 46 is, for example, a SiO2 film. Details of the laminated film 26 and the interlayer insulating film 21 are referred to above. Figure 1 The above is described in Figure 4(c). Figure 4(c) schematically shows the structure of the laminated film 26 and the interlayer insulating film 21. The steps shown in Figure 4(c) or subsequent steps are described below with reference to Figures 5 to 9.

[0057] Figures 5 to 9 are cross-sectional views showing the detailed process of manufacturing the semiconductor device according to the first embodiment.

[0058] Figures 5(a) to 6(b) The details of the steps shown in Figure 4(c) are illustrated below. First, an insulating film 46 is formed on the top cover insulating film 45, and a laminated film 26' is formed on the insulating film 46 (Figure 5(a)). The laminated film 26' is a film used to form the laminated film 26 through a replacement process. The laminated film 26' is formed in a manner that alternately includes multiple sacrificial layers 31' and multiple insulating layers 32. The sacrificial layer 31' is, for example, a SiN film.

[0059] Next, multiple memory holes H1 are formed that penetrate the stacked film 26' and the insulating film 46. Within each memory hole H1, a memory insulating film 33, a channel semiconductor layer 34, and a core insulating film 35 are sequentially formed (Fig. 5(a)). As a result, multiple columnar portions 27 extending in the Z direction are formed within these memory holes H1. The memory insulating film 33 is formed by sequentially forming a barrier insulating film 33a, a charge accumulation layer 33b, and a tunnel insulating film 33c within each memory hole H1 (see reference). Figure 2 ).

[0060] Next, an insulating film 47 is formed on the laminated film 26' and the columnar portion 27 (Fig. 5(a)). The insulating film 47 is, for example, a SiO2 film.

[0061] Next, a slit (not shown) is formed through the insulating film 47 and the stacked film 26', and the sacrificial layer 31' is removed by wet etching using the slit (Fig. 5(b)). As a result, multiple cavities H2 are formed between the insulating layers 32 within the stacked film 26'.

[0062] Next, multiple electrode layers 31 are formed within these cavities H2 through slits (Fig. 6(a)). As a result, a multilayer film 26, alternately containing multiple electrode layers 31 and multiple insulating layers 32, is formed between insulating films 46 and 47 (replacement process). Furthermore, a structure in which multiple columnar portions 27 penetrate the multilayer film 26 is formed above the substrate 41. In addition, when forming the electrode layer 31 in each cavity H2, a barrier insulating film 39, a barrier metal layer 31a, and an electrode material layer 31b are sequentially formed in each cavity H2 (see reference). Figure 2 ).

[0063] Next, the insulating film 47 is removed, and a portion of the core insulating film 35 within each columnar portion 27 is removed. A core semiconductor layer 36 is then embedded in the area where a portion of the core insulating film 35 has been removed (Fig. 6(b)). As a result, each columnar portion 27 is fabricated to include a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36.

[0064] Next, an interlayer insulating film 21, metal pads 22, via plugs 23, a wiring layer 24, and a plurality of contact plugs 25 are formed on the multilayer film 26 and the columnar portion 27 (Fig. 6(b)). At this time, these contact plugs 25 are formed on the core semiconductor layer 36 of their respective columnar portions 27, and the wiring layer 24, via plugs 23, and metal pads 22 are sequentially formed on these contact plugs 25. Furthermore, Fig. 6(b) shows the same state as shown in Fig. 4(b).

[0065] Figure 7(a) illustrates the steps of bonding the circuit wafer W1 to the array wafer W2 (bonding steps). The circuit wafer W1 shown in Figure 7(a) is manufactured by preparing a substrate 11 and forming transistors 12, interlayer insulating films 13, multiple contact plugs 14, wiring layers 15, through-hole plugs 16, and metal pads 17 (see reference) on the substrate 11. Figure 1 At this time, transistor 12 is formed on substrate 11, and contact plugs 14 are formed on substrate 11 or transistor 12. Furthermore, wiring layer 15, via plugs 16, and metal pads 17 are sequentially formed on these contact plugs 14.

[0066] Next, the orientation of the array wafer W2 is flipped, and the circuit wafer W1 and the array wafer W2 are bonded together by mechanical pressure (Fig. 7(a)). As a result, the interlayer insulating film 13 and the interlayer insulating film 21 are bonded. Next, the circuit wafer W1 and the array wafer W2 are annealed (Fig. 7(a)). As a result, the metal pads 17 and 22 are bonded. In this way, the substrate 11 and the substrate 41 are bonded together with the interlayer insulating films 13 and 21, the stacked film 26, the insulating film 46, the top cover insulating film 45, the semiconductor layer 44a, the dummy insulating film 43, and the semiconductor layer 42a sandwiched between them, and the substrate 41 is stacked on top of the substrate 11.

[0067] Next, the array wafer W2 is irradiated with a laser (Fig. 7(b)). This laser may contain, for example, infrared light. In the step shown in Fig. 7(b), the dummy insulating film 43, which is irradiated by the laser, heats up (melts), and this heat applies stress to the semiconductor layers 42a and 44a. As a result, the semiconductor layer 42a, the dummy insulating film 43, or the semiconductor layer 44a breaks. Thus, the substrate 11 can be separated from the substrate 41 (Fig. 8(a)). In Fig. 8(a), the semiconductor layer 42a breaks, and therefore the substrate 11 separates from the substrate 41 at the location of the semiconductor layer 42a. As a result, a portion of the semiconductor layer 42a remains on the surface of the substrate 41, and the remaining portion of the semiconductor layer 42a remains on the surface of the substrate 11. Furthermore, the memory cell array or CMOS circuit also remains on the surface of the substrate 11.

[0068] Ideally, the heat generated by the dummy insulating film 43 should be easily transferred to the semiconductor layers 42a and 44a. Therefore, it is ideal for the semiconductor layers 42a and 44a to be in contact with the dummy insulating film 43. In this embodiment, stress can be applied to the semiconductor layers 42a and 44a by transferring heat from the dummy insulating film 43 to the semiconductor layers 42a and 44a.

[0069] The semiconductor layers 42a and 44a in this embodiment are porous semiconductor layers containing a large number of pores, making them prone to breakage. Therefore, by applying stress to the semiconductor layers 42a and 44a, it is possible to cause the semiconductor layers 42a or 44a to break. Generally, the higher the concentration of impurity atoms in the semiconductor layers 42a and 44a, the more pores are generated in the semiconductor layers 42a and 44a, and the more easily the semiconductor layers 42a and 44a are to break. Therefore, it is ideal to set the concentration of impurity atoms in the semiconductor layers 42a and 44a to be relatively high, ideally, for example, 1.0 × 10⁻⁶. 21 / cm 3 As described above, the impurity atom is, for example, a H atom or a rare gas atom (e.g., a He atom). Alternatively, substrate 11 and substrate 41 can be separated not by breaking semiconductor layers 42a and 44a, but by breaking the dummy insulating film 43. In this embodiment, semiconductor layer 42a, dummy insulating film 43, and semiconductor layer 44a function as separation layers (peel-off layers) for separating (stripping) substrate 41 from substrate 11.

[0070] The heat generated by the dummy insulating film 43 is generally transferred to both the upper and lower surfaces of the dummy insulating film 43. Therefore, the array wafer W2 shown in FIG8(a) has a semiconductor layer 42a on the upper surface of the dummy insulating film 43 and a semiconductor layer 44a on the lower surface of the dummy insulating film 43. This allows for efficient utilization of the heat generated by the dummy insulating film 43. On the other hand, the array wafer W2 of this embodiment may also have only one of the semiconductor layers 42a and 44a.

[0071] In this embodiment, instead of shaving off the substrate 41, the substrate 41 above the substrate 11 is removed by peeling the substrate 41 off from the substrate 11. This suppresses damage to the substrate 41 and allows for its reuse. In this embodiment, after separating the substrate 11 from the substrate 41, any remaining semiconductor layer 42a or the like on the surface of the substrate 41 is removed, and the substrate 41 is reused in the bonding step shown in FIG. 7(a). This avoids the waste caused by using multiple substrates 41.

[0072] Next, the semiconductor layer 42a, the dummy insulating film 43, the semiconductor layer 44a, and the top cover insulating film 45 above the substrate 11 are removed (Fig. 8(b)). As a result, the insulating film 46 or each columnar portion 27 is exposed above the substrate 11. The steps shown in Fig. 8(b) are performed, for example, using CMP (Chemical Mechanical Polishing) or etching. In the steps of Fig. 8(b), the substrate 11 can also be further thinned using CMP or etching.

[0073] Next, a portion of the memory insulating film 33 of the insulating film 46 or each pillar 27 is removed by etching (FIG. 9(a)). The portion of the memory insulating film 33 that is removed is, for example, the portion exposed from the stacked film 26. As a result, a portion of the channel semiconductor layer 34 of each pillar 27 is exposed from the memory insulating film 33 at a position higher than the stacked film 26.

[0074] Next, a semiconductor layer 37, a metal layer 38, and an insulating film 29 are sequentially formed on the stacked film 26 and the columnar portion 27 (Fig. 9(b)). As a result, a source layer 28 is formed on the channel semiconductor layer 34 of each columnar portion 27 and is electrically connected to the channel semiconductor layer 34 of each columnar portion 27.

[0075] Then, the circuit wafer W1 and the array wafer W2 are diced into multiple chips. These chips are diced such that each chip contains both circuit region 1 and array region 2. This process is repeated to manufacture the chips. Figure 1 Semiconductor devices.

[0076] Furthermore, the semiconductor device in this embodiment can... Figure 1 It can be sold in the state shown in Figure 7(a), or it can be sold in the state shown in Figure 7(a). In the latter case, it is implemented by the purchaser of the semiconductor device. Figures 7(b) to 9(b) The steps shown or subsequent steps.

[0077] Figure 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0078] Figure 10(a) shows the steps corresponding to those shown in Figure 7(b). In this variation, instead of irradiating the array wafer W2 with a laser, a force F is applied to the array wafer W2 using a scraper or water jet (Figure 10(a)). Specifically, the force F is applied to the cross-section of the semiconductor layer 42a, the dummy insulating film 43, or the semiconductor layer 44a. As a result, the semiconductor layer 42a, the dummy insulating film 43, or the semiconductor layer 44a breaks. Thus, the substrate 11 can be separated from the substrate 41 (Figure 10(b)). In Figures 10(a) and 10(b), because the semiconductor layer 42a breaks due to the force F applied to its cross-section, the substrate 11 and the substrate 41 separate at the position of the semiconductor layer 42a. As a result, a portion of the semiconductor layer 42a remains on the surface of the substrate 41, and the remaining portion of the semiconductor layer 42a remains on the surface of the substrate 11. Furthermore, the memory cell array or CMOS circuit also remains on the surface of the substrate 11.

[0079] In this variation, the other steps can be performed in the same way as in the first embodiment. As a result, a product is manufactured. Figure 1 The semiconductor device. Additionally, the array wafer W2 of this variation may not have the dummy insulating film 43. In this case, the array wafer W2 of this variation may also not have one of the semiconductor layers 42a and 44a. Furthermore, the force F can be applied mechanically like a scraper, fluidly like a water jet, or in other forms.

[0080] Figure 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another variation of the first embodiment.

[0081] Figure 11(a) shows the steps corresponding to those shown in Figure 4(c). In the variation shown in Figure 11(a), the array wafer W2 has a semiconductor layer 51 instead of semiconductor layer 42a. Semiconductor layer 51 is, for example, an amorphous Si layer or a polycrystalline Si layer other than a porous Si layer. Therefore, in the steps shown in Figure 8(a) or Figure 10(b), semiconductor layer 42a is more prone to cracking than semiconductor layer 51.

[0082] Figure 11(b) also shows the steps corresponding to those shown in Figure 4(c). In the variation shown in Figure 11(b), the array wafer W2 has a semiconductor layer 52 instead of semiconductor layer 44a. Semiconductor layer 52 is, for example, an amorphous Si layer or a polycrystalline Si layer other than a porous Si layer. Therefore, in the steps shown in Figure 8(a) or Figure 10(b), semiconductor layer 44a is more prone to cracking than semiconductor layer 52.

[0083] Figure 11(c) also shows the steps corresponding to those shown in Figure 4(c). In the variation shown in Figure 11(c), the array wafer W2 does not have the dummy insulating film 43 and the semiconductor layer 44a. In this variation, by applying a force F to the semiconductor layer 42a, the steps shown in Figures 10(a) and 10(b) can be performed. On the other hand, in this variation, the steps shown in Figures 7(b) and 8(a) can also be performed by heating the insulating film 45a instead of heating the dummy insulating film 43.

[0084] Figures 3(a) to 9(b) The method of the first embodiment shown can also be performed by replacing the steps shown in FIG4(c) with the steps shown in FIG11(a), FIG11(b), or FIG11(c). The same applies to the methods in the variations shown in FIG10(a) and FIG10(b).

[0085] Figure 12 This is a cross-sectional view showing the structure of a semiconductor device according to another variation of the first embodiment. (See reference) Figures 1 to 11(c) The semiconductor device described may also not have Figure 1 The structure shown has Figure 12 The structure shown.

[0086] The semiconductor device in this variation, like the semiconductor device of the first embodiment, includes a circuit region 1 and an array region 2. The circuit region 1, except... Figure 1 In addition to the components shown, the array region 2 also includes wiring layers 15' and 15' that electrically connect wiring layer 15 to through-hole plug 16. Figure 1 In addition to the components shown, there is also a wiring layer 24' that electrically connects the through-hole plug 23 to the wiring layer 24. Wiring layers 15', 15" and 24' each contain a plurality of wires in the same manner as wiring layer 15 or wiring layer 24.

[0087] Figure 12 The diagram shows multiple word lines WL (electrode layers 31) within the stacked film 26, multiple columnar portions 27 penetrating the stacked film 26, and a stepped structure portion 61 of the stacked film 26. Each word line WL is electrically connected to the word wiring layer 63 via a contact plug 62 at the stepped structure portion 61. Each columnar portion 27 is electrically connected to the bit line BL via a contact plug 25 and is also electrically connected to the source layer 28. In this variation, the word wiring layer 63 and the bit line BL are contained within the wiring layer 24.

[0088] The array region 2 also includes a plurality of through-hole plugs 71 disposed on the wiring layer 24, metal pads 72 disposed on these through-hole plugs 71 or the insulating film 29, and a passivation film 73 disposed on the metal pads 72 or the insulating film 29. The passivation film 73 is, for example, a multilayer insulating film comprising a silicon oxide film or a silicon nitride film, and has an opening P that exposes the upper surface of the metal pads 72. The metal pads 72 are external connection pads of the semiconductor device of this variation, and can be connected to the mounting substrate or other devices via solder balls, metal bumps, bonding wires, etc.

[0089] As described above, the semiconductor device of this embodiment is manufactured by bonding substrate 11 and substrate 41 together with semiconductor layer 42a, dummy insulating film 43, and semiconductor layer 44a sandwiched between them, and then separating substrate 11 and substrate 41 at the locations of semiconductor layer 42a, dummy insulating film 43, or semiconductor layer 44a. Therefore, according to this embodiment, these substrates 11 and 41 can be appropriately separated after bonding, for example, substrate 41 separated from substrate 11 can be reused. This appropriate separation can be achieved, for example, by perforating semiconductor layers 42a and 44a using laser annealing, or by separating these substrates 11 and 41 using laser irradiation.

[0090] (Second Embodiment) Figures 13 and 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. In this embodiment, the manufacturing process is carried out... Figures 13(a) to 14(c) The steps shown are in lieu of those in the first embodiment. Figures 3(a) to 4(c) The steps are shown. In the following description, matters common to the first embodiment are appropriately omitted.

[0091] First, a substrate 41 is prepared, and a semiconductor layer 42 is formed on the substrate 41 (Fig. 13(a)). The semiconductor layer 42 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. However, in this embodiment, the semiconductor layer 42 does not need to contain impurity atoms such as H atoms or rare gas atoms at this point in time.

[0092] Next, a dummy insulating film 43 is formed on the semiconductor layer 42 (Fig. 13(b)), and a semiconductor layer 44 is formed on the dummy insulating film 43 (Fig. 13(c)). The semiconductor layer 44 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. However, in this embodiment, the semiconductor layer 44 does not need to contain impurity atoms such as H atoms or rare gas atoms at this point in time.

[0093] Next, plasma doping is performed on semiconductor layers 44 and 42 (Fig. 13(c)). This implants impurity atoms into semiconductor layers 44 and 42. These impurity atoms are, for example, H atoms. In this embodiment, plasma doping is performed with high concentrations of H atoms in semiconductor layer 44 and semiconductor layer 42, for example, 1.0 × 10⁻⁶.21 / cm 3 The above method is used. The impurity atom can also be an atom other than H, such as a noble gas atom like He.

[0094] Next, a top cover insulating film 45 is formed on the semiconductor layer 44 (FIG. 14(a)). The top cover insulating film 45 includes an insulating film 45a formed on the semiconductor layer 44 and an insulating film 45b formed on the insulating film 45a.

[0095] Next, the array wafer W2 undergoes RTA (Rapid Thermal Annealing) (Fig. 14(a)). As a result, semiconductor layers 42 and 44 are heated and melted. Then, semiconductor layers 42 and 44 crystallize, becoming semiconductor layers 42a and 44a, respectively (Fig. 14(b)). The semiconductor layers 42a and 44a in this embodiment are, for example, porous semiconductor layers such as porous polycrystalline Si layers, similar to those in the first embodiment. The semiconductor layers 42 and 44 in this embodiment are also porous polycrystalline Si layers that are both polycrystalline Si layers and porous layers, by becoming porous during crystallization. Alternatively, the array wafer W2 can also be annealed using methods other than RTA.

[0096] The porosity in this embodiment is also achieved by the aggregation of impurity atoms within semiconductor layers 42 and 44, forming numerous bubble-like pores. Specifically, when semiconductor layers 42 and 44 are porosified using plasma doping and RTA, large pores are easily generated. Figure 14(b) shows the large pore V generated within semiconductor layer 44.

[0097] In this embodiment, the concentration of impurity atoms in semiconductor layer 44 is easily increased, but the concentration of impurity atoms in semiconductor layer 42 is difficult to increase. This is because the impurity atoms injected into semiconductor layer 42 reach semiconductor layer 42 through semiconductor layer 44 and the dummy insulating film 43. Therefore, the concentration of impurity atoms in semiconductor layer 42 may become less than 1.0 × 10⁻⁶. 21 / cm 3 Furthermore, in order to achieve a concentration of impurity atoms of 1.0 × 10⁻⁶ within the semiconductor layer 42... 21 / cm 3 The above may require the concentration of impurity atoms within semiconductor layer 44 to be significantly higher than 1.0 × 10⁻⁶. 21 / cm 3 In Figure 14(b), the concentration of impurity atoms in semiconductor layer 42 is lower than that in semiconductor layer 44, thus large pores V are only generated in semiconductor layer 44. Furthermore, the method for addressing this problem will be described below.

[0098] Next, an insulating film 46, a laminated film 26, and an interlayer insulating film 21 are sequentially formed on the top cover insulating film 45 (Fig. 14(c)). Then, by performing... Figures 5(a) to 9(b) The steps shown are for manufacturing Figure 1 Semiconductor devices. At this time, it is also possible to use... Figures 10(a) to 11(c) The method shown in the variation example can also be used. Figure 12 The construction of the variation example shown.

[0099] Figures 15 and 16 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a variation of the second embodiment. In this variation, the manufacturing process is as follows: Figures 15(a) to 16(c) The steps shown are in lieu of those in the second embodiment. Figures 13(a) to 14(c) The steps are shown. In the following description, matters common to the second embodiment are appropriately omitted.

[0100] First, a substrate 41 is prepared, and a semiconductor layer 42 is formed on the substrate 41 (Fig. 15(a)). The semiconductor layer 42 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. However, in this variation, the semiconductor layer 42 does not need to contain impurity atoms such as H atoms or rare gas atoms at this point in time.

[0101] Next, the semiconductor layer 42 is plasma-doped (Fig. 15(a)). This implants impurity atoms into the semiconductor layer 42. These impurity atoms are, for example, H atoms. The plasma doping is performed in such a way that the H atom concentration within the semiconductor layer 42 becomes high, for example, 1.0 × 10⁻⁶. 21 / cm 3 The above method is used. The impurity atom can also be an atom other than H, such as a noble gas atom like He.

[0102] Next, a dummy insulating film 43 is formed on the semiconductor layer 42 (Fig. 15(b)), and a semiconductor layer 44 is formed on the dummy insulating film 43 (Fig. 15(c)). The semiconductor layer 44 is, for example, an amorphous semiconductor layer such as an amorphous Si layer. However, in this variation, the semiconductor layer 44 does not need to contain impurity atoms such as H atoms or rare gas atoms at this time point.

[0103] Next, the semiconductor layer 44 is subjected to plasma doping (Fig. 15(c)). This implants impurity atoms into the semiconductor layer 44. These impurity atoms are, for example, H atoms. The plasma doping is performed in such a way that the H atom concentration within the semiconductor layer 44 is high, for example, to 1.0 × 10⁻⁶. 21 / cm 3 The above method is used. The impurity atom can also be an atom other than H, such as a noble gas atom like He.

[0104] Alternatively, the plasma doping step shown in Figure 15(c) can also be performed by implanting impurity atoms into semiconductor layers 44 and 42. In this case, the H atom concentration in semiconductor layer 42 can be less than 1.0 × 10⁻⁶ before plasma doping. 21 / cm 3 After plasma doping, it becomes 1.0 × 10⁻⁶. 21 / cm 3 above.

[0105] Next, a top cover insulating film 45 is formed on the semiconductor layer 44 (FIG. 16(a)). The top cover insulating film 45 includes an insulating film 45a formed on the semiconductor layer 44 and an insulating film 45b formed on the insulating film 45a.

[0106] Next, RTA (Regenerative Thermal Acrylamide) is performed on the array wafer W2 (Fig. 16(a)). As a result, semiconductor layers 42 and 44 are heated and melted. Then, semiconductor layers 42 and 44 are crystallized, becoming semiconductor layers 42a and 44a, respectively (Fig. 16(b)). In this variation, semiconductor layers 42a and 44a are, for example, porous semiconductor layers such as porous polycrystalline Si layers, similar to those in the first and second embodiments. In this variation, semiconductor layers 42 and 44 are also porous polycrystalline Si layers that are both polycrystalline Si layers and porous layers, by becoming porous during crystallization. Alternatively, the array wafer W2 can also be annealed using methods other than RTA.

[0107] The porosity in this variation is also achieved by the aggregation of impurity atoms within semiconductor layers 42 and 44, forming numerous bubble-like pores. Specifically, when semiconductor layers 42 and 44 are porosified using plasma doping and RTA, large pores are easily generated. Figure 16(b) shows the large pores V generated within semiconductor layers 42 and 44. In Figure 16(b), the concentration of impurity atoms within semiconductor layers 42 and 44 is high, thus resulting in large pores V within semiconductor layers 42 and 44.

[0108] Next, an insulating film 46, a laminated film 26, and an interlayer insulating film 21 are sequentially formed on the top cover insulating film 45 (Fig. 16(c)). Then, by performing... Figures 5(a) to 9(b) The steps shown are for manufacturing Figure 1 Semiconductor devices. At this time, it is also possible to use... Figures 10(a) to 11(c) The method shown in the variation example can also be used. Figure 12 The construction of the variation example shown.

[0109] As described above, the semiconductor device of this embodiment is manufactured by bonding substrate 11 and substrate 41 together with semiconductor layer 42a, dummy insulating film 43, and semiconductor layer 44a sandwiched between them, and then separating substrate 11 and substrate 41 at the locations of semiconductor layer 42a, dummy insulating film 43, or semiconductor layer 44a. Therefore, according to this embodiment, these substrates 11 and 41 can be appropriately separated after bonding, for example, substrate 41 separated from substrate 11 can be reused. Such appropriate separation can be achieved, for example, by porousification of semiconductor layers 42a and 44a using plasma doping and RTA, or by separating these substrates 11 and 41 using laser irradiation, etc.

[0110] The foregoing has described several embodiments, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass such embodiments or variations as included in the scope or spirit of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: On the first substrate, a first film containing the first element is formed; On a second substrate, a second film comprising a first semiconductor layer, a first insulating film, and a second semiconductor layer is formed. The first semiconductor layer contains hydrogen atoms or rare gas atoms. The first insulating film is formed on the first semiconductor layer. The second semiconductor layer is formed on the first insulating film and contains hydrogen atoms or rare gas atoms. On the second film, a second insulating film comprising a third insulating film and a fourth insulating film is formed, wherein the third insulating film comprises silicon atoms and oxygen atoms, and the fourth insulating film comprises silicon atoms and nitrogen atoms; At least one of the first and second semiconductor layers, which are amorphous layers, is transformed into a porous layer by laser annealing; After the change to the porous layer, a third film containing the second element is formed on the second insulating film; The first substrate and the second substrate are bonded together in such a way that the first film, the third film and the second film are sandwiched between them; as well as By irradiating the first insulating film with a laser, the first substrate and the second substrate are separated at the location of the second film.

2. A method for manufacturing a semiconductor device, comprising the following steps: On the first substrate, a first film containing the first element is formed; On a second substrate, a second film comprising a first semiconductor layer, a first insulating film, and a second semiconductor layer is formed. The first semiconductor layer contains hydrogen atoms or rare gas atoms. The first insulating film is formed on the first semiconductor layer. The second semiconductor layer is formed on the first insulating film and contains hydrogen atoms or rare gas atoms. Plasma doping is performed on at least one of the first and second semiconductor layers by implanting impurity atoms containing hydrogen atoms or rare gas atoms. At least one of the first and second semiconductor layers, which are amorphous layers, is transformed into a porous layer by rapid high-temperature annealing; After the change to the porous layer, a third film containing the second element is formed on the second film; The first substrate and the second substrate are bonded together in such a way that the first film, the third film and the second film are sandwiched between them; as well as By irradiating the first insulating film with a laser, the first substrate and the second substrate are separated at the location of the second film.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the concentration of hydrogen atoms or rare gas atoms in at least one of the first and second semiconductor layers is 1.0 × 10⁻⁶. 21 / cm 3 above.

4. The method of manufacturing a semiconductor device according to claim 2, wherein the third film is formed on the second film through a second insulating film.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the second insulating film comprises a third insulating film containing silicon atoms and oxygen atoms, and a fourth insulating film containing silicon atoms and nitrogen atoms.

6. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein at least one of the first and second semiconductor layers is in contact with the first insulating film.

7. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the laser irradiating the first insulating film comprises infrared light.

8. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein one of the first and second elements comprises a memory cell array, and the other of the first and second elements comprises circuitry for controlling the memory cell array.

9. The method of manufacturing a semiconductor device according to claim 1 or 2, further comprising the step of: reusing the second substrate separated from the first substrate.

10. A method for reusing a substrate, comprising the following steps: Prepare the first substrate and the second substrate; On the second substrate, a second film comprising a first semiconductor layer, a first insulating film, and a second semiconductor layer is formed. The first semiconductor layer contains hydrogen atoms or rare gas atoms. The first insulating film is formed on the first semiconductor layer. The second semiconductor layer is formed on the first insulating film and contains hydrogen atoms or rare gas atoms. On the second film, a second insulating film comprising a third insulating film and a fourth insulating film is formed, wherein the third insulating film comprises silicon atoms and oxygen atoms, and the fourth insulating film comprises silicon atoms and nitrogen atoms; At least one of the first and second semiconductor layers, which are amorphous layers, is transformed into a porous layer by laser annealing; After the change to the porous layer, the first substrate and the second substrate are bonded together in a manner that sandwiches the second film; By irradiating the first insulating film with a laser, the first substrate and the second substrate are separated at the location of the second film; as well as The second substrate, which is separated from the first substrate, is then reused.

11. A semiconductor device comprising: The first film is disposed on the first substrate and contains the first element; A third membrane is disposed on the first membrane and includes the second element; A second insulating film, comprising a fourth insulating film containing silicon atoms and nitrogen atoms, and a third insulating film containing silicon atoms and oxygen atoms, is disposed on the third film; A second film includes a second semiconductor layer, a first insulating film, and a first semiconductor layer. The second semiconductor layer is disposed on the second insulating film, the first insulating film is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulating film. At least one of the first and second semiconductor layers is a porous layer, and at least one of the first and second semiconductor layers is in contact with the first insulating film. The second substrate is disposed on the second film.

12. The semiconductor device of claim 11, wherein at least one of the first and second semiconductor layers comprises hydrogen atoms or rare gas atoms.

13. The semiconductor device of claim 12, wherein the concentration of hydrogen atoms or rare gas atoms in the semiconductor layer is 1.0 × 10⁻⁶. 21 / cm 3 above.

14. The semiconductor device according to any one of claims 11 to 13, wherein the second film is disposed on the third film through a second insulating film.

15. The semiconductor device according to any one of claims 11 to 13, wherein the first element comprises circuitry for controlling the memory cell array, and the second element comprises the memory cell array.

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