An integrated circuit including standard cells and at least one capacitive fill structure.

Abstract

Embodiments of this disclosure relate to an integrated circuit including standard cells and at least one capacitive fill structure. An integrated circuit includes a logic portion comprising standard cells arranged in parallel rows along a first direction with alternating complementary semiconductor wells. In each standard cell, at least one capacitive fill structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and a first well. The second well's extent in the first direction is interrupted above the length of the capacitive fill structure, such that the first well occupies the width of two adjacent rows of the capacitive fill structure in a second direction. A conductive structure electrically connects to the second well on either side of the capacitive fill structure.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2109789, filed on September 17, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The implementation methods and embodiments relate to integrated circuits, and more particularly to the logic portion of an integrated circuit that includes standard cells and capacitive fill structures. Background Technology

[0004] Typically, standard cells are the "building blocks" of the logic section of an integrated circuit. Standard cells are pre-designed and characterized to have basic logic functions, such as "NOT", "AND", "OR", and "XOR", which can be combined with each other in a fully compatible manner to design complex logic mechanisms.

[0005] Physically, combinations of standard cells are typically arranged in rows within a logic section, with these rows having a fixed width corresponding to the width applied to each standard cell. Each row of the logic section can contain multiple standard cells over its length, and the length of each standard cell can vary depending on the basic logical function of the cell.

[0006] Basic logic functions are typically implemented using complementary metal-oxide-semiconductor (CMOS) technology, including “NMOS”, which uses an n-channel MOS transistor in a p-type semiconductor well, and “PMOS”, which uses a p-channel MOS transistor in an n-type semiconductor well.

[0007] Furthermore, logic components can advantageously include capacitive structures known as “fillers” because they are formed in spaces that could accommodate standard cells but leave blank spaces in the rows of logic components due to the nature of the design of complex logic mechanisms. Thus, capacitive filler structures allow for the use of available space in the logic section of an integrated circuit and thereby reduce the surface footprint of capacitive elements (typically capacitive elements in resistor-capacitor (RC) filters that reduce supply voltage variations).

[0008] To further limit the surface footprint of capacitor elements, it is advantageous to increase the capacitance per unit surface area of ​​the capacitive fill structure. In this regard, implementations of capacitor elements based on a "metal-oxide-semiconductor" (MOS) type capacitive structure architecture have been proposed, wherein the conductive armature includes trenches filled with conductive material that extend vertically in depth within the complementary well and longitudinally in the surface direction of the logic component.

[0009] In other words, the capacitance value of this type of capacitive structure is limited by the composition of complementary wells in CMOS-type standard cells.

[0010] In fact, on the one hand, in order to operate in depletion mode, the well containing the capacitive structure (usually N-type) is polarized to a non-zero voltage, typically the supply voltage. Therefore, well taps are provided and occupy a surface that contributes only slightly to the capacitive effect.

[0011] Furthermore, when this type of MOS capacitive structure is suitable for operation in NOT mode, typically in a p-type well, the longitudinal end of the trench must be separated from the adjacent well of the opposite type (usually an adjacent N-type well) by a non-negligible distance to prevent current from flowing through the conducting transistor effect. Here, the separation distance again occupies the surface that does not contribute to the capacitive effect. Summary of the Invention

[0012] The implementations and embodiments defined below propose introducing discontinuities in the arrangement of complementary wells in the logic portions of the capacitively filled structure to allow for the elimination of the aforementioned problems while increasing the capacitance per unit surface area. Furthermore, the implementations and embodiments do not introduce constraints on the combination possibilities and compatibility of standard cells, and are particularly compatible with non-well tap techniques.

[0013] According to one aspect, an integrated circuit is proposed, comprising a logic portion including standard cells arranged in parallel rows along a first direction, and the logic portion having a fixed width that covers half the width of a first semiconductor well having a first type of doping (e.g., P-type) and half the width of a second semiconductor well having a second type of doping (e.g., N-type) opposite to the first type in a second direction perpendicular to the first direction, each well being shared by two adjacent rows. In the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted above the length of the capacitive filling structure such that the first well occupies the width of two rows of the capacitive filling structure in the second direction, the capacitive filling structure further including a conductive structure adapted to electrically connect the second well on either side of the capacitive filling structure in the first direction.

[0014] Therefore, the capacitive interface formed by the conductive armature and the first well can be significantly enlarged because the first well occupies the entire width of the capacitive filling structure due to the absence of a second well. This effect of enlarging the capacitive interface is also achieved when the conductive armature does not include a trench filled with conductive material, which extends vertically in depth within the first well.

[0015] This further allows for the elimination of the requirement for a separation distance between the capacitive structure and the second well, as well as the need for well taps.

[0016] Furthermore, the electrical continuity of the second well is ensured by the conductive structure, although its range is interrupted; that is, there is no second well above the length of the capacitively filled structure.

[0017] According to one embodiment, the conductive structure includes at least one metal track located in a metal layer and extending in a first direction opposite to the length of the capacitive fill structure, and the capacitive interface extending in a second direction over the entire width of the two rows of the capacitive fill structure.

[0018] This advantageously allows the entire width of the two rows of capacitive fill structures to be dedicated, and further ensures electrical continuity between the second well and the conductive structure, which allows for a reduction in the number of well taps (typically regularly arranged within the well), and the conductive structure has a lower resistance than the second well.

[0019] According to one embodiment, the conductive structure includes a strongly doped surface semiconductor strip of a second type, the surface semiconductor strip being located in a first well and extending in a first direction over the length of the capacitive filling structure, the capacitive interface extending in the second direction over the entire width of the two rows of capacitive filling structures excluding the width of the surface semiconductor strip.

[0020] Therefore, the quasi-total width range of the two rows, for example, greater than 60% or even greater than 80%, is dedicated to capacitive filling structures, and here, the conductive structure can have a lower resistance than the resistance of the second well, thereby allowing a reduction in the number of well taps to be provided.

[0021] For example, the surface semiconductor strip includes metal silicide.

[0022] For example, the conductive structure includes a shallow insulating trench on either side of the surface semiconductor strip in a second direction.

[0023] For example, the surface semiconductor strip includes a second type of dopant material implanted in the first well, with a density of 1 x 10⁻⁶ per cubic centimeter. 15 One atom and 1 x 10^12 atoms per cubic centimeter 16 Between atoms.

[0024] According to one embodiment, the conductive armature of the capacitive fill structure includes at least one vertical gate structure that extends in depth within the first well.

[0025] According to one embodiment, the at least one vertical gate structure includes a region where a second type of doping is implanted at the vertical end of a vertical gate located at the depth of a first well, and a region where a second type of doping is implanted at the vertical end of a vertical gate structure located on the surface of a first well.

[0026] The doped region implanted at the vertical end of the vertical gate structure can be applied through the fabrication of the vertical gate, but advantageously allows operation in NOT mode, which is generally more stable in terms of voltage variations in capacitance value.

[0027] Furthermore, in particular, this implementation does not experience the problem of current flow between the doped region and adjacent wells polarized to different voltages via the on-transistor effect (forming a conductive channel).

[0028] According to one embodiment, the conductive armature of the capacitive fill structure further includes at least one horizontal gate structure, the at least one vertical gate structure being located on the surface of the first well facing the at least one vertical gate structure.

[0029] According to one implementation, the integrated circuit further includes a non-volatile memory comprising memory cells, each memory cell being provided with a vertical gate buried access transistor and a floating gate state transistor, and the vertical gate structure of the conductive armature being composed of the same material and having the same depth as the vertical gate of the buried access transistor of the memory cell.

[0030] This implementation of integrated circuits advantageously allows for the fabrication of shared non-volatile memory cells and capacitive fill structures, and in particular, that is, in practice, the capacitive fill mechanism can be fabricated without additional cost.

[0031] According to another aspect, a method for manufacturing an integrated circuit is also proposed, comprising manufacturing a logic component, the logic component comprising forming alternating portions of a first semiconductor well having a first type of doping and a second semiconductor well having a second type of doping opposite to the first type, the first semiconductor wells extending parallel in a first direction, and the logic component comprising forming standard cells arranged in parallel rows in the first direction, and the integrated circuit having a fixed width, the fixed width covering half the width of one of the first wells and half the width of one of the second wells in a second direction perpendicular to the first direction, each well being shared by two adjacent rows. The method further comprises forming at least one capacitive fill structure belonging to two adjacent rows in the middle of the standard cells, and includes forming a capacitive interface between a conductive armature and a first well, the second well being formed such that its extension in the first direction is interrupted above the length of the capacitive fill structure, the first well being formed to occupy the width of two rows of the capacitive fill structure in the second direction, the formation of the capacitive fill structure further comprising forming a conductive structure configured to...

[0032] According to one embodiment, the formation of the conductive structure includes the formation of at least one metal track located in the metal layer and extending in a first direction opposite to the length of the capacitive fill structure, and the capacitive interface is formed to extend over the entire width of the two rows of the capacitive fill structure in a second direction.

[0033] According to one embodiment, the formation of the conductive structure includes forming a surface semiconductor strip with a second type of strong doping in a first well, the surface semiconductor strip extending over the length of the capacitive filling structure in a first direction, and the capacitive interface being formed to extend in the second direction over the entire width of the two rows of capacitive filling structures excluding the width of the surface semiconductor strip.

[0034] For example, the formation of the surface semiconductor strip includes a silicide step of forming a metal silicide in the surface semiconductor strip.

[0035] For example, the formation of the conductive structure includes forming a shallow insulating trench on either side of the surface semiconductor strip in a second direction.

[0036] For example, the formation of the surface semiconductor strip includes an implantation density of 1 x 10⁻⁶ per cubic centimeter in the first well. 15 One atom and 1 x 10^12 atoms per cubic centimeter 16 Type II doped material between atoms.

[0037] According to one embodiment, the formation of the conductive armature includes the formation of at least one vertical gate structure, the vertical gate extending in depth within the first well.

[0038] For example, forming the vertical gate structure includes forming a trench etched in a first well and covered with a dielectric cladding on the bottom and sides, implanting a region with a second type of doping in the first well at the bottom of the trench, filling the trench with a conductive material, implanting a region with a second type of doping in the trench, and implanting a region with a second type of doping adjacent to the trench on the surface of the first well.

[0039] For example, the formation of the conductive armature of the capacitive fill structure further includes forming at least one horizontal gate structure, the at least one vertical gate structure being located on the surface of the first well facing the at least two vertical gate structures.

[0040] According to one embodiment, the method further includes manufacturing a non-volatile memory comprising a memory cell having a vertical gate buried access transistor and a floating gate state transistor, wherein the formation of the vertical gate structure of the conductive armature is performed simultaneously with the formation of the vertical gate of the buried access transistor of the memory cell. Attached Figure Description

[0041] Other advantages and features will emerge after a review of the detailed description of the implementation and embodiments (without any limitation) and the accompanying drawings, wherein:

[0042] Figure 1 An integrated circuit including logic sections and other peripheral sections is shown;

[0043] Figure 2A-2C This illustrates the implementation of the conductive structure;

[0044] Figures 3A-3C This illustrates another implementation of the conductive structure;

[0045] Figure 4A-4I The steps involved in manufacturing integrated circuits are explained above. Figure 1 As stated above. Detailed Implementation

[0046] Figure 1 An example of an integrated circuit CI is shown, including the logic section LG and other peripheral sections such as the non-volatile memory section NVM and the high-voltage section HV. It should be noted that... Figure 1 The proportions shown are not necessarily proportional.

[0047] The logic section LG includes standard cells CPC, each configured to implement basic logic functions using CMOS technology, such as AND and OR logic gates, latches, etc. Therefore, each standard cell CPC is formed on a first semiconductor well PW with a first type of doping, i.e., for example, P-type, and formed on a second semiconductor well NW with a second type of doping opposite to the first type (i.e., for example, N-type).

[0048] Furthermore, the organization of standard cells CPC in the logic section LG is achieved by arranging standard cells CPC in parallel rows RG along a first direction X, which defines the length of the row RG, and having a fixed width W_RG in a second direction Y perpendicular to the first direction X. The fixed width W_RG is applied to each standard cell CPC. The length of the standard cell CPC is free and can vary depending on the size of the logic circuit that constitutes it.

[0049] In the logic section LG, the first well PW and the second well NW are arranged alternately in parallel along the first direction X, such that each well PW and NW is shared by two adjacent rows RG. Therefore, the rows cover a width W_RG in the second direction Y, which is half the width of the first semiconductor well PW and half the width of the second semiconductor well NW.

[0050] Furthermore, in the standard cell CPC, the logic portion LG includes at least one capacitive fill structure SCR located in a position in the row RG not occupied by the standard cell CPC. Each capacitive fill structure SCR includes a capacitive interface between a conductive armature and a first well PW.

[0051] Each capacitive fill structure SCR belongs to two adjacent rows, and the range of the second well NW in the first direction X is interrupted, that is, the second well NW is not formed above the length of the capacitive fill structure L_SCR. For the first well PW, it occupies the width of two rows RG of the capacitive fill structure W_SCR in the second direction Y.

[0052] Therefore, the following will be combined Figures 2A-2C and Figures 3A-3C The capacitive interface can be formed to extend in the second direction Y over the entire or almost entire width of the two rows of capacitive fill structures W_SCR.

[0053] Furthermore, to ensure electrical continuity in the second semiconductor well NW, each capacitively filled structure SCR includes a conductive structure COND (in... Figure 1 The diagram is schematically shown in the middle by a horizontal line connecting two points (according to the X direction), which electrically connects the second well NW on either side of the capacitively filled structure SCR in the first direction X.

[0054] In this regard, refer to Figure 2A-2C and Figures 3A-3C In particular, it explains the two implementation methods of the conductive structures CONDa and CONDb.

[0055] Figure 2A A top view of a first example of a capacitively filled structure SCRa in a plane (XY) is shown. Figure 2B It shows Figure 2A A cross-sectional view of the capacitively filled structure CRA in the plane BB(XZ). Figure 2C It shows in Figure 2A Cross-sectional view of the capacitive filler structure SCRa on plane CC (YZ). Directions X, Y, and Z correspond to... Figure 2A , 2B The orthogonal reference frame is shared with 2C.

[0056] In this example, the conductive structure CONDa is electrically connected to the second well NW on either side of the capacitively filled structure SCRa via a metal track M1, which extends in the first direction X over the length of the capacitively filled structure L_SCR. The metal track M1 is located on a metal layer, such as a first metal layer, of an interconnect portion commonly referred to as the back-end of the line (BEOL), which is formed above the front side FA of the semiconductor portion and is commonly referred to as the front-end of the line (FEOL). The front side FA typically represents the surface of the semiconductor substrate and the surfaces of the semiconductor wells PW and NW, on which semiconductor devices such as MOS-type transistors and capacitors are formed.

[0057] Therefore, the conductive structure CONDa does not occupy any space in the first well PW, and leaves the entire width W_SCR of the first well PW completely free to form a capacitive interface therein.

[0058] The conductive armature ARM, which forms a MOS-type capacitive interface with the first well PW, advantageously includes at least one vertical gate structure SGV, which extends vertically (along the Z direction) in depth within the first well PW. The vertical gate structure SGV comprises a conductive material, such as polysilicon, filling trenches etched into the first well PW. Dielectric cladding is provided on the sides and bottom of the trenches to electrically insulate the conductive material from the first well PW.

[0059] Furthermore, the vertical gate structures SGV extend in length along the second direction Y and are parallel to each other along the second direction Y. The width of the vertical gate structures SGV in the first direction X is minimized so that the number of parallel vertical gate structures SGV is included in the length L_SCR (first direction X) of the multiply capacitive fill structure SCRa.

[0060] Furthermore, in this example, the conductive armature ARM of the capacitively filled structure SCR also includes a horizontal gate structure SGH, which is located on the surface of the first well PW facing the at least one vertical gate structure SGV. The horizontal gate structure SGH is electrically connected to the vertical gate structure SGV.

[0061] The capacitive interface is defined by the surfaces of the conductive armature ARM and the first well PW facing each other. Therefore, the capacitive interface is specifically formed by the outer surface of the trench that contacts the first well PW.

[0062] Therefore, with Figure 2A As can be seen, the entire available space is occupied by capacitive interfaces within the frames RGDS, each frame RGDS corresponding to the outline of a standard cell CPC with length L_SCR in the corresponding row RG. In this case, the standard cell is absent and is replaced by a capacitively filled structure SCRa.

[0063] In fact, the vertical gate structure SGV and thus the capacitive interface advantageously extend in the second direction Y over the entire length of the two rows RG of the capacitive fill structure W_SCR.

[0064] In the first direction X, negligible space is used to form a contact with the second well NW on either side of the length L_SCR of the capacitive fill structure SCRa, so as to electrically connect the metal track M1 of the conductive structure CONDa there, thereby ensuring the electrical continuity of the second well NW. This space also allows for compatibility with the rule of longitudinal adjacency between adjacent standard cells and the capacitive fill structure SCRa in the first direction X.

[0065] Furthermore, the vertical gate structure SGV may include a region NS with a second type (N-type) doping, which is implanted in the first well PW at the bottom of the trench before the first well PW is filled with conductive material. The vertical gate structure SGV may also include another region with a second type (N-type) doping, which is implanted on the surface of the first well PW (at the front FA).

[0066] These injection regions of the second type of NS, which exist due to the method of manufacturing vertical gate structure SGV, are advantageously combined with the method of manufacturing non-volatile memory cells (see below for details). Figure 4A-4I (Content). In other words, the injection regions NS and AS provide minority carrier sources, allowing the formation of inverted channels along the capacitive interface, which allows the capacitively filled SCR structure to operate in NOT mode.

[0067] Now for reference Figure 3A , 3B And 3C.

[0068] Figure 3AA top view of a second example of a capacitively filled structure SCRb in a plane (XY) is shown. Figure 3B It shows Figure 3A A cross-sectional view of the capacitively filled structure SCRb in the plane BB(XZ). Figure 3C Show Figure 3A Cross-sectional view of the capacitive filler structure SCRb on plane CC (YZ). Directions X, Y, and Z correspond to... Figure 3A , 3B The orthogonal reference frame is shared with 3C.

[0069] In this example, the conductive structure CONDb is electrically connected to a second well NW on either side of the capacitively filled structure SCRb via a surface semiconductor strip BDN+, the surface semiconductor strip having a strong second type (type N, N+) doping located in the first well PW, and extending over the length of the capacitively filled structure L_SCR in the first direction X.

[0070] Compared to the implantation depth of the transistor conduction region, "surface" refers to the implantation depth of the semiconductor band BDN+ located on the surface of the first well PW, rather than being equivalent to the depth of wells such as the first well PW or the second well NW.

[0071] For example, a surface semiconductor band BDN+ with strong N-type doping can be obtained by implanting N-type dopant (typically boron for the substrate) and a first well PW made of silicon, with a density of approximately 5 per cubic centimeter. 10 15 10 atoms per cubic centimeter 16 One atom.

[0072] Advantageously, the surface semiconductor band BDN+ includes metal silicide, thereby allowing for a reduction in the resistivity of the semiconductor band BDN+.

[0073] Furthermore, a shallow insulating trench STI (typically shallow trench insulation) is provided on either side of the surface semiconductor band BDN+ in the second direction Y to avoid short circuits with another adjacent region including metal silicide, such as at the contact CNTSGV of the vertical gate structure SGV.

[0074] The conductive armatures ARMh and ARMb of this example of the capacitive fill structure SCRb have the same characteristics as described above. Figure 2A-2C The conductive armature ARM described herein has the same advantageous design. The same components are supported by the same reference numerals and will not be described in detail herein.

[0075] In other words, when the conductive structure CONDb exists in the first well PW, along the first direction X, the conductive armatures ARMh and ARMb of the capacitive filling structure SCRb are divided into two parts, namely the "upper" part ARMh and the "lower" part ARMb of the conductive structure CONDb on either side of the second direction Y.

[0076] Therefore, each of the components ARMh and ARMb of the conductive armature may specifically include: the vertical gate structure SGV, the injection regions NS and AS, and the horizontal gate structure SG.

[0077] The conductive structure CONDb advantageously passes through the capacitive fill structure SCRb at the midpoint of its width. Therefore, the two parts ARMh and ARMb of the conductive armature can be identical or symmetrical with respect to the midpoint or center point.

[0078] In other words, apart from the width of the surface semiconductor band BDN+, STI, the capacitive interface extends along the entire width of the two rows of the capacitive filling structure W_SCR in the second direction Y. The width of the surface semiconductor band BDN+, STI in the second direction Y is less than 10% of the width of the two rows RG of the capacitive filling structure SCRb, W_SCR.

[0079] Therefore, the quasi-total range of the width W_SCR of the two rows RG of the capacitive fill structure SCRb (e.g., greater than 60% or even greater than 80%) is dedicated to the capacitive interface.

[0080] Now for reference Figures 4A to 4I , Figures 4A to 4I It shows in Figure 2A-2C The first example SCRa and Figures 3A-3C The results of the method steps for manufacturing integrated circuit CI in the second example SCRb shown.

[0081] The manufacturing method also includes, in conjunction with the manufacturing of capacitive fill structures SRa and SCRb, the fabrication of non-volatile memory cells NVM including vertical gate access transistors and floating gate state transistors, high-voltage transistors belonging to the high-voltage portion HV, and low-voltage transistors belonging to the low-voltage portion LV, such as logic portion LG. Figure 1 ).

[0082] Therefore, as shown below, all the steps for manufacturing the capacitive fill structures SCRa and SCRb can also be used to manufacture other devices in the integrated circuit CI. In other words, the methods used to manufacture the capacitive fill structures SCRa and SCRb can be integrated with existing manufacturing methods and are therefore freely implementable.

[0083] The various parts of the integrated circuit CI, NVM, HV, LV, SCRa, and SCRb, are formed from the same semiconductor substrate PSUB, typically p-type doped silicon.

[0084] Corresponding to Figures 3A-3C The example capacitively filled structure SCRb is shown as being in a pair of YZ planes (similar to...) Figure 3C ), and corresponding to Figures 2A-2C The example capacitively filled structure SCA is shown as being in a pair of XZ planes (similar to the attached...) Figure 2B Of course, the manufacturing methods for the two examples mentioned above are shown simultaneously, but in practice, only one of the two examples can be executed.

[0085] Figure 4A The results of defining the trap PWNVM for the non-volatile memory cell NVM and forming the shallow insulating trench STI are shown.

[0086] The formation of shallow insulating trenches (STIs) typically involves etching openings (called trenches) in the substrate PSUB and forming a dielectric material to fill the trenches. STIs are generally present in all parts of an integrated circuit and allow for defining the contours of the "active region" and ensuring lateral electrical insulation between adjacent devices.

[0087] The formation of the well of the memory cell PWNVM is particularly due to specific doping relative to the write voltage involved, and the well PWNVM is insulated and forms the source line (or source plane) of the memory NVM by implanting a buried semiconductor layer NISO at a depth in the substrate PSUB.

[0088] Figure 4B The results of defining the steps of the high-voltage well PW are shown, having a first type of doping, that is, during the operation of the integrated circuit CI, a p-type dopant is implanted at a concentration suitable for the voltage involved in the high-voltage section.

[0089] Figure 4C The results of the etching trench TR step are shown. The trench TR is used to accommodate the vertical gate structure SGV belonging to the memory cell NVM (vertical gate buried access transistor) and the capacitive fill structures SCRa and SCRb. The trench TR is opened in the individual wells PW and PWNVM by dry directional etching of a plasma etching type, using an etch mask pattern. The depth of the trench TR is the same in all parts of the integrated circuit CI, and the bottom of the trench is located at a depth substantially at the source plane NISO, slightly above the source plane.

[0090] The gate dielectric cladding is deposited on the sides and bottom of the trench TR, for example, by thermal growth of a silicon oxide layer.

[0091] Furthermore, a region NS with type II (N-type) doping is implanted at the bottom of the trench TR. The region NS forms the source region of the vertical gate buried access transistor of the memory cell and contacts the source plane NISO.

[0092] Figure 4D The results of the steps in forming the vertical gate structure SGV are shown, including overfilling the trench TR with a conductive material (e.g., polysilicon PO). Excess conductive material overflowing from the trench TR is removed, for example, by a chemical mechanical polishing method.

[0093] In addition, a high-voltage oxide layer HVOX is deposited on the entire front side FA of the substrate PSUB, and then thinned to a thickness called tunnel thickness TNOX in the non-volatile memory NVM portion.

[0094] Figure 4E The results of the steps of forming a first gate conductive layer P1 (typically made of polysilicon) on the high voltage HVOX and tunnel TNOX oxide layers are shown, as well as the results of the etching step GR1 (typically dry etching with a mask pattern), which is typically dry etching in the mask pattern to allow the gate region defining the high voltage transistor HV and to remove the first gate conductive layer P1 in the regions SCRa, SCRb and LV of the integrated circuit CI.

[0095] Figure 4F The results of steps in forming a dielectric layer ONO in a non-volatile memory (NVM) component and a capacitive fill structure SCRa, SCRb are shown. The dielectric layer comprises, for example, a stack of oxide, nitride, and silicon oxide layers.

[0096] Then, wells NW with second-type (i.e., N-type) doping are implanted into the portion of the integrated circuit containing N-type wells, particularly the logic portion LG. Figure 1 The second well NW of LV. Therefore, capacitively filled structures SCRa and SCRb are defined in this step.

[0097] A second gate conductive layer P2, typically made of polysilicon, is formed on the entire surface of the integrated circuit CI. In the first etch GR2HV, the second gate conductive layer P2 is removed in the high-voltage section HV.

[0098] Figure 4G The result of the second etch GR2NVM is shown. In the non-volatile memory NVM region, the floating gate GF and control gate GC regions of the floating gate state transistor are defined by the second gate conductive layer P2, the dielectric stack ONO and the first gate conductive layer P1.

[0099] Figure 4HThe result of the third etching GR2LV of the second gate conductive layer P2 is shown, which defines the gate region of the low-voltage transistor LV and the horizontal gate structure SGH of the capacitive fill structures SCRa and SCRb.

[0100] Figure 4I The results of the step of implanting strongly doped conductive regions N+ and P+ into either side of the gate region of the above-mentioned high-voltage HV, low-voltage LV transistors and floating-gate state transistors are shown.

[0101] Furthermore, this injection step allows for the formation of an n+ contact with the second well NW in the capacitively filled structure SCRa, where a metal track M1 belonging to the conductive structure CONDa is electrically connected via a metal contact post CNT, and in the capacitively filled structure SCRb, a strongly doped surface semiconductor band BDN+ with a second type of N+ belonging to the conductive structure CONDb.

[0102] Prior to the formation of the metal contact pillars (CNTs) and the first metal layer, a silicide process is performed in all portions of the integrated circuit (CI). This allows the formation of metal silicide compounds on the surfaces of all exposed portions made of silicon, particularly the surface semiconductor band BDN+, including transistor conduction regions, well taps, and / or other regions, as well as the gates of transistors made of polysilicon. The metal silicides allow for improved conductivity in the silicon-based regions, especially where ohmic contacts are formed.

Claims

1. An integrated circuit, comprising: The logic section includes standard cells arranged in parallel rows along a first direction and having a fixed width, the fixed width covering half the width of a first semiconductor well having a first type of doping and half the width of a second semiconductor well having a second type of doping opposite to the first type in a second direction perpendicular to the first direction; Each of the first and second semiconductor wells is shared by two adjacent rows; and A capacitive fill structure is located between the standard cells and belongs to two adjacent rows, and the capacitive fill structure includes a capacitive interface between the conductive armature and the first semiconductor well; The second semiconductor well is interrupted in the first direction above the length of the capacitive filling structure, such that the first semiconductor well occupies the width of the two adjacent rows of the capacitive filling structure in the second direction; as well as The capacitive filling structure further includes a conductive structure configured to be electrically connected in the first direction to the second semiconductor well on the opposite side of the capacitive filling structure.

2. The integrated circuit of claim 1, wherein the conductive structure includes at least one metal track located in a layer of metal interconnects and extending in the first direction relative to the length of the capacitive fill structure, and the capacitive interface extending in the second direction over the entire width of the two adjacent rows of the capacitive fill structure.

3. The integrated circuit of claim 1, wherein the conductive structure includes a surface semiconductor strip located in the first semiconductor well and extending in the first direction over the length of the capacitive filling structure, the surface semiconductor strip having strong doping of the second type, and the capacitive interface extending in the second direction over the entire width of the two adjacent rows of the capacitive filling structure excluding the width of the surface semiconductor strip.

4. The integrated circuit of claim 3, wherein the surface semiconductor strip comprises metal silicide.

5. The integrated circuit of claim 3, wherein the conductive structure includes a shallow insulating trench on either side of the surface semiconductor strip extending in the second direction.

6. The integrated circuit of claim 3, wherein the surface semiconductor strip comprises a dopant of the second type implanted into the first semiconductor well, the second type of dopant having a density of 10 15 atoms / cubic centimeter and 10 16 Between atoms per cubic centimeter.

7. The integrated circuit of claim 1, wherein the conductive armature of the capacitive fill structure includes at least one vertical gate structure extending in depth within the first semiconductor well.

8. The integrated circuit of claim 7, wherein the at least one vertical gate structure comprises: The region where the second type of doping is implanted at the first vertical end of the vertical gate structure located at the depth of the first semiconductor well, and the region where the second type of doping is implanted at the second vertical end of the vertical gate structure located on the surface of the first semiconductor well.

9. The integrated circuit of claim 7, wherein the conductive armature of the capacitive fill structure further comprises at least one horizontal gate structure, the at least one horizontal gate structure being located on the surface of the first semiconductor well facing the at least one vertical gate structure.

10. The integrated circuit of claim 7 further includes a non-volatile memory, the volatile memory comprising a memory cell having a vertical gate buried access transistor and a floating gate state transistor, wherein the vertical gate structure of the conductive armature is made of the same material as the vertical gate of the vertical gate buried access transistor and has the same depth.

11. A method for manufacturing an integrated circuit, comprising: Manufacturing logic components, including: An alternating portion is formed of a first semiconductor well having a first type of doping and a second semiconductor well having a second type of doping opposite to the first type, the alternating portion extending parallel in length in a first direction; Standard cells are formed in parallel rows along the first direction. The standard cells have a fixed width, which covers half the width of one of the first semiconductor wells and half the width of one of the second semiconductor wells in a second direction perpendicular to the first direction. Each of the first and second semiconductor wells is shared by two adjacent rows; In the middle of the standard cell, a capacitive filling structure belonging to two adjacent rows is formed through the following steps: The second semiconductor well is interrupted in the first direction above the length of the capacitive filling structure, such that the first semiconductor well occupies the width of the two adjacent rows of the capacitive filling structure in the second direction; A capacitive interface is formed between the conductive armature and the first semiconductor well; and A conductive structure is formed, the conductive structure being configured to be electrically connected in the first direction to the second semiconductor well on the opposite side of the capacitive filling structure.

12. The method of claim 11, wherein forming the conductive structure comprises forming at least one metal track located in a layer of metal interconnects and extending in the first direction toward the length of the capacitive fill structure, and wherein the capacitive interface extends in the second direction over the entire width of the two adjacent rows of the capacitive fill structure.

13. The method of claim 11, wherein forming the conductive structure comprises forming a surface semiconductor strip in the first semiconductor well, the surface semiconductor strip having strong doping of the second type, and the surface semiconductor strip extending in the first direction over the length of the capacitive filling structure, and wherein the capacitive interface extends in the second direction over the entire width of the two adjacent rows of the capacitive filling structure, excluding the width of the surface semiconductor strip.

14. The method of claim 13, wherein forming the conductive structure further comprises silicide formation of a metal silicide in the surface semiconductor strip.

15. The method of claim 13, wherein forming the conductive structure further comprises forming a shallow insulating trench on either side of the surface semiconductor strip extending in the second direction.

16. The method of claim 13, wherein forming the surface semiconductor strip comprises implanting a dopant of the second type into the first semiconductor well, the density of the second type of dopant being 10 15 atoms / cubic centimeter and 10 16 Between atoms per cubic centimeter.

17. The method of claim 11, wherein forming the conductive armature comprises forming at least one vertical gate structure extending in depth within the first semiconductor well.

18. The method of claim 17, wherein forming the vertical gate structure comprises: A trench is formed, the trench being etched into the first semiconductor well and covered with a dielectric encapsulation on the bottom and sides; A region with the second type of doping is implanted into the first semiconductor well at the bottom of the trench; The trench is filled with a conductive material; as well as A region with the second type of doping is implanted on the surface of the first semiconductor well, adjacent to the trench.

19. The method of claim 17, wherein the conductive armature forming the capacitive fill structure further comprises a horizontal gate structure formed on a surface of the first semiconductor well facing the at least one vertical gate structure.

20. The method of claim 17, further comprising: Manufacturing a non-volatile memory, which includes a memory cell provided with a vertical gate buried access transistor and a floating gate state transistor; The vertical gate structure forming the conductive armature and the vertical gate forming the vertical gate buried access transistor are performed simultaneously.

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