A fan-out packaging structure and its forming method

Abstract

This invention relates to a fan-out packaging structure, characterized by comprising: a first wafer; a second wafer having a cavity and anode-bonded to the first wafer; and a chip stack structure located within the cavity of the second wafer and connected to the first wafer via a bonding layer. The cavity depth in this fan-out packaging structure is uniform, and the use of a metal bonding layer instead of adhesive results in low and uniform thermal resistance distribution on the back side of the chip. This invention also relates to a method for forming the fan-out packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging structure and its formation method. Background Technology

[0002] Currently, there are two main types of fan-out packaging: one based on epoxy molding compound (EMC) and the other based on silicon. Silicon-based fan-out packaging involves etching cavities on a silicon wafer, then attaching the chip to the cavities using adhesive, filling the gaps with filler material, and finally fabricating the redistribution layer (RDL) fan-out structure. Silicon-based fan-out packaging has two main problems. First, the adhesive has low thermal conductivity, resulting in high thermal resistance on the back side of the chip. Also, the etched cavities are not perfectly flat, being concave, leading to uneven adhesive thickness and uneven thermal resistance distribution. Therefore, this silicon-based fan-out packaging method is not suitable for high-power-density chip fan-out packaging. Second, it is difficult to achieve uniform depth of cavities formed at different locations on the silicon wafer through etching. Summary of the Invention

[0003] To address at least some of the aforementioned problems in the prior art, the present invention provides a fan-out packaging structure and a method for forming the same. The fan-out packaging structure has a uniform cavity depth and uses a metal bonding layer instead of adhesive, resulting in low thermal resistance and uniform thermal resistance distribution on the back side of the chip.

[0004] In a first aspect, the present invention provides a fan-out packaging structure, comprising:

[0005] First wafer;

[0006] The second wafer has a cavity and is anode-bonded to the first wafer;

[0007] A chip stack structure is located in the cavity of the second wafer and is connected to the first wafer through a bonding layer.

[0008] In one embodiment of the present invention, it further includes:

[0009] Insulating material is located on the front side of the chip stack structure and the front side of the second wafer, as well as in the gap between them;

[0010] The dielectric layer, which sits on top of the insulating material;

[0011] A redistribution layer, located within a dielectric layer and electrically connected to the chip stack structure via conductive vias in an insulating material; and

[0012] Solder balls are arranged on the redistribution layer.

[0013] In one embodiment of the present invention, the bonding layer is formed by bonding a second bonding layer located on the back side of the chip stack structure and a first bonding layer located on the front side of the first wafer; and

[0014] The bonding layer is made of metal and has a uniform thickness.

[0015] In one embodiment of the present invention, the chip stacking structure is formed by stacking multiple chips back to back, and the spaces between the chips are filled with a bottom filler material.

[0016] In one embodiment of the present invention, the first wafer has microchannels located on the back side of the first wafer or extending through the first wafer, the microchannels being used to cool the chip stack structure.

[0017] In a second aspect, the present invention provides a method for forming a fan-out packaging structure, characterized in that it includes:

[0018] A first bonding layer is formed on the front side of the first wafer, and the front side of the wafer is anodicly bonded to a second wafer with a cavity.

[0019] A second bonding layer is formed on the back of the first-layer chip, then a chip stack structure is formed, and cut to form a single-chip stack structure; and

[0020] The single-chip stack structure is arranged in a cavity by bonding the second solder layer on the back of the single-chip stack structure to the first solder layer.

[0021] In one embodiment of the present invention, the invention further includes filling the front side of the single-chip stack structure and the front side of the second wafer and the gap between them with an insulating material, then arranging a dielectric layer and a redistribution layer electrically connected to the single-chip stack structure on the insulating material, and arranging solder balls on the redistribution layer.

[0022] In one embodiment of the present invention, the first solder layer is located in the middle of the front side of the first wafer, and after the first wafer and the second wafer are bonded, the first solder layer is located in the cavity of the second wafer.

[0023] In one embodiment of the present invention, both the first weld layer and the second weld layer are metals and have uniform thickness; and / or

[0024] The back side of the first wafer has microchannels for cooling the chip stack structure.

[0025] In one embodiment of the present invention, the back side of the first layer chip is metallized and a solder layer is grown, and then multiple chips are stacked back to back to form a chip stack structure using a wafer-level process, and underfill adhesive is filled between the chips.

[0026] The present invention has at least the following beneficial effects: The fan-out packaging structure and its formation method disclosed in the present invention adopt a non-etching process, and obtains a flat cavity with consistent depth by bonding a second wafer with a cavity to a first wafer; the use of a metal bonding layer instead of adhesive makes the thermal resistance on the back of the chip low and the bonding layer thickness uniform, thereby achieving uniform thermal resistance distribution; microchannels can also be integrated in the first wafer to further improve the heat dissipation capability of the fan-out packaging structure. Attached Figure Description

[0027] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0028] Figure 1 A cross-sectional schematic diagram of a fan-out packaging structure according to an embodiment of the present invention is shown;

[0029] Figure 2 A cross-sectional schematic diagram of a fan-out packaging structure with microchannels according to an embodiment of the present invention is shown;

[0030] Figures 3A to 3D A schematic cross-sectional view of the process of forming such a fan-out packaging structure according to an embodiment of the present invention is shown. Detailed Implementation

[0031] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0032] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0033] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0034] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0035] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0036] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0038] Figure 1 A cross-sectional schematic diagram of a fan-out packaging structure according to an embodiment of the present invention is shown.

[0039] like Figure 1 As shown, a fan-out package structure includes a first wafer 101, a second wafer 102, a bonding layer 103, a chip stack structure 104, an insulating material 105, a dielectric layer 106, a redistribution layer 107, and solder balls 108.

[0040] The first wafer 101 and the second wafer 102 are anoly bonded. The second wafer 102 has a cavity that extends through the second wafer 102. A flat cavity of uniform depth is obtained by bonding the second wafer 102 with the cavity to the first wafer 101 using a non-etching process.

[0041] The chip stack structure 104 is located in the cavity and is connected to the front side of the first wafer 101 via a bonding layer 103. The bonding layer 103 is formed by bonding a first solder layer on the front side of the first wafer 101 and a second solder layer on the back side of the chip stack structure 104. The chip stack structure 104 is formed by stacking multiple chips back-to-back, with underfill material filling the spaces between the chips. The front side of the first chip layer is connected to the back side of the second chip layer, the front side of the second chip layer is connected to the back side of the third chip layer, and so on, forming the chip stack structure. The bonding layer 103, made of metal, has high thermal conductivity, resulting in low thermal resistance on the back side of the chip. Furthermore, the cavity is flat, the bonding layer 103 has uniform thickness, and the thermal resistance distribution is uniform.

[0042] Insulating material 105 is located on the front side of the chip stack structure 104 and the front side of the second wafer 102, as well as in the gap between them.

[0043] The dielectric layer 106 is located on top of the insulating material 105.

[0044] The redistribution layer 107 is located in the dielectric layer 106 and is electrically connected to the chip stack structure 104 through conductive vias located in the insulating material 105. The surface of the redistribution layer 107 is exposed above the dielectric layer 106.

[0045] Solder balls 108 are arranged on redistribution layer 107.

[0046] Next, let's combine... Figure 2 This paper will provide a detailed description of a fan-out packaging structure with microfluidics according to an embodiment of the present invention. Figure 2 A cross-sectional schematic diagram of a fan-out packaging structure with microchannels according to an embodiment of the present invention is shown.

[0047] The fan-out package structure with microchannels includes: a first wafer 201, a second wafer 202, a bonding layer 203, a chip stack structure 204, an insulating material 205, a dielectric layer 206, a redistribution layer 207, solder balls 208, and microchannels 209.

[0048] Figure 2 The described embodiments and Figure 1 Compared to the previous embodiment, the only difference is that the back side of the first wafer 201 has microchannels 209. These microchannels are used to cool the chip stack structure 204, which can improve the heat dissipation performance of the fan-out package structure.

[0049] In other embodiments of the present invention, the microchannel 209 penetrates through the first wafer 201 and is closer to the chip stack structure 204, resulting in better heat dissipation.

[0050] Figures 3A to 3D A schematic cross-sectional view of the process of forming such a fan-out packaging structure according to an embodiment of the present invention is shown.

[0051] A method for forming a fan-out package structure includes:

[0052] Step 1, as follows Figure 3A As shown, a first bonding layer 302 is formed on the front side of a first wafer 301, and the front side of wafer 301 is anodically bonded to a second wafer 303 having a cavity. The first bonding layer 302 is located in the center of the front side of the first wafer 301, and after bonding, the first bonding layer 302 is located in the cavity of the second wafer 303. The thickness of the first bonding layer 302 is uniform. The first wafer 301 can be, for example, a silicon wafer, and the second wafer 303 can be, for example, a glass wafer. In another embodiment of the invention, the back side of the first wafer has microchannels. The microchannels are used for cooling, which can improve the heat dissipation performance of the fan-out packaging structure.

[0053] Step 2, as follows Figure 3BAs shown, a second solder layer 305 is formed on the back side of the first-layer chip 304, then a chip stack structure is formed, and diced to form a single-chip stack structure 300. The back side of the first-layer chip 304 is metallized and a solder layer is grown. Then, multiple chips are stacked back-to-back using wafer-level processes to form a chip stack structure, and underfill adhesive is filled between the chips. The back side of the second-layer chip is connected to the front side of the first-layer chip, the front side of the second-layer chip is connected to the back side of the third-layer chip, and so on, forming the chip stack structure. The second solder layer 305 is a metallic material with low thermal resistance; if the thickness of the second solder layer 305 is uniform, the thermal resistance distribution is also uniform.

[0054] Step 3, as follows Figure 3C As shown, a single-chip stack structure 300 is arranged in a cavity. The single-chip stack structure 300 is arranged in the cavity by bonding the second solder layer 305 to the first solder layer 302 on the back side of the single-chip stack structure 300. Both the second solder layer 305 and the first solder layer 302 are metals, and their bonding results in low thermal resistance and uniform thermal resistance distribution on the back side of the chip.

[0055] Step 4, as follows Figure 3D As shown, insulating material 306 is filled on the front side of the single-chip stack structure 300, the front side of the second wafer 303, and the gap between them. Then, a dielectric layer 307 and a redistribution layer 308 electrically connected to the single-chip stack structure 300 are disposed on the insulating material 306, and solder balls 309 are disposed on the redistribution layer 308. Vias are formed in the insulating material 306 on the front side of the single-chip stack structure 300 by etching, and then metal is electroplated to fill the vias to form conductive vias, which are electrically connected to the single-chip stack structure 300. A dielectric layer 307 is disposed on the insulating material 306, and then the dielectric layer is etched to form a circuit pattern, and metal is filled into the circuit pattern to form the redistribution layer 308. The redistribution layer 308 is electrically connected to the single-chip stack structure 300 through conductive vias.

[0056] The present invention has at least the following beneficial effects: The fan-out packaging structure and its formation method disclosed in the present invention adopt a non-etching process, and obtains a flat cavity with consistent depth by bonding a second wafer with a cavity to a first wafer; the use of a metal bonding layer instead of adhesive makes the thermal resistance on the back of the chip low and the bonding layer thickness uniform, thereby achieving uniform thermal resistance distribution; microchannels can also be integrated in the first wafer to further improve the heat dissipation capability of the fan-out packaging structure.

[0057] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A method for forming a fan-out packaging structure, characterized in that, include: A first bonding layer is formed on the front side of the first wafer, and the front side of the first wafer is anodicly bonded to a second wafer with a cavity, the cavity penetrating the second wafer; The first solder layer is located in the middle of the front side of the first wafer. After the first wafer and the second wafer are bonded, the first solder layer is located in the cavity of the second wafer. A second bonding layer is formed on the back of the first-layer chip, then a chip stack structure is formed, and cut to form a single-chip stack structure; as well as The single-chip stack structure is arranged in a cavity by bonding the second solder layer on the back side of the single-chip stack structure to the first solder layer; both the first solder layer and the second solder layer are metal and have uniform thickness. An insulating material is filled on the front side of the single-chip stack structure, the front side of the second wafer, and the gap between them. Then, a dielectric layer and a redistribution layer electrically connected to the single-chip stack structure are arranged on the insulating material, and solder balls are arranged on the redistribution layer.

2. The method for forming the fan-out packaging structure according to claim 1, characterized in that, The back side of the first wafer has microchannels for cooling the chip stack structure.

3. The method for forming the fan-out packaging structure according to claim 1, characterized in that, The back side of the first layer of chip is metallized and a solder layer is grown. Then, multiple chips are stacked back to back using wafer-level processes to form a chip stack structure, and underfill adhesive is filled between the chips.

4. A fan-out packaging structure formed according to the method of claim 1, 2 or 3, characterized in that, include: First wafer; The second wafer has a cavity and is anode-bonded to the first wafer; A chip stack structure is located in the cavity of the second wafer and is connected to the first wafer through a bonding layer.

5. The fan-out packaging structure according to claim 4, characterized in that, Also includes: Insulating material is located on the front side of the chip stack structure and the front side of the second wafer, as well as in the gap between them; The dielectric layer, which sits on top of the insulating material; A redistribution layer, located within a dielectric layer and electrically connected to the chip stack structure via conductive vias in an insulating material; and Solder balls are arranged on the redistribution layer.

6. The fan-out packaging structure according to claim 4, characterized in that, The bonding layer is formed by bonding a second bonding layer located on the back side of the chip stack structure and a first bonding layer located on the front side of the first wafer; and The bonding layer is made of metal and has a uniform thickness.

7. The fan-out packaging structure according to claim 4, characterized in that, The chip stacking structure is formed by stacking multiple chips back to back, with underfill material filling the spaces between the chips.

8. The fan-out packaging structure according to claim 4, characterized in that, The first wafer has microchannels located on the back of the first wafer or extending through the first wafer, the microchannels being used to cool the chip stack structure.

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