半导体存储器装置及制造半导体存储器装置的方法
By employing a segmented insulating layer design in the three-dimensional memory structure of NAND flash memory, the problem of low yield was solved, and the stability and performance of the memory device were improved.
CN115831924BActive Publication Date: 2026-07-17KIOXIA CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2022-03-07
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
The existing three-dimensional memory structure of NAND flash memory suffers from low yield during the manufacturing process.
Method used
By employing a segmentation method that utilizes multiple interconnect layers, memory pillars, a first component, and an insulating layer for the segmented portion, the insulation and stability of the segmented portion of the memory pillar are improved.
Benefits of technology
It improves the yield of semiconductor memory devices, enhances the insulation and stability of the segmented parts of the memory pillars, and improves the overall performance of the memory devices.
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Abstract
本文中描述的实施例大体上涉及一种半导体存储器装置及一种制造所述半导体存储器装置的方法。根据一个实施例，一种半导体存储器装置包含：互连层，其堆叠于衬底上方；存储器支柱，其经配置以穿透所述互连层；第一构件及第二构件；及分割部分，其提供于所述第一构件与所述第二构件之间。所述分割部分包含绝缘层。所述绝缘层各自包含第一部分及第二部分。所述第一部分提供于所述第一构件与所述第二部分之间。所述第二部分提供于所述第一部分与所述第二构件之间。所述第一部分及所述第二部分在从顶部看时各自具有个别弧形且彼此接触。
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