Semiconductor device

Abstract

Provided is a semiconductor device with improved reliability, comprising: a first metal layer connected to a first main terminal at a first connection region; a second metal layer connected to a second main terminal at a second connection region; a third metal layer connected to an output terminal; a plurality of first semiconductor chips arranged in a first direction, comprising a first upper electrode, a first lower electrode, a first gate electrode, and a first Schottky barrier diode, the first lower electrode being connected to the first metal layer; a plurality of second semiconductor chips arranged in the first direction, comprising a second upper electrode, a second lower electrode, a second gate electrode, and a second Schottky barrier diode, the second lower electrode being connected to the third metal layer; a first connection line connecting the first upper electrode and the third metal layer; and a second connection line connecting the second upper electrode and the second metal layer, an angle between the third direction and the first direction, and an angle between the elongation direction of the first connection line and the second connection line and the second direction being 20 degrees or less.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-152688 (filed on September 17, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Silicon carbide (SiC) is anticipated as a material for next-generation semiconductor devices. Compared to silicon, SiC has superior physical properties, including a band gap three times larger, a breaking electric field strength approximately ten times stronger, and thermal conductivity approximately three times greater. If these properties are fully utilized, it is possible to realize, for example, high-voltage, low-loss MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) capable of operating at high temperatures.

[0005] Vertical MOSFETs using silicon carbide have a pn junction diode as the body diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, return current can flow through by using the body diode.

[0006] However, if a body diode is used to carry the return current, there is a problem that the stacking defects in the silicon carbide layer grow due to the recombination energy of charge carriers, increasing the on-resistance of the MOSFET. This increased on-resistance leads to a decrease in the reliability of the MOSFET.

[0007] There are MOSFETs with a built-in Schottky barrier diode (SBD) that operates unipolarly. By using an SBD to flow the return current instead of a pn junction diode that operates bipolarly, the growth of stack-up defects is suppressed, and the reliability of the MOSFET is improved. Summary of the Invention

[0008] Embodiments of the present invention provide semiconductor devices with improved reliability.

[0009] A semiconductor device according to one aspect of the present invention includes: an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer disposed on the insulating substrate and having a first connection region electrically connected to the first main terminal in the first connection region; a second metal layer disposed on the insulating substrate and having a second connection region electrically connected to the second main terminal in the second connection region; a third metal layer disposed on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region electrically connected to the output terminal in the third connection region; a plurality of first semiconductor chips, each including a first upper electrode, a first lower electrode, a first gate electrode, and a first silicon carbide layer, and including a first Schottky barrier diode, wherein the first lower electrode is electrically connected to the first metal layer, and the plurality of first semiconductor chips are arranged in a first direction; and a plurality of second semiconductor chips, each including a second upper electrode, a second lower electrode, and a second gate electrode. The first semiconductor chip has a second silicon carbide layer, including a second Schottky barrier diode, and a second lower electrode electrically connected to the third metal layer. The plurality of second semiconductor chips are arranged in the first direction. A first connecting line electrically connects the first upper electrode to the third metal layer. A second connecting line electrically connects the second upper electrode to the second metal layer. A second semiconductor chip exists in a second direction perpendicular to the first direction and parallel to the insulating substrate. The angle between the third direction connecting the first and second connecting regions and the first direction is less than 20 degrees. The angle between the extension direction of the first connecting line and the second direction is less than 20 degrees. Among the plurality of second semiconductor chips, the angle between the extension direction of the second connecting line connecting the second upper electrode of the second semiconductor chip closest to the first metal layer in the first direction and the second direction is less than 20 degrees. Attached Figure Description

[0010] Figure 1 This is a schematic top view of the semiconductor device according to the embodiment.

[0011] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the embodiment.

[0012] Figure 3 This is an equivalent circuit diagram of the semiconductor device in the implementation method.

[0013] Figure 4 This is a schematic top view of a comparative example semiconductor device.

[0014] Figure 5 This is an illustration of the problem points of a comparative example semiconductor device.

[0015] Figure 6This is an explanatory diagram illustrating the function and effects of the semiconductor device in the implementation method. Detailed Implementation

[0016] In this specification, the same or similar components are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0017] In this specification, to indicate the positional relationship of components, the upper direction of the attached drawings is sometimes described as "upper" and the lower direction as "lower". In this specification, the concepts of "upper" and "lower" do not necessarily refer to their relationship with the direction of gravity.

[0018] The semiconductor device of the embodiment includes: an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer disposed on the insulating substrate, having a first connection region electrically connected to the first main terminal in the first connection region; a second metal layer disposed on the insulating substrate, having a second connection region electrically connected to the second main terminal in the second connection region; a third metal layer disposed on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region electrically connected to the output terminal in the third connection region; a plurality of first semiconductor chips, each including a first upper electrode, a first lower electrode, a first gate electrode, and a first silicon carbide layer, including a first Schottky barrier diode, the first lower electrode being electrically connected to the first metal layer, the plurality of first semiconductor chips arranged in a first direction; a plurality of second semiconductor chips, each including a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, including a second Schottky barrier diode, the second lower electrode being electrically connected to the third metal layer, the plurality of second semiconductor chips arranged in a first direction; a first connecting line electrically connecting the first upper electrode to the third metal layer; and a second connecting line electrically connecting the second upper electrode to the second metal layer. Furthermore, a second semiconductor chip exists in a second direction that is perpendicular to the first direction and parallel to the insulating substrate. The angle between the third direction connecting the first connection region and the second connection region and the first direction is 20 degrees or less. The angle between the extension direction of the first connection line and the second direction is 20 degrees or less. Among the multiple second semiconductor chips, the angle between the extension direction of the second connection line that connects to the second upper electrode of the second semiconductor chip closest to the first metal layer in the first direction and the second direction is 20 degrees or less.

[0019] Figure 1 This is a schematic top view of the semiconductor device according to the embodiment. Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the embodiment. Figure 2 yes Figure 1 AA' section. Figure 3 This is an equivalent circuit diagram of the semiconductor device in the implementation method.

[0020] The semiconductor device in this embodiment is a power semiconductor module 100. For example... Figure 3 As shown, the power semiconductor module 100 of this embodiment is a so-called "2-in-1" type module capable of forming a half-bridge circuit with a single module. Three half-bridge units are connected in parallel within the power semiconductor module 100. For example, by using three power semiconductor modules of this embodiment, a three-phase inverter circuit can be constructed.

[0021] like Figure 3 As shown, the power semiconductor module 100 includes a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), multiple high-side MOSFETs 11 (first semiconductor chips), and multiple low-side MOSFETs 21 (second semiconductor chips). Each MOSFET, in addition to a pn junction diode, also incorporates a Schottky barrier diode (SBD). The SBD, for example, functions to allow return current to pass through.

[0022] Multiple high-side MOSFETs 11 are connected in parallel. Multiple low-side MOSFETs 21 are connected in parallel. Multiple high-side MOSFETs 11 and multiple low-side MOSFETs 21 are connected in series.

[0023] Figures 1 to 3 The example illustrates a scenario where there are 3 high-side MOSFETs 11 and 3 low-side MOSFETs 21.

[0024] The power semiconductor module 100 of the implementation method is as follows: Figure 1 and Figure 2 As shown, it includes a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), multiple high-side MOSFETs 11 (first semiconductor chips), multiple low-side MOSFETs 21 (second semiconductor chips), a resin housing 24, a cover 26, a metal base 28, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36 (fourth metal layer), a second gate metal layer 37 (fifth metal layer), a back metal layer 40, a first gate terminal 41, a second gate terminal 42, a first bonding line 44 (first connecting line), a second bonding line 46 (second connecting line), a gate bonding line 48, and a sealing resin 50.

[0025] Multiple high-side MOSFETs 11 (first semiconductor chips) respectively include a first source electrode 11a (first upper electrode), a first drain electrode 11b (first lower electrode), a first gate electrode 11c, a first silicon carbide layer 11x, and a first Schottky barrier diode 11y.

[0026] Multiple low-side MOSFETs 21 (second semiconductor chips) respectively include a second source electrode 21a (second upper electrode), a second drain electrode 21b (second lower electrode), a second gate electrode 21c, a second silicon carbide layer 21x, and a second Schottky barrier diode 21y.

[0027] The first metal layer 31 has a first connection region 31x. The second metal layer 32 has a second connection region 32x. The third metal layer 33 has a third connection region 33x.

[0028] Figure 1 This is a top view of the power semiconductor module 100 after removing the cover 26 and the sealing resin 50.

[0029] The metal base 28 is, for example, copper. For example, when the power semiconductor module 100 is mounted in the product, a heat sink (not shown) is connected to the back of the metal base 28.

[0030] An insulating substrate 30 is disposed on a metal base 28. The insulating substrate 30 is disposed between the metal base 28 and the high-side MOSFET 11, and between the metal base 28 and the low-side MOSFET 21.

[0031] The insulating substrate 30 has the function of electrically separating the metal base 28 from the high-side MOSFET 11 and the metal base 28 from the low-side MOSFET 21.

[0032] The insulating substrate 30 is, for example, ceramic. The insulating substrate 30 is, for example, alumina, aluminum nitride, or silicon nitride.

[0033] A first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36, and a second gate metal layer 37 are disposed on the surface of the insulating substrate 30. The first metal layer 31, the second metal layer 32, the third metal layer 33, the first gate metal layer 36, and the second gate metal layer 37 are, for example, copper.

[0034] A back metal layer 40 is provided on the back side of the insulating substrate 30. The back metal layer 40 is, for example, copper. The back metal layer 40 is bonded to the metal base 28, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0035] A resin housing 24 is disposed around the metal base 28 and the insulating substrate 30. A portion of the resin housing 24 is disposed on the metal base 28. The resin housing 24 functions to protect the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0036] A cover 26 is provided on the resin housing 24. The cover 26 has the function of protecting the high-side MOSFET 11, the low-side MOSFET 21 and the insulating substrate 30.

[0037] Multiple high-side MOSFETs 11 are disposed on the first metal layer 31. Each high-side MOSFET 11 includes a first source electrode 11a, a first drain electrode 11b, a first gate electrode 11c, a first silicon carbide layer 11x, and a first Schottky barrier diode 11y. The first source electrode 11a is an example of a first upper electrode. The first drain electrode 11b is an example of a first lower electrode.

[0038] The first source electrode 11a is electrically connected to the third metal layer 33. The first source electrode 11a and the third metal layer 33 are electrically connected, for example, using a first bonding wire 44. The first drain electrode 11b is electrically connected to the first metal layer 31. The first drain electrode 11b is electrically connected to the first metal layer 31, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0039] Multiple high-side MOSFETs 11 are arranged in a first direction parallel to the insulating substrate 30.

[0040] Multiple low-side MOSFETs 21 are disposed on the third metal layer 33. Each low-side MOSFET 21 includes a second source electrode 21a, a second drain electrode 21b, a second gate electrode 21c, a second silicon carbide layer 21x, and a second Schottky barrier diode 21y. The second source electrode 21a is an example of a second upper electrode. The second drain electrode 21b is an example of a second lower electrode.

[0041] The second source electrode 21a is electrically connected to the second metal layer 32. The second source electrode 21a and the second metal layer 32 are electrically connected, for example, using a second bonding wire 46. The second drain electrode 21b is electrically connected to the third metal layer 33, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0042] Multiple low-side MOSFETs 21 are arranged in a first direction parallel to the insulating substrate 30.

[0043] Sealing resin 50 is filled in resin housing 24. Sealing resin 50 is surrounded by resin housing 24. Sealing resin 50 covers high-side MOSFET 11, low-side MOSFET 21 and insulating substrate 30.

[0044] The sealing resin 50 has the function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30. In addition, it has the function of insulating the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0045] The sealing resin 50 comprises a resin. The sealing resin 50 is, for example, a silicone gel. Other resins, such as epoxy resin and polyimide resin, can also be used for the sealing resin 50.

[0046] The positive terminal P is disposed on one end of the insulating substrate 30. For example, in Figure 1 In the middle, the positive terminal P is located on the right side of the insulating substrate 30. The positive terminal P has a wiring connection hole.

[0047] The positive terminal P is electrically connected to the first metal layer 31 in the first connection region 31x. In the first connection region 31x, the first metal layer 31 and the positive terminal P are connected, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0048] A positive voltage, for example, is applied to the positive terminal P from the outside. The positive terminal P is formed of metal. For example, the positive terminal P is copper.

[0049] The negative terminal N is disposed on one end of the insulating substrate 30. The negative terminal N and the positive terminal P are disposed on the same side of the insulating substrate 30. The negative terminal N has a wiring connection hole.

[0050] The negative terminal N is electrically connected to the second metal layer 32 in the second connection region 32x. In the second connection region 32x, the second metal layer 32 and the negative terminal N are connected, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0051] A negative voltage, for example, is applied to the negative terminal N from the outside. The negative terminal N is formed of metal. For example, the negative terminal N is copper.

[0052] An AC output terminal is located on one end of the insulating substrate 30. The AC output terminal, along with the positive terminal P and the negative terminal N, are located on the same side of the insulating substrate 30. The AC output terminal AC has a wiring connection hole.

[0053] The AC output terminal is electrically connected to the third metal layer 33 in the third connection region 33x. In the third connection region 33x, the third metal layer 33 and the AC output terminal are connected, for example, using a solder layer or a silver nanoparticle layer (not shown).

[0054] The AC output terminal outputs the output current of the half-bridge circuit. The AC output terminal is made of metal, such as copper.

[0055] The first gate terminal 41 is electrically connected to the first gate electrode 11c of the high-side MOSFET 11. The first gate terminal 41 is electrically connected to the first gate electrode 11c, for example, using a first gate metal layer 36 and a gate bonding line 48.

[0056] The second gate terminal 42 is electrically connected to the second gate electrode 21c of the low-side MOSFET 21. The second gate terminal 42 is electrically connected to the second gate electrode 21c, for example, using a second gate metal layer 37 and a gate bonding line 48.

[0057] A first metal layer 31 is disposed on an insulating substrate 30. The first metal layer 31 has a first connection region 31x. The first metal layer 31 is electrically connected to the positive terminal P in the first connection region 31x.

[0058] A second metal layer 32 is disposed on the insulating substrate 30. The second metal layer 32 has a second connection region 32x. The second metal layer 32 is electrically connected to the negative terminal N in the second connection region 32x. The second metal layer 32 is electrically connected to the second source electrode 21a of the low-side MOSFET 21.

[0059] A third metal layer 33 is disposed on the insulating substrate 30. The third metal layer 33 includes a third connection region 33x. The third metal layer 33 is electrically connected to the AC output terminal AC in the third connection region 33x. The third metal layer 33 is electrically connected to the first source electrode 11a of the high-side MOSFET 11.

[0060] In each of the plurality of high-side MOSFETs 11, in a second direction perpendicular to the first direction and parallel to the insulating substrate 30, there is one of the plurality of low-side MOSFETs 21. In other words, the high-side MOSFET 11 is disposed adjacent to the low-side MOSFET 21 in the second direction.

[0061] The direction connecting the first connecting region 31x and the second connecting region 32x is defined as the third direction. The third direction is the direction of the line segment connecting the first connecting region 31x and the second connecting region 32x with the shortest distance. The angle between the third direction and the first direction is less than 20 degrees.

[0062] For example, in Figure 1 In this configuration, the third direction is parallel to the first direction. The angle between the third direction and the first direction is 0 degrees. Therefore, multiple high-side MOSFETs 11 are arranged along the third direction. Additionally, multiple low-side MOSFETs 21 are arranged along the third direction.

[0063] The angle between the extension direction of the first bonding line 44 and the second direction is 20 degrees or less. For example, when a high-side MOSFET 11 is connected to multiple first bonding lines 44, the angle between the extension direction of at least one of the multiple first bonding lines 44 and the second direction is 20 degrees or less. The angle between the extension direction of the first bonding line 44 connected to any one of the multiple high-side MOSFETs 11 and the second direction is 20 degrees or less.

[0064] The angle between the extension direction of the first bonding line 44 and a third direction is 70 degrees or more and 90 degrees or less. For example, when a high-side MOSFET 11 is connected to multiple first bonding lines 44, the angle between the extension direction of at least one of the multiple first bonding lines 44 and a third direction is 70 degrees or more and 90 degrees or less. The angle between the extension direction of the first bonding line 44 connected to any one of the multiple high-side MOSFETs 11 and a third direction is 70 degrees or more and 90 degrees or less.

[0065] Furthermore, the elongation direction of the so-called first bonding line 44 is, for example, the direction of the line segment connecting the position where the first bonding line 44 is connected to the first source electrode 11a and the position where the first bonding line 44 is connected to the third metal layer 33.

[0066] For example, the angle between the elongation direction and the second direction of all the first bonding lines 44 of the semiconductor module 100 is less than 20 degrees. Figure 1 The diagram shows the case where the angle between the extension direction and the second direction of all the first bonding lines 44 of the semiconductor module 100 is 0 degrees.

[0067] The angle between the extension direction of the second bonding line 46 and the second direction is 20 degrees or less. For example, when a low-side MOSFET 21 is connected to multiple first bonding lines 44, the angle between the extension direction of at least one of the multiple second bonding lines 46 and the second direction is 20 degrees or less. The angle between the extension direction of the second bonding line 46 connected to any one of the multiple low-side MOSFETs 21 and the second direction is 20 degrees or less.

[0068] Among the multiple low-side MOSFETs 21, the angle between the elongation direction of the second bonding lead 46, which connects to the second source electrode 21a of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction, and the second direction is 20 degrees or less. That is, in Figure 1 In the multiple low-side MOSFETs 21, the angle between the elongation direction of the second junction line 46, which is connected to the second source electrode 21a of the lowest low-side MOSFET 21, and the second direction is less than 20 degrees.

[0069] The angle between the extension direction of the second bonding line 46 and a third direction is 70 degrees or more and 90 degrees or less. For example, when a low-side MOSFET 21 is connected to multiple second bonding lines 46, the angle between the extension direction of at least one of the multiple second bonding lines 46 and a third direction is 70 degrees or more and 90 degrees or less. The angle between the extension direction of the second bonding line 46 connected to any one of the multiple low-side MOSFETs 21 and a third direction is 70 degrees or more and 90 degrees or less.

[0070] Furthermore, the elongation direction of the so-called second bonding line 46 is, for example, the direction of the line segment connecting the position where the second bonding line 46 is connected to the second source electrode 21a and the position where the second bonding line 46 is connected to the second metal layer 32.

[0071] For example, the angle between the elongation direction and the second direction of all the second bonding lines 46 in the semiconductor module 100 is less than 20 degrees. Figure 1 The diagram shows the case where the angle between the extension direction of all the second bonding lines 46 of the semiconductor module 100 and the second direction is 0 degrees.

[0072] For example, among the plurality of low-side MOSFETs 21, a second metal layer 32 exists in the second direction of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction. That is, in Figure 1 In the middle, among the multiple low-side MOSFETs 21, a second metal layer 32 is present in the second direction of the low-side MOSFET 21 located at the bottommost side.

[0073] For example, among a plurality of low-side MOSFETs 21, the junction of the second source electrode 21a and the second junction line 46 of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction ( Figure 1 A second metal layer 32 exists in the second direction of C1 and C2. For example, among a plurality of low-side MOSFETs 21, the contact between the second source electrode 21a and the second junction line 46 of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction is the contact closest to the first metal layer 31 ( Figure 1 A second metal layer 32 exists in the second direction of C2).

[0074] For example, at the end of the lower-side MOSFET 21 closest to the first metal layer 31 in the first direction (closest to the first metal layer 31) Figure 1 In E1), a second metal layer 32 exists in the second direction.

[0075] For example, the first distance in the first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side ( Figure 1 d1 in the first direction is greater than the second distance in the first direction between the end of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction and the end of the second metal layer 32 on the side of the first metal layer 31. Figure 1 d2) is large.

[0076] For example, the first distance in the first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side ( Figure 1 d1 in the first direction is greater than the third distance in the first direction between the second connection region 32x and the opposite end of the first metal layer 31 of the second metal layer 32. Figure 1 d3) in .

[0077] Next, the function and effects of the semiconductor device in the implementation method will be explained.

[0078] Vertical MOSFETs using silicon carbide have a pn junction diode as the body diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, return current can flow through by using the body diode.

[0079] However, if a body diode is used to carry the return current, there is a problem that stacking defects can grow in the silicon carbide layer due to the recombination energy of charge carriers, leading to an increase in the on-resistance of the MOSFET. The increase in the on-resistance of the MOSFET results in a decrease in its reliability.

[0080] There are MOSFETs with a built-in unipolar Schottky barrier diode (SBD). Instead of a bipolar pn junction diode, the SBD is used to flow the return current, thereby suppressing the growth of stack-up defects and improving the reliability of the MOSFET.

[0081] In power semiconductor modules containing multiple MOSFETs with built-in SBDs, it is also important to suppress the operation of the pn junction diodes of each MOSFET from the viewpoint of improving the reliability of the power semiconductor module.

[0082] Figure 4 This is a schematic top view of a comparative example semiconductor device. The comparative example semiconductor device is a power semiconductor module 900. The equivalent circuit diagram of the power semiconductor module 900 is shown below. Figure 3 same.

[0083] Power semiconductor module 900 Figure 4As shown, the difference from the power semiconductor module 100 of the embodiment is that the first direction in which the plurality of high-side MOSFETs 11 are arranged is perpendicular to the third direction. Additionally, the difference from the power semiconductor module 100 of the embodiment is that the first direction in which the plurality of low-side MOSFETs 21 are arranged is perpendicular to the third direction. The third direction is the direction connecting the first connection region 31x and the second connection region 32x.

[0084] In addition, power semiconductor module 900, such as Figure 4 As shown, the difference between this embodiment and the power semiconductor module 100 is that the extension direction of the first bonding line 44 is parallel to the angle formed by the third direction. Additionally, the power semiconductor module 900 is as follows... Figure 4 As shown, the difference from the power semiconductor module 100 of the embodiment is that the extension direction of the second bonding line 46 is parallel to the angle formed by the third direction.

[0085] It is known that during the switching operation of the power semiconductor module 900, the current flowing through the diodes included in the multiple high-side MOSFETs 11 or the diodes included in the multiple low-side MOSFETs 21 deviates. It is known that if the deviation of the current flowing through the diodes becomes large, there is a possibility that the pn-junction diode may operate due to the current exceeding the amount flowing through the Schottky barrier diode.

[0086] Figure 5 This is an illustration of the problem points of a comparative example semiconductor device. Figure 5 This is a schematic top view of the power semiconductor module 900.

[0087] exist Figure 5 In the diagram, dashed arrows represent the three paths from the positive terminal P through the MOSFET to the negative terminal N: path X9, path Y9, and path Z9. Paths X9, Y9, and Z9 are the paths from the first connection region 31x to the second connection region 32x.

[0088] The inventors' research results clarified that the deviation of the current flowing through the diode during the switching action of the power semiconductor module 900 depends on the deviation of the lengths of path X9, path Y9, and path Z9.

[0089] For example, among the three paths, path X9 is the shortest path, and path Z9 is the longest path. The MOSFET diode in path X9, which is the shortest path, carries the largest current. Conversely, the MOSFET diode in path Z9, which is the longest path, carries the smallest current.

[0090] For example, consider a scenario where the power semiconductor module 900 is connected to an external inductive load, multiple high-side MOSFETs 11 are in the off state, and multiple low-side MOSFETs 21 are in the on state, with current flowing through them. From this state, the multiple high-side MOSFETs 11 are switched to the on state, and the multiple low-side MOSFETs 21 are switched to the off state. At this time, the multiple low-side MOSFETs 21 become reverse-biased, and the return current flows through the diodes built into the low-side MOSFETs 21.

[0091] At this point, the current flowing through the diode of the low-side MOSFET 21, which exists in path X9 (the shortest path), is the largest. Conversely, the current flowing through the diode of the low-side MOSFET 21, which exists in path Z9 (the longest path), is the smallest.

[0092] If the return current flowing through the diode of the low-side MOSFET 21 present in path X9 exceeds the allowable current range of the second Schottky barrier diode 21y included in the low-side MOSFET 21, the pn junction diode will operate. When the pn junction diode operates, the reliability of the low-side MOSFET 21 present in path X9 is reduced. Furthermore, the reliability of the power semiconductor module 900 is reduced.

[0093] Figure 6 This is an explanatory diagram illustrating the function and effects of the semiconductor device in the implementation method. Figure 6 This is a schematic top view of the power semiconductor module 100.

[0094] exist Figure 6 In the diagram, dashed arrows represent three paths from the positive terminal P through the MOSFET to the negative terminal N: path X1, path Y1, and path Z1. Paths X1, Y1, and Z1 are paths from the first connection region 31x to the second connection region 32x.

[0095] The power semiconductor module 100 of the first embodiment, compared with the power semiconductor module 900 of the comparative example, suppresses the deviation in the length of path X1, path Y1 and path Z1 by changing the arrangement direction of MOSFETs and the extension direction of the bonding wires.

[0096] Specifically, a plurality of high-side MOSFETs 11 are arranged along a third direction connecting the first connection region 31x and the second connection region 32x. A plurality of low-side MOSFETs 21 are also arranged along a third direction. The angle between the third direction and the first direction in which the plurality of high-side MOSFETs 11 and the plurality of low-side MOSFETs 21 are arranged is less than 20 degrees.

[0097] Furthermore, the angle between the elongation direction of the first joining line 44 and the second direction is 20 degrees or less. The angle between the elongation direction of the second joining line 46 and the second direction is 20 degrees or less.

[0098] The power semiconductor module 100 of the embodiment, through the above-described structure, suppresses deviations in the lengths of paths X1, Y1, and Z1. Therefore, deviations in the current flowing through the diodes during the switching operation of the power semiconductor module 100 are suppressed. Therefore, the operation of the pn junction diode included in the MOSFET is suppressed. Therefore, the reliability of the power semiconductor module 100 is improved.

[0099] The angle between the third direction and the first direction in which the plurality of high-side MOSFETs 11 and the plurality of low-side MOSFETs 21 are arranged is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degrees. By reducing the above angle, deviations in the lengths of path X1, path Y1, and path Z1 can be further suppressed.

[0100] Furthermore, the angle between the extension direction of all the first bonding lines 44 of the semiconductor module 100 and the second direction is preferably 20 degrees or less. Additionally, the angle between the extension direction of all the second bonding lines 46 of the semiconductor module 100 and the second direction is preferably 20 degrees or less. With the above structure, deviations in the lengths of paths X1, Y1, and Z1 can be further suppressed.

[0101] Furthermore, the angle between the extension direction of the first joining line 44 and the second direction is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degrees. The angle between the extension direction of the second joining line 46 and the second direction is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degrees. By reducing the above angles, deviations in the lengths of paths X1, Y1, and Z1 can be further suppressed.

[0102] Preferably, a second metal layer 32 exists in the second direction of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the plurality of low-side MOSFETs 21. That is, in Figure 1 Preferably, a second metal layer 32 is present in the second direction of the lowest-side MOSFET 21 among the plurality of low-side MOSFETs 21. With the above structure, deviations in the lengths of paths X1, Y1, and Z1 can be further suppressed.

[0103] Preferably, among the plurality of low-side MOSFETs 21, the junction of the second source electrode 21a and the second junction line 46 of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction is ( Figure 1A second metal layer 32 exists in the second direction of C1 and C2. Preferably, among the plurality of low-side MOSFETs 21, the junction of the second source electrode 21a and the second junction line 46 of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction is the junction closest to the first metal layer 31. Figure 1 A second metal layer 32 exists in the second direction of C2. With the above structure, deviations in the lengths of paths X1, Y1, and Z1 can be further suppressed.

[0104] Preferably, among the plurality of low-side MOSFETs 21, the end of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction is near the first metal layer 31. Figure 1 A second metal layer 32 exists in the second direction of E1. With the above structure, deviations in the lengths of path X1, path Y1, and path Z1 can be further suppressed.

[0105] The first distance in the first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side ( Figure 1 d1) is preferably greater than the second distance in the first direction between the end of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction and the end of the second metal layer 32 on the side of the first metal layer 31. Figure 1 (d2 in the above structure). Through the above structure, the deviations in the lengths of path X1, path Y1, and path Z1 can be further suppressed.

[0106] The first distance in the first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side ( Figure 1 The distance d1 in the first direction is preferably greater than the third distance in the first direction between the second connection region 32x and the end opposite to the first metal layer 31 of the second metal layer 32. Figure 1 (d3 in the above structure). Through the above structure, the deviations in the lengths of path X1, path Y1, and path Z1 can be further suppressed.

[0107] In this implementation, the example is given with three power semiconductor chips arranged in parallel, but there can be two or more power semiconductor chips.

[0108] In this implementation, the example is a "2in1" type power semiconductor module, but the power semiconductor module may also be a "4in1" type or a "6in1" type, or other circuit structures.

[0109] The first and second connecting lines can be either linear or strip-shaped bonding wires. Furthermore, as long as they have electrical connection functionality, the first and second connecting lines can also be, for example, plate-shaped conductors.

[0110] In this embodiment, the case in which a portion of a terminal such as the positive terminal P is directly connected to the metal layer is described as an example, but for example, a bonding wire can also be used to connect the terminal to the metal layer.

[0111] In this embodiment, the example is described with the positive terminal, negative terminal, and AC output terminal all located at the same end of the power semiconductor module. However, the configuration of the positive terminal, negative terminal, and AC output terminal is not limited to the above configuration.

[0112] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: Insulating substrate; First main terminal; Second main terminal; Output terminals; A first metal layer is disposed on the insulating substrate and has a first connection area, which is electrically connected to the first main terminal. A second metal layer is disposed on the insulating substrate and has a second connection area, which is electrically connected to the second main terminal. A third metal layer is disposed on the insulating substrate, located between the first metal layer and the second metal layer, and has a third connection area, which is electrically connected to the output terminal. A plurality of first semiconductor chips, including a first upper electrode, a first lower electrode, a first gate electrode and a first silicon carbide layer, including a first Schottky barrier diode, wherein the first lower electrode is electrically connected to the first metal layer, and the plurality of first semiconductor chips are arranged in a first direction; A plurality of second semiconductor chips, including a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, including a second Schottky barrier diode, wherein the second lower electrode is electrically connected to the third metal layer, and the plurality of second semiconductor chips are arranged in the first direction; The first connecting line electrically connects the first upper electrode to the third metal layer; The second connecting line electrically connects the second upper electrode to the second metal layer; A fourth metal layer is disposed on the insulating substrate, between the first metal layer and the third metal layer, and electrically connected to the first gate electrode; as well as A fifth metal layer is disposed on the insulating substrate, between the second metal layer and the third metal layer, and is electrically connected to the second gate electrode. The second semiconductor chip exists in a second direction that is perpendicular to the first direction and parallel to the insulating substrate. The angle between the third direction connecting the first connection area and the second connection area and the first direction is less than 20 degrees. Among the plurality of second semiconductor chips, the angle between the elongation direction of the second connecting line of the second semiconductor chip closest to the first metal layer in the first direction and the second upper electrode is less than 20 degrees.

2. The semiconductor device according to claim 1, wherein, In the second direction of the second semiconductor chip that is closest to the first metal layer in the first direction among a plurality of second semiconductor chips, the second metal layer exists.

3. The semiconductor device according to claim 1 or 2, wherein, In one of the plurality of second semiconductor chips, the second metal layer is present in the second direction of the junction of the second upper electrode and the second connecting line of the second semiconductor chip closest to the first metal layer in the first direction.

4. The semiconductor device according to claim 1 or 2, wherein, In one of the plurality of second semiconductor chips, the second metal layer is present in the second direction at the end of the second semiconductor chip closest to the first metal layer in the first direction, on the side closer to the first metal layer.

5. The semiconductor device according to claim 1 or 2, wherein, The first distance in the first direction between the second connection region and the end of the second metal layer on the first metal layer side is greater than the second distance between the end of the second semiconductor chip that is closest to the first metal layer in the first direction and the end of the second metal layer on the first metal layer side of the second metal layer.

6. The semiconductor device according to claim 1 or 2, wherein, The first distance in the first direction between the second connection region and the end of the second metal layer on the first metal layer side is greater than the third distance in the first direction between the second connection region and the end of the second metal layer on the opposite side of the first metal layer.

7. The semiconductor device according to claim 1 or 2, wherein, The angle between the extension direction of the first connecting line and the second direction is less than 20 degrees.

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