Nitride semiconductor devices

Abstract

An embodiment provides a nitride semiconductor device capable of improving operational stability. The nitride semiconductor device of this embodiment includes: a conductive substrate; a nitride semiconductor layer disposed on the substrate; a first electrode disposed on and connected to the nitride semiconductor layer; a second electrode disposed on and connected to the nitride semiconductor layer; a first control electrode disposed on the nitride semiconductor layer and positioned between the first electrode and the second electrode when viewed from above; a protective ring disposed on the nitride semiconductor layer and surrounding the region where the first electrode, the second electrode, and the first control electrode are disposed, forming a first capacitor between the protective ring and the first electrode, and a second capacitor between the protective ring and the second electrode; and a connecting member connecting the protective ring to the substrate.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-152133 (filed on September 17, 2021). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation methods relate to nitride semiconductor devices. Background Technology

[0004] In recent years, nitride semiconductor devices have been developed as switching devices for controlling current. Compared with silicon (Si), nitride semiconductors such as gallium nitride (GaN) have higher carrier density and electron mobility, thus offering the potential to realize highly efficient switching devices. In nitride semiconductor devices, improving operational stability is a key requirement. Summary of the Invention

[0005] The embodiment provides a nitride semiconductor device that can improve the stability of operation.

[0006] A nitride semiconductor device according to an embodiment includes: a conductive substrate; a nitride semiconductor layer disposed on the substrate; a first electrode disposed on and connected to the nitride semiconductor layer; a second electrode disposed on and connected to the nitride semiconductor layer; a first control electrode disposed on the nitride semiconductor layer and positioned between the first electrode and the second electrode when viewed from above; a protective ring disposed on the nitride semiconductor layer and surrounding the region where the first electrode, the second electrode, and the first control electrode are disposed, wherein a first capacitor is formed between the protective ring and the first electrode, and a second capacitor is formed between the protective ring and the second electrode; and a connecting member connecting the protective ring to the substrate. Attached Figure Description

[0007] Figure 1 This is a top view showing the nitride semiconductor device of the first embodiment.

[0008] Figure 2 (a) is Figure 1 The cross-sectional view of line A-A' shown. Figure 2 (b) is Figure 1 The cross-sectional view of line B-B' shown. Figure 2 (c) is Figure 1 The cross-sectional view of the C-C' line shown.

[0009] Figure 3This is a diagram schematically showing the connection relationships of various parts in the nitride semiconductor device of the first embodiment.

[0010] Figure 4 This is a top view showing the nitride semiconductor device according to the second embodiment.

[0011] Figure 5 yes Figure 4 The cross-sectional view of line D-D' shown.

[0012] Figure 6 This is a top view showing the nitride semiconductor device according to the third embodiment.

[0013] Figure 7 This is a diagram schematically showing the connection relationships of various parts in the nitride semiconductor device of the third embodiment.

[0014] Figure 8 This is a top view showing the nitride semiconductor device according to the fourth embodiment.

[0015] Figure 9 yes Figure 8 The cross-sectional view of the E-E' line shown. Detailed Implementation

[0016] <First Implementation>

[0017] Figure 1 This is a top view showing the nitride semiconductor device of this embodiment.

[0018] Figure 2 (a) is Figure 1 The cross-sectional view of line A-A' shown. Figure 2 (b) is Figure 1 The cross-sectional view of line B-B' shown. Figure 2 (c) is Figure 1 The cross-sectional view of the C-C' line shown.

[0019] The nitride semiconductor device 1 in this embodiment is, for example, a switching element for current control, such as a one-way switch.

[0020] like Figure 1 , Figure 2 As shown in (a) to (c), the nitride semiconductor device 1 of this embodiment includes a substrate 10, a nitride semiconductor layer 20, an insulating film 30, a source pad 40 (first pad), a drain pad 50 (second pad), a gate pad 60, a source electrode 46 (first electrode), a drain electrode 56 (second electrode), a gate electrode 66 (first control electrode), a guard ring 70, a first capacitor electrode 71, a second capacitor electrode 72, wiring 80, and a through hole 81.

[0021] The substrate 10 is, for example, a rectangular plate. When viewed from above, the substrate 10 is disposed over the entire nitride semiconductor device 1. The substrate 10 is conductive, for example, made of single-crystal silicon.

[0022] For ease of explanation, an XYZ orthogonal coordinate system is used in this specification. The two directions parallel and orthogonal to the main surface of the substrate 10 are designated as the "X direction" and the "Y direction," and the direction perpendicular to the main surface of the substrate 10 is designated as the "Z direction." The direction in the Z direction from the substrate 10 towards the nitride semiconductor layer 20 is also called "up," and its opposite direction is called "down," but this designation is for convenience and is independent of the direction of gravity. The nitride semiconductor layer 20 is disposed on the substrate 10, for example, in contact with the substrate 10.

[0023] The nitride semiconductor layer 20 is made of, for example, gallium nitride (GaN) or aluminum gallium nitride (AlGaN). For example, in the nitride semiconductor layer 20, an AlGaN layer is stacked on top of the GaN layer. In this case, the nitride semiconductor layer 20 contains gallium (Ga), aluminum (Al), and nitrogen (N).

[0024] When viewed from above, the outer edge of the nitride semiconductor layer 20 is located inside the outer edge of the substrate 10. Therefore, the outer periphery of the substrate 10 is not covered by the nitride semiconductor layer 20. In other words, the area directly above the outer periphery of the substrate 10 is the opening of the nitride semiconductor layer 20. When viewed from above, this opening surrounds the nitride semiconductor layer 20.

[0025] An insulating film 30 is disposed on the nitride semiconductor layer 20, covering substantially the entire nitride semiconductor layer 20. The insulating film 30 is formed of an insulating material, such as silicon nitride (SiN). Source pads 40, drain pads 50, gate pads 60, and wiring 80 are disposed on the insulating film 30.

[0026] like Figure 1 As shown, when viewed from above, a cell region Rc is provided in the central part of the nitride semiconductor device 1. The cell region Rc is an active region through which source and drain currents flow. Source pads 40, drain pads 50, gate pads 60, and wiring 80 are disposed outside the cell region Rc.

[0027] exist Figure 1 In the example shown, when viewed from the cell region Rc, the source pad 40 and the gate pad 60 are positioned on one side of the cell region Rc in the Y direction, and the drain pad 50 is positioned on the other side of the cell region Rc in the Y direction. The source pad 40 and the gate pad 60 are arranged along the X direction.

[0028] For example, four wirings 80 are provided, respectively positioned on both sides of the X-direction and both sides of the Y-direction when viewed from the cell region Rc. Each wiring 80 is configured to pass over the stepped portion of the insulating film 30 and the nitride semiconductor layer 20 and reach the upper surface of the substrate 10 from the upper surface of the insulating film 30. However, the planar layout of the pads and wirings 80 is not limited to... Figure 1 The example shown illustrates this. For instance, the gate pad 60 can also be arranged side-by-side with the drain pad 50. Furthermore, the number of wirings 80 is not limited to four; it can be three or fewer, or five or more. When multiple wirings 80 are provided, the widths of the wirings 80 can be the same or different.

[0029] like Figure 1 , Figure 2 As shown in (a) to (c), the source electrode 46, drain electrode 56, gate electrode 66, guard ring 70, first capacitor electrode 71, and second capacitor electrode 72 are disposed on the nitride semiconductor layer 20 and covered by the insulating film 30. The source electrode 46 is connected to the source pad 40, the drain electrode 56 is connected to the drain pad 50, and the gate electrode 66 is connected to the gate pad 60. In this specification, "connection" refers to electrical connection.

[0030] Source electrode 46, drain electrode 56, and gate electrode 66 are disposed inside the cell region Rc, and multiple of them are provided. For example, the source electrode 46, drain electrode 56, and gate electrode 66 are linear in shape extending along the Y direction. In the cell region Rc, the source electrode 46 and drain electrode 56 are arranged alternately along the X direction, and when viewed from above, the gate electrode 66 is disposed between adjacent source electrode 46 and drain electrode 56.

[0031] like Figure 2 As shown in (a), the source electrode 46 and the drain electrode 56 are connected to the upper surface of the nitride semiconductor layer 20. The gate electrode 66 is isolated from the nitride semiconductor layer 20 by a portion of the insulating film 30. The gate electrode 66 is disposed near the source electrode 46. That is, the distance between the source electrode 46 and the gate electrode 66 is shorter than the distance between the drain electrode 56 and the gate electrode 66.

[0032] like Figure 1 as well as Figure 2 As shown in (b), the guard ring 70, the first capacitor electrode 71, and the second capacitor electrode 72 are disposed outside the unit region Rc, for example, each is provided. The guard ring 70, the first capacitor electrode 71, and the second capacitor electrode 72 can be connected to the nitride semiconductor layer 20, or they can be isolated from the nitride semiconductor layer 20 through a portion of the insulating film 30.

[0033] Viewed from above, the guard ring 70 is frame-shaped, enclosing the area including the cell region Rc, the source pad 40, the drain pad 50, and the gate pad 60. The first capacitor electrode 71 and the second capacitor electrode 72 are connected to the guard ring 70 and extend from the guard ring 70 toward the inside of the guard ring 70.

[0034] The first capacitor electrode 71 is, for example, plate-shaped. The first capacitor electrode 71 is disposed on the nitride semiconductor layer 20 and directly below the source pad 40. When viewed from above, a portion of the source pad 40 overlaps with a portion of the first capacitor electrode 71. Thus, a portion of the source pad 40 is positioned opposite a portion of the first capacitor electrode 71 through a portion of the insulating film 30, forming a first capacitor C1 between the source pad 40 and the first capacitor electrode 71.

[0035] Similarly, the second capacitor electrode 72 is, for example, plate-shaped. The second capacitor electrode 72 is disposed on the nitride semiconductor layer 20 and directly below the drain pad 50. When viewed from above, a portion of the drain pad 50 overlaps with a portion of the second capacitor electrode 72. Thus, a portion of the drain pad 50 is positioned opposite a portion of the second capacitor electrode 72 through a portion of the insulating film 30, forming a second capacitor C2 between the drain pad 50 and the second capacitor electrode 72.

[0036] Preferably, the capacitance of the first capacitor C1 is equal to the capacitance of the second capacitor C2. Furthermore, "equal" means equal in design value; for example, even if there are differences caused by manufacturing process errors or by parasitic capacitance with surrounding conductive parts, as long as the design value is equal, it is included in "equal".

[0037] like Figure 2 As shown in (c), one end of the wiring 80 is disposed on the insulating film 30, and the through-hole 81 is disposed within the insulating film 30. One end of the wiring 80 is connected to the protective ring 70 via the through-hole 81. The other end of the wiring 80 is disposed on the outer periphery of the substrate 10, i.e., the opening of the nitride semiconductor layer 20, and is connected to the substrate 10. Thus, the protective ring 70 is connected to the substrate 10 via the through-hole 81 and the wiring 80. The through-hole 81 and the wiring 80 form a connecting member that connects the protective ring 70 to the substrate 10.

[0038] Next, the operation of the nitride semiconductor device 1 in this embodiment will be explained.

[0039] Figure 3 This diagram schematically illustrates the connection relationships of various parts in the nitride semiconductor device of this embodiment.

[0040] like Figure 1As shown, in the nitride semiconductor device 1, a first capacitor C1 is formed between the source pad 40 and the first capacitor electrode 71. The source pad 40 is connected to the source electrode 46, and the first capacitor electrode 71 is connected to the substrate 10 via a guard ring 70, a through-hole 81, and wiring 80. Therefore, as Figure 3 As shown, the first capacitor C1 is formed between the source electrode 46 and the substrate 10.

[0041] Similarly, as Figure 1 as well as Figure 2 As shown in (b), in the nitride semiconductor device 1, a second capacitor C2 is formed between the drain pad 50 and the second capacitor electrode 72. The drain pad 50 is connected to the drain electrode 56, and the second capacitor electrode 72 is connected to the substrate 10 via a guard ring 70, a via 81, and wiring 80. Therefore, as Figure 3 As shown, the second capacitor C2 is formed between the drain electrode 56 and the substrate 10.

[0042] Thus, substrate 10 is capacitively coupled to source electrode 46 via first capacitor C1, and capacitively coupled to drain electrode 56 via second capacitor C2. Consequently, the potential of substrate 10 becomes an intermediate potential between the potential of source electrode 46 and drain electrode 56. For example, Figure 3 As shown, the first capacitor C1 has the same size as the second capacitor C2. When the source pad 40 is applied with a ground potential GND and the drain pad 50 is applied with a power supply potential VDD, the potential of the substrate 10 is approximately (VDD / 2). Furthermore, if the potential of the source electrode 46 and the drain electrode 56 changes, the potential of the substrate 10 will also change accordingly.

[0043] Next, the effects of this implementation method will be explained.

[0044] In this embodiment, the potential of the substrate 10 can be made to be an intermediate potential between the potential of the source electrode 46 and the potential of the drain electrode 56. As a result, the potential of the substrate 10 can be stabilized, thereby stabilizing the operation of the nitride semiconductor device 1.

[0045] Furthermore, within the nitride semiconductor layer 20, electric field concentration can be suppressed, and the electric field intensity can be dispersed. As a result, the withstand voltage of the nitride semiconductor device 1 can be improved. At this time, by making the size of the first capacitor C1 equal to the size of the second capacitor C2, the potential difference between the substrate 10 and the source electrode 46 and the potential difference between the substrate 10 and the drain electrode 56 can be made approximately equal. Thus, the electric field intensity can be dispersed more effectively.

[0046] Furthermore, assuming that the substrate 10 is in a floating state without the first capacitor C1 and the second capacitor C2, the potential of the substrate 10 will change over time as the nitride semiconductor device 1 operates, potentially leading to instability in the operation of the nitride semiconductor device 1. Additionally, if the substrate 10 is connected to ground potential GND, its potential will be stable, but the electric field will be concentrated in the portion of the nitride semiconductor layer 20 located between the substrate 10 and the drain electrode 56, potentially resulting in a decrease in withstand voltage. To ensure withstand voltage in this state, the nitride semiconductor layer 20 must be thickened, increasing costs.

[0047] <Second Implementation>

[0048] Figure 4 This is a top view showing the nitride semiconductor device of this embodiment.

[0049] Figure 5 yes Figure 4 The cross-sectional view of line D-D' shown.

[0050] like Figure 4 as well as Figure 5 As shown, in the nitride semiconductor device 2 of this embodiment, when viewed from above, the outer edge of the insulating film 30 and the outer edge of the nitride semiconductor layer 20 are roughly aligned with the outer edge of the substrate 10, and the outer periphery of the nitride semiconductor layer 20 is not exposed.

[0051] Through-holes 21 are formed in the insulating film 30 and the nitride semiconductor layer 20. The portion of the through-hole 21 located within the nitride semiconductor layer 20 is an opening of the nitride semiconductor layer 20. A via 82 is formed within the through-hole 21. The lower end of the via 82 is connected to the substrate 10, and the upper end is connected to the wiring 80.

[0052] Thus, the protective ring 70 is connected to the substrate 10 via the through hole 81, the wiring 80, and the through hole 82. In this embodiment, the through hole 81, the wiring 80, and the through hole 82 form a connecting member for connecting the protective ring 70 to the substrate 10.

[0053] The configuration, operation, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0054] <Third Implementation Method>

[0055] Figure 6 This is a top view showing the nitride semiconductor device of this embodiment.

[0056] Figure 7 This diagram schematically illustrates the connection relationships of various parts in the nitride semiconductor device of this embodiment.

[0057] like Figure 6As shown, in the nitride semiconductor device 3 of this embodiment, in addition to the configuration of the nitride semiconductor device 1 of the first embodiment, a first resistor 91 and a second resistor 92 are also provided. The first resistor 91 is connected between the source pad 40 and the guard ring 70. The second resistor 92 is connected between the drain pad 50 and the guard ring 70.

[0058] The first resistor 91 and the second resistor 92 are components made of a conductive material with a resistivity higher than that of the guard ring 70, such as components formed of polycrystalline silicon. The first resistor 91 forms the first resistor R1, and the second resistor 92 forms the second resistor R2. Preferably, the first resistor R1 and the second resistor R2 are equal. Furthermore, as described above, "equal" means equal in design values.

[0059] Therefore, as Figure 7 As shown, in the nitride semiconductor device 3, a first resistor R1 is connected in parallel with a first capacitor C1 between the source pad 40 and the substrate 10. Additionally, a second resistor R2 is connected in parallel with a second capacitor C2 between the drain pad 50 and the substrate 10.

[0060] According to this embodiment, the substrate 10 is capacitively coupled to the source electrode 46 via a first capacitor C1, capacitively coupled to the drain electrode 56 via a second capacitor C2, and connected to the source electrode 46 via a first resistor R1 and to the drain electrode 56 via a second resistor R2. This allows for further stabilization of the potential of the substrate 10. Furthermore, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2, leakage current flowing between the source pad 40 and the drain pad 50 can be suppressed.

[0061] The configuration, operation, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0062] <Fourth Implementation>

[0063] Figure 8 This is a top view showing the nitride semiconductor device of this embodiment.

[0064] Figure 9 yes Figure 8 The cross-sectional view of the E-E' line shown.

[0065] like Figure 8 as well as Figure 9 As shown, in the nitride semiconductor device 4 of this embodiment, in addition to the configuration of the nitride semiconductor device 3 of the third embodiment, a gate pad 61 and a gate electrode 66 (second control electrode) are also provided. The gate pad 61 is connected to the gate electrode 67.

[0066] Furthermore, in the nitride semiconductor device 4, compared to the nitride semiconductor device 3 of the third embodiment, a source pad 41 is provided instead of the drain pad 50, and a source electrode 47 is provided instead of the drain electrode 56. The source pad 41 is connected to the source electrode 47. In the nitride semiconductor device 4, a second capacitor C2 is formed between the source pad 41 and the second capacitor electrode 72.

[0067] like Figure 8 As shown, the gate pad 61 and the source pad 41 are arranged along the X direction on the insulating film 30. Additionally, as... Figure 9 As shown, the source electrode 47 is connected to the nitride semiconductor layer 20, and the gate electrode 67 is isolated from the nitride semiconductor layer 20 through a portion of the insulating film 30.

[0068] Viewed from above, gate electrode 66 and gate electrode 67 are disposed between source electrode 46 and source electrode 47. Gate electrode 66 is disposed near source electrode 46, and gate electrode 67 is disposed near source electrode 47. That is, gate electrode 66 is disposed between gate electrode 67 and source electrode 46, and gate electrode 67 is disposed between gate electrode 66 and source electrode 47.

[0069] In the nitride semiconductor device 4 of this embodiment, two gate electrodes 66 and 67 are disposed between the two source electrodes 46 and 47. Furthermore, the current flowing from the source electrode 46 to the source electrode 47 is controlled by the gate electrode 67, and the current flowing from the source electrode 47 to the source electrode 46 is controlled by the gate electrode 66. Thus, the nitride semiconductor device 4 can be used as an integrated bidirectional switch.

[0070] According to this embodiment, the potential of the substrate 10 and the guard ring 70 can be made to be an intermediate potential between the potential of the source electrode 46 and the potential of the source electrode 47. Therefore, the same characteristics can be achieved both when current flows from the source electrode 46 to the source electrode 47 and when current flows from the source electrode 47 to the source electrode 46. As a result, the stability of operation is improved when the nitride semiconductor device 4 is used as a bidirectional switch.

[0071] The configurations, operations, and effects in this embodiment other than those described above are the same as in the third embodiment.

[0072] According to the embodiments described above, a nitride semiconductor device that can improve the stability of operation can be realized.

[0073] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention and its equivalents as described in the claims. Furthermore, the foregoing embodiments can also be combined with each other.

[0074] For example, in the embodiments described above, examples are shown where the nitride semiconductor layer 20 is formed of GaN or AlGaN, but the present invention is not limited to this. Furthermore, multiple guard rings 70, first capacitor electrodes 71, and second capacitor electrodes 72 may be provided respectively. Moreover, in the embodiments described above, examples are shown where a first capacitor C1 is formed by the source pad 40 and the first capacitor electrode 71, and a second capacitor C2 is formed by the drain pad 50 and the second capacitor electrode 72, but the methods for forming the first capacitor C1 and the second capacitor C2 are not limited to this.

Claims

1. A nitride semiconductor device comprising: Conductive substrate; A nitride semiconductor layer is disposed on the substrate; The first electrode is disposed on the nitride semiconductor layer and connected to the nitride semiconductor layer; The second electrode is disposed on the nitride semiconductor layer and connected to the nitride semiconductor layer; A first control electrode is disposed on the nitride semiconductor layer and, when viewed from above, is located between the first electrode and the second electrode; A protective ring is disposed on the nitride semiconductor layer and around the region where the first electrode, the second electrode and the first control electrode are disposed. A first capacitor is formed between the protective ring and the first electrode, and a second capacitor is formed between the protective ring and the second electrode. as well as A connecting component connects the protective ring to the substrate.

2. The nitride semiconductor device according to claim 1, It also includes a second control electrode, which is disposed on the nitride semiconductor layer and, when viewed from above, is located between the first control electrode and the second electrode.

3. The nitride semiconductor device according to claim 1 or 2, further comprising: An insulating film is disposed on the nitride semiconductor layer, covering the first electrode, the second electrode, and the first control electrode; The first pad is disposed on the insulating film and connected to the first electrode; The second pad is disposed on the insulating film and connected to the second electrode; The first capacitor electrode is connected to the protective ring and is positioned directly below the first pad, facing the first pad through a portion of the insulating film; as well as The second capacitor electrode is connected to the guard ring and positioned directly below the second pad, opposite the second pad across a portion of the insulating film. The first capacitor is formed between the first pad and the first capacitor electrode, and the second capacitor is formed between the second pad and the second capacitor electrode.

4. The nitride semiconductor device according to claim 1 or 2, An opening is formed in the nitride semiconductor layer. The connecting component is connected to the substrate via the opening.

5. The nitride semiconductor device according to claim 4, When viewed from above, the opening surrounds the nitride semiconductor layer.

6. The nitride semiconductor device according to claim 1 or 2, further comprising: A first resistive element is connected between the first electrode and the protective ring; and The second resistor is connected between the second electrode and the guard ring.

7. The nitride semiconductor device according to claim 1 or 2, The size of the first capacitor is equal to the size of the second capacitor.

8. The nitride semiconductor device according to claim 1 or 2, The nitride semiconductor layer comprises gallium and nitrogen.

9. A nitride semiconductor device comprising: Conductive substrate; A nitride semiconductor layer is disposed on the substrate; The first electrode is disposed on the nitride semiconductor layer and electrically connected to the nitride semiconductor layer; The second electrode is disposed on the nitride semiconductor layer and electrically connected to the nitride semiconductor layer; A first control electrode is disposed on the nitride semiconductor layer and, when viewed from above, is located between the first electrode and the second electrode; A protective ring is disposed on the nitride semiconductor layer and around the region where the first electrode, the second electrode, and the first control electrode are disposed; A connecting component connects the protective ring to the substrate; An electrode, connected to the protective ring, extends from the protective ring toward the inside of the protective ring when viewed from above; An insulating film is disposed on the nitride semiconductor layer, covering the first electrode, the second electrode, and the first control electrode; as well as The first pad is located on the insulating film and connected to the first electrode. The electrode is positioned directly below the first pad, opposite the first pad through a portion of the insulating film.

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