Low-temperature polysilicon array substrate, manufacturing method thereof and display panel

Abstract

The application discloses a low-temperature polysilicon array substrate, a manufacturing method thereof and a display panel. The low-temperature polysilicon array substrate comprises a transparent base material, a thin film transistor, a light shielding layer, a barrier layer, a polysilicon layer, an n+ ion implantation layer, a pixel electrode layer, a data line layer, an insulating layer, a scanning line layer, a protective layer and a common electrode layer. The array substrate of the application removes a plurality of vias in the pixel area, saves a large amount of space and improves the pixel aperture ratio. The display panel of the application is used to manufacture a VR product, and the PPI can be improved to 1000+. The manufacturing method of the application saves two mask plates for forming a bridging hole and an organic insulating layer compared with a traditional process, saves a layer of silicon nitride protective layer and an organic insulating layer in a process, improves the efficiency, and saves the cost.

Description

Technical Field

[0001] This invention relates to the field of thin-film transistor manufacturing, and particularly to a low-temperature polycrystalline silicon array substrate and its manufacturing method, as well as a display panel. Background Technology

[0002] Low-temperature poly-silicon (LTPS) thin-film transistor liquid crystal displays differ from traditional amorphous silicon thin-film transistor liquid crystal displays. They can effectively reduce the area of ​​thin-film transistor devices, thereby increasing display brightness while reducing overall power consumption.

[0003] As display quality requirements increase, a higher PPI (Pixels Per Inch) results in more detailed image quality. This is especially true for VR products, where the mainstream PPI has now reached around 1000.

[0004] Figure 1 This illustrates the existing low-temperature polycrystalline silicon array substrate manufacturing process. Figure 2 This illustrates the pixel structure of a prior art low-temperature polycrystalline silicon array substrate. Figure 3 It shows Figure 2 A cross-sectional view at point AA. Specifically, the existing low-temperature polycrystalline silicon array substrate manufacturing process includes the following steps:

[0005] Provide a transparent substrate 1';

[0006] A light-shielding layer 2' is formed on the transparent substrate 1' using a first mask;

[0007] A barrier layer 3' is formed on the aforementioned light-shielding layer 2' and transparent substrate 1', such as Figure 2 As shown, the blocking layer 3' covers the aforementioned light-shielding layer 2';

[0008] A polysilicon layer 4' is formed on the barrier layer 3' using a second mask, such as... Figure 2 As shown, the polycrystalline silicon layer 4' is located above the aforementioned light-shielding layer 2';

[0009] Using a third mask, n+ ions are implanted into the sides of the polycrystalline silicon layer 4' located above the light-shielding layer 2' to form an n+ ion implantation layer 5';

[0010] A gate insulating layer 6' is formed on the n+ ion implantation layer 5', the polysilicon layer 4' and the barrier layer 3';

[0011] A scan line layer 7' is formed on the gate insulating layer 6' using a fourth mask, such as... Figure 2 As shown, the scan line layer 7' is located above the aforementioned polysilicon layer 4';

[0012] A silicon nitride protective layer 8' is formed on the aforementioned scan line layer 7' and gate insulating layer 6';

[0013] The bridging hole 9' is obtained by etching the gate insulating layer 6' and the silicon nitride protective layer above the n+ ion implantation layer 5' using the fifth mask;

[0014] The data line layer 10' is formed on the silicon nitride protective layer using the sixth mask, such as... Figure 2 As shown, the data line layer 10' is connected to the n+ ion implantation layer 5' through the bridging hole 9';

[0015] An organic insulating layer 11' is formed on the data line layer 10' and the protective layer using a seventh mask;

[0016] A common electrode layer 12' is formed on the organic insulating layer 11' using an eighth mask;

[0017] A silicon nitride protective layer 13' is formed on the aforementioned common electrode layer 12';

[0018] Contact hole 14' is obtained by etching the organic insulating layer 11' and silicon nitride protective layer above the data line layer 10' using the ninth mask;

[0019] A pixel electrode layer 15' is formed on the aforementioned silicon nitride protective layer using a tenth mask, as follows: Figure 2 As shown, the pixel electrode layer 15' covers the contact hole 14' and is connected to the data line layer 10' through the contact hole 14'.

[0020] from Figure 2 , 3 As can be seen, the presence of multiple vias (such as bridging holes 9' and contact holes 14') within the pixel area occupies pixel space, affects pixel aperture ratio, and makes it difficult to further improve PPI. Although LCD display panels manufactured using the aforementioned existing LTPS array substrates can achieve a certain PPI, high cost remains a major factor restricting the production of low-temperature polysilicon array substrate products. Summary of the Invention

[0021] The technical problem to be solved by the present invention is to overcome the defects of poor display effect and high production cost of LTPS LCD in the prior art, and to provide a low temperature polycrystalline silicon array substrate and its manufacturing method and display panel.

[0022] The present invention solves the above-mentioned technical problems through the following technical solution:

[0023] In a first aspect, a low-temperature polycrystalline silicon array substrate includes:

[0024] Transparent substrate;

[0025] Thin-film transistor, the thin-film transistor comprising:

[0026] A light-shielding layer is formed on the transparent substrate;

[0027] A barrier layer is formed on the light-shielding layer and the transparent substrate;

[0028] A polycrystalline silicon layer is formed on the barrier layer and located above the light-shielding layer;

[0029] The n+ ion implantation layer is implanted into the polycrystalline silicon layer at the two sides above the light-shielding layer.

[0030] A pixel electrode layer is formed on the barrier layer within the pixel region and overlaps with one of the n+ ion implantation layers;

[0031] A data line layer is formed on the barrier layer and partially overlaps another of the n+ ion implantation layers;

[0032] An insulating layer is formed on the data line layer, pixel electrode layer, n+ ion implantation layer, and polysilicon layer;

[0033] A scan line layer is formed on the insulating layer and corresponds to the polysilicon layer that has not been implanted with n+ ions;

[0034] A protective layer is formed on the scan line layer and the insulating layer;

[0035] A common electrode layer is formed on the protective layer and located within the pixel area.

[0036] In a preferred embodiment of the low-temperature polycrystalline silicon array substrate provided by the present invention, the polycrystalline silicon layer is lightly doped in the region between the n+ ion implantation layer and the scan line layer.

[0037] In a preferred embodiment of the low-temperature polycrystalline silicon array substrate provided by the present invention, the light doping is n-ion implantation.

[0038] In a preferred embodiment of the low-temperature polycrystalline silicon array substrate provided by the present invention, the light-shielding layer is a metal light-shielding layer.

[0039] Secondly, a method for manufacturing the aforementioned low-temperature polycrystalline silicon array substrate includes the following steps:

[0040] Provide transparent substrates;

[0041] A light-shielding layer is formed on the transparent substrate;

[0042] A barrier layer is formed on the light-shielding layer and the transparent substrate to cover the light-shielding layer;

[0043] A polycrystalline silicon layer is formed on the barrier layer, which is located above the light-shielding layer;

[0044] n+ ions are implanted into the sides of the polycrystalline silicon layer located above the light-shielding layer to form an n+ ion implantation layer;

[0045] A pixel electrode layer is formed on the barrier layer, which is located within the pixel region, and the pixel electrode layer overlaps with one of the n+ ion implantation layers.

[0046] A data line layer is formed on another n+ ion implantation layer;

[0047] An insulating layer is formed on the data line layer, pixel electrode layer, n+ ion implantation layer, and polysilicon layer.

[0048] A scan line layer is formed on the insulating layer, which corresponds to the polycrystalline silicon layer without n+ ion implantation;

[0049] A protective layer is formed on the scan line layer and the insulating layer;

[0050] A common electrode layer is formed on the protective layer, which is located within the pixel area.

[0051] In a preferred embodiment of the method for manufacturing a low-temperature polycrystalline silicon array substrate provided by the present invention, after the n+ ion implantation step and before the step of forming a pixel electrode layer or a data line layer, the method further includes: performing a light doping step on the region of the polycrystalline silicon layer between the n+ ion implantation layer and the scan line layer.

[0052] In a preferred embodiment of the manufacturing method of the low-temperature polycrystalline silicon array substrate provided by the present invention, the light doping is n-ion implantation.

[0053] In a preferred embodiment of the manufacturing method of the low-temperature polycrystalline silicon array substrate provided by the present invention, the material for forming the light-shielding layer is metal.

[0054] In a preferred embodiment of the manufacturing method of the low-temperature polycrystalline silicon array substrate provided by the present invention, the projected area of ​​the light-shielding layer is larger than the projected area of ​​the overlapping region of the polycrystalline silicon layer and the scan line layer.

[0055] Thirdly, a display panel comprising:

[0056] The low-temperature polycrystalline silicon array substrate described above or the low-temperature polycrystalline silicon array substrate manufactured by the manufacturing method described above.

[0057] Color film substrate;

[0058] And a liquid crystal layer disposed between the low-temperature polycrystalline silicon array substrate and the color filter substrate.

[0059] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of the present invention.

[0060] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0061] The low-temperature polycrystalline silicon array substrate of the present invention eliminates multiple vias in the pixel area, saving a lot of space and increasing the pixel aperture ratio; when the display panel of the present invention is used to make VR products, the PPI can be increased to 1000+; moreover, the manufacturing method of the low-temperature polycrystalline silicon array substrate of the present invention saves two photomasks for forming bridging holes and organic insulating layers compared with the traditional process, and saves one layer of silicon nitride protective layer and organic insulating layer in the process, improving efficiency and saving costs. Attached Figure Description

[0062] Figure 1 This is a flowchart of the manufacturing process for low-temperature polycrystalline silicon array substrates using existing technology.

[0063] Figure 2 This is a schematic diagram of the pixel structure of a low-temperature polycrystalline silicon array substrate in the prior art;

[0064] Figure 3 for Figure 2 A cross-sectional view of line A in the middle;

[0065] Figure 4 This is a flowchart illustrating the manufacturing process of a low-temperature polycrystalline silicon array substrate according to a preferred embodiment of the present invention.

[0066] Figure 5 This is a schematic diagram of the pixel structure of a low-temperature polycrystalline silicon array substrate according to a preferred embodiment of the present invention.

[0067] Figure 6 for Figure 5 A cross-sectional view of line B in the middle. Detailed Implementation

[0068] As described in the background art above, in the prior art low-temperature polycrystalline silicon array substrate, from... Figure 2 , 3 It is known that the presence of multiple vias (such as bridging holes and contact holes) within the pixel area occupies pixel space, affects the pixel aperture ratio, and makes it difficult to further improve PPI. Although LCD display panels manufactured using the aforementioned existing LTPS array substrates can achieve a certain PPI, the high cost remains a major factor restricting the production of low-temperature polysilicon array substrate products.

[0069] To address this technical problem, the inventors have proposed a low-temperature polycrystalline silicon array substrate, its manufacturing method, and a display panel.

[0070] The present invention solves the above-mentioned technical problems through the following technical solution:

[0071] In a first aspect, a low-temperature polycrystalline silicon array substrate includes:

[0072] Transparent substrate 1;

[0073] Thin-film transistor, the thin-film transistor comprising:

[0074] A light-shielding layer 2 is formed on the transparent substrate 1;

[0075] A barrier layer 3 is formed on the light-shielding layer 2 and the transparent substrate 1;

[0076] A polycrystalline silicon layer 4 is formed on the barrier layer 3 and is located above the light-shielding layer 2;

[0077] The n+ ion implantation layer 5 is implanted into the polysilicon layer 4 at the side ends above the light-shielding layer 2.

[0078] A pixel electrode layer 6 is formed on the barrier layer 3 within the pixel region and overlaps with an n+ ion implantation layer 5.

[0079] Data line layer 7 is formed on the barrier layer 3 and partially overlaps on another n+ ion implantation layer 5;

[0080] An insulating layer 8 is formed on the data line layer 7, the pixel electrode layer 6, the n+ ion implantation layer 5, and the polysilicon layer 4.

[0081] Scan line layer 9 is formed on the insulating layer 8 and corresponds to the polysilicon layer 4 without n+ ion implantation;

[0082] A protective layer 10 is formed on the scan line layer 9 and the insulating layer 8;

[0083] A common electrode layer 11 is formed on the protective layer 10 and located within the pixel area.

[0084] The low-temperature polycrystalline silicon array substrate of the present invention eliminates multiple vias in the pixel area, saving a lot of space and increasing the pixel aperture ratio; when the display panel of the present invention is used to make VR products, the PPI can be increased to 1000+.

[0085] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0086] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0087] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0088] Example 1

[0089] like Figure 4 As shown, a method for manufacturing a low-temperature polycrystalline silicon array substrate is illustrated, which includes the following steps S1 to S12.

[0090] Step S1: Provide a transparent substrate 1.

[0091] The transparent substrate 1 is made of glass. Of course, those skilled in the art should understand that other types of substrate 1, such as plastic, can also be used in other embodiments.

[0092] Step S2: Form a light-shielding layer 2 on the transparent substrate 1.

[0093] A metal layer is formed on a transparent substrate 1, and then the metal layer is patterned by a first photomask process to obtain a light-shielding layer 2 with a predetermined pattern.

[0094] The principle and process of the first photomask process are as follows: A photoresist is coated on a whole metal layer, and then the first photomask is used for exposure and development. After development, the exposed and unexposed photoresist are removed and retained on the metal layer, respectively. Then, the metal layer not covered by the photoresist is etched away. Finally, the photoresist is removed to obtain the light-shielding layer 2.

[0095] Step S3: Form a barrier layer 3 on the light-shielding layer 2 and the transparent substrate 1 to cover the light-shielding layer 2.

[0096] The barrier layer 3 can be a silicon nitride layer or a silicon oxide layer, used to prevent impurities in the transparent substrate 1 from diffusing upwards and affecting the quality of the polycrystalline silicon layer 4 formed later in the subsequent process.

[0097] Step S4: A polycrystalline silicon layer 4 is formed on the barrier layer 3, which is located above the light-shielding layer 2.

[0098] A polysilicon layer 4 is formed on the blocking layer 3. Then, the polysilicon layer 4 is patterned by a second photomask process to obtain a polysilicon layer 4 with a predetermined pattern, that is, a polysilicon layer 4 located above the light-shielding layer 2. The process principle and procedure of the second photomask are similar to those of the first photomask, and will not be described in detail here.

[0099] Step S5: n+ ions are implanted into the sides of the polycrystalline silicon layer 4 above the light-shielding layer 2 to form an n+ ion implantation layer 5.

[0100] A third photomask is placed above the polysilicon layer 4, and then n+ ion implantation is performed on the unshielded part. The corresponding side ends on both sides above the light-shielding layer 2 become the n+ ion implantation layer 5.

[0101] Step S6: A pixel electrode layer 6 is formed on the barrier layer 3, which is located in the pixel region, and the pixel electrode layer 6 overlaps with the n+ ion implantation layer 5.

[0102] A transparent electrode layer is formed on the barrier layer 3, the n+ ion implantation layer 5, and the polysilicon layer 4. Then, a fourth photomask process is used to pattern this transparent electrode layer, resulting in a pixel electrode layer 6 with a predetermined pattern, located within the pixel region. The pixel electrode layer 6 also overlaps with one of the n+ ion implantation layers 5. The fabrication principle and process of the fourth photomask are similar to those of the first photomask and will not be described in detail here.

[0103] Step S7: A data line layer 7 is formed on the barrier layer 3, which is partially overlapped on another n+ ion implantation layer 5.

[0104] A full-surface conductive metal layer is formed on the barrier layer 3, the n+ ion implantation layer 5, and the polysilicon layer 4. Then, a fifth photomask process is used to pattern this full-surface conductive metal layer, thereby obtaining a data line layer 7 with a predetermined pattern, i.e., a data line layer 7 that is on the barrier layer 3 and partially overlaps with another n+ ion implantation layer 5. The fabrication principle and process of the fifth photomask are similar to those of the first photomask, and will not be described in detail here.

[0105] In other embodiments, after step S7, the following steps are performed first: a light doping step, such as n-ion implantation, is performed on the polysilicon layer 4 in the region between the n+ ion implantation layer 5 and the scan line layer 9.

[0106] Step S8: An insulating layer 8 is formed on the data line layer 7, the pixel electrode layer 6, the n+ ion implantation layer 5, and the polysilicon layer 4.

[0107] Step S9: A scan line layer 9 is formed on the insulating layer 8, which corresponds to the polycrystalline silicon layer 4 without n+ ion implantation.

[0108] A full-surface metallic conductive layer is formed on the insulating layer 8. Then, the full-surface metallic conductive layer is patterned using a sixth photomask process to obtain a scan line layer 9 with a predetermined pattern, located directly above the polysilicon layer 4 without n+ ion implantation. The process principle and procedure of the sixth photomask are similar to those of the first photomask, and will not be described in detail here.

[0109] Step S10: Form a protective layer 10 on the scan line layer 9 and the insulating layer 8.

[0110] Step S11: A common electrode layer 11 is formed on the protective layer 10, which is located within the pixel area.

[0111] A transparent electrode layer is formed on the protective layer 10. Then, the transparent electrode layer is patterned using a seventh photomask process to obtain a common electrode layer 11 with a predetermined pattern, which is the common electrode layer 11 located in the pixel area and overlaps with the pixel electrode layer 6. The process principle and procedure of the seventh photomask are similar to those of the first photomask, and will not be described in detail here.

[0112] The low-temperature polycrystalline silicon array substrate manufacturing method of this embodiment saves two photomasks for forming bridging holes and organic insulating layer 8 compared with the conventional process, and only uses 7 photomask processes. The process saves one layer of silicon nitride protective layer 10 and organic insulating layer 8, thereby greatly simplifying the process, improving efficiency, and saving costs.

[0113] Example 2

[0114] This embodiment illustrates a low-temperature polycrystalline silicon array substrate, which includes a transparent substrate 1 and thin-film transistors formed on the transparent substrate 1. The low-temperature polycrystalline silicon array substrate of this embodiment is mainly obtained by the manufacturing method of Embodiment 1 described above.

[0115] Specifically, the thin-film transistor includes: a light-shielding layer 2 formed on a transparent substrate 1; a barrier layer 3 formed on the light-shielding layer 2 and the transparent substrate 1; a polysilicon layer formed on the barrier layer 3 and above the light-shielding layer 2; an n+ ion implantation layer 5 formed by implanting n+ ions into the side ends of the polysilicon layer 4 located on both sides above the light-shielding layer 2; a lightly doped layer 12 on the polysilicon layer 4 and between the n+ ion implantation layer 5 and the scan line layer 9; a pixel electrode layer 6 formed on the barrier layer 3, located in the pixel region and overlapping with one n+ ion implantation layer 5; a data line layer 7 formed on the barrier layer 3 and partially overlapping with another n+ ion implantation layer 5; an insulating layer 8 formed on the data line layer 7, the pixel electrode layer 6, the n+ ion implantation layer 5, and the polysilicon layer 4; a scan line layer 9 formed on the insulating layer 8 and corresponding to the polysilicon layer 4 without n+ ion implantation; a protective layer 10 formed on the scan line layer 9 and the insulating layer 8; and a common electrode layer 11 formed on the protective layer 10 and located in the pixel region.

[0116] Example 3

[0117] This embodiment illustrates a display panel comprising a color filter substrate and an array substrate disposed at relatively intervals, and a liquid crystal layer filling the color filter substrate and the low-temperature polycrystalline silicon array substrate. The array substrate can employ the same structural design as the low-temperature polycrystalline silicon array substrate of Embodiment 1 or Embodiment 2, and therefore has the same beneficial effects.

[0118] It should be noted that in the claims and specification of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A low-temperature polycrystalline silicon array substrate, characterized in that, It includes: Transparent substrate; Thin-film transistor, the thin-film transistor comprising: A light-shielding layer is formed on the transparent substrate. The light-shielding layer is a metal light-shielding layer, and the projected area of ​​the light-shielding layer is larger than the projected area of ​​the overlapping region of the polysilicon layer and the scan line layer. A barrier layer is formed on the light-shielding layer and the transparent substrate; A polycrystalline silicon layer is formed on the barrier layer and located above the light-shielding layer; The n+ ion implantation layer is implanted into the polycrystalline silicon layer at the two sides above the light-shielding layer. A pixel electrode layer is formed on the barrier layer within the pixel region and overlaps with one of the n+ ion implantation layers; A data line layer is formed on the barrier layer and partially overlaps another of the n+ ion implantation layers; An insulating layer is formed on the data line layer, pixel electrode layer, n+ ion implantation layer, and polysilicon layer; A scan line layer is formed on the insulating layer and corresponds to the polysilicon layer that has not been implanted with n+ ions; A protective layer is formed on the scan line layer and the insulating layer; A common electrode layer is formed on the protective layer and located within the pixel area.

2. The low-temperature polycrystalline silicon array substrate as described in claim 1, characterized in that, The polycrystalline silicon layer is lightly doped in the region between the n+ ion implantation layer and the scan line layer.

3. The low-temperature polycrystalline silicon array substrate as described in claim 2, characterized in that, The light doping is achieved through n-ion implantation.

4. A method for manufacturing a low-temperature polycrystalline silicon array substrate as described in claim 1, characterized in that, Includes the following steps: Provide transparent substrates; A light-shielding layer is formed on the transparent substrate, and the projected area of ​​the light-shielding layer is larger than the projected area of ​​the overlapping region of the polysilicon layer and the scan line layer. A barrier layer is formed on the light-shielding layer and the transparent substrate to cover the light-shielding layer; A polycrystalline silicon layer is formed on the barrier layer, which is located above the light-shielding layer; n+ ions are implanted into the sides of the polycrystalline silicon layer located above the light-shielding layer to form an n+ ion implantation layer; A light doping step is performed on the region of the polycrystalline silicon layer between the n+ ion implantation layer and the scan line layer; A pixel electrode layer is formed on the barrier layer, which is located within the pixel region, and the pixel electrode layer overlaps with one of the n+ ion implantation layers. A data line layer is formed on another n+ ion implantation layer; An insulating layer is formed on the data line layer, pixel electrode layer, n+ ion implantation layer, and polysilicon layer. A scan line layer is formed on the insulating layer, which corresponds to the polycrystalline silicon layer without n+ ion implantation; A protective layer is formed on the scan line layer and the insulating layer; A common electrode layer is formed on the protective layer, which is located within the pixel area.

5. The method for manufacturing a low-temperature polycrystalline silicon array substrate as described in claim 4, characterized in that, The light doping is achieved through n-ion implantation.

6. The method for manufacturing a low-temperature polycrystalline silicon array substrate as described in claim 4, characterized in that, The material used to form the light-shielding layer is metal.

7. A display panel, characterized in that, It includes: The low-temperature polycrystalline silicon array substrate as described in any one of claims 1-3 or the low-temperature polycrystalline silicon array substrate manufactured by the manufacturing method as described in any one of claims 4-6; Color film substrate; And a liquid crystal layer disposed between the low-temperature polycrystalline silicon array substrate and the color filter substrate.

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