Semiconductor device
By setting a semiconductor layer structure with a specific impurity concentration distribution in the RC-IGBT device, the problem of increased losses caused by bounce was solved, and the stability and efficiency of the return current were improved.
Patent Information
- Application Number
- CN202210131976.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2021-09-17
- Filing Date
- 2022-02-14
- Publication Date
- 2026-11-06
- Estimated Expiration
- 2042-02-14
AI Technical Summary
Existing RC-IGBT devices are prone to backflow during the return current process, which leads to increased losses.
A semiconductor layer structure with a specific impurity concentration distribution is set between the diode region and the IGBT region, including a high impurity concentration region near the IGBT region and a low impurity concentration region far away from the IGBT region, in order to control the injection and discharge of charge carriers and suppress the occurrence of backlash.
It effectively suppressed the backflow phenomenon, reduced device losses, and improved the stability and efficiency of the return current.
Smart Images
Figure CN115832003B_ABST
Abstract
Description
[0001] This application claims priority based on Japanese Patent Application No. 2021-152087 (filed on September 17, 2021), the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to semiconductor devices. Background Technology
[0003] Previously, RC-IGBTs (Reverse Conducting IGBTs) were known to have both a diode region and an IGBT (Insulated Gate Bipolar Transistor) region. In RC-IGBTs, the return current from the emitter side to the collector side of the IGBT region can flow through the diode region. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device that can reduce losses while suppressing snapback.
[0005] The semiconductor device according to the technical solution is a semiconductor device having a diode region and an IGBT region, comprising: a first electrode disposed across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type disposed on the first electrode in the diode region; a second semiconductor layer of a second conductivity type disposed on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type disposed on the first semiconductor layer and the second semiconductor layer, wherein the impurity concentration in the first region of the upper layer located in the diode region and adjacent to the IGBT region is lower than the impurity concentration in the second region located in the diode region and separated from the IGBT region; and a third semiconductor layer of the second conductivity type disposed on the first and second semiconductor layers. The diode region and the IGBT region are disposed on the semiconductor portion; the fourth semiconductor layer of the first conductivity type is disposed on the upper portion of the third semiconductor layer in the IGBT region; the second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion; the third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and an insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode. Attached Figure Description
[0006] Figure 1 This is a top view showing the semiconductor device according to the first embodiment.
[0007] Figure 2 yes Figure 1 A cross-sectional view of line A-A'.
[0008] Figure 3 (a) is a schematic diagram showing the direction of carrier movement within the semiconductor device according to the first embodiment. Figure 3 (b) is a schematic diagram showing the direction of carrier movement within a semiconductor device for the reference example.
[0009] Figure 4 (a) is a graph showing the simulation results of the relationship between the voltage Vak applied between the upper electrode and the lower electrode and the return current Iak in the diode region of the semiconductor device of the first embodiment and the semiconductor device of the reference example. Figure 4 (b) is a graph showing the simulation results of the carrier density of the semiconductor device of the first embodiment and the semiconductor device of the reference example.
[0010] Figure 5 This is a cross-sectional view showing the semiconductor device according to the second embodiment.
[0011] Figure 6 This is a cross-sectional view showing the semiconductor device according to the third embodiment.
[0012] Figure 7 (a) is along the p-type semiconductor layer and p in the first region of the diode region. + A cross-sectional view of the upper surface of the contact layer of the type. Figure 7 (b) is along the p-type semiconductor layer and p in the second region of the diode region. + A cross-sectional view of the upper surface of the contact layer of the type. Detailed Implementation
[0013] The following is a reference to the appendix. Figure 1 Each embodiment will be described below. Furthermore, the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the proportions between parts, etc., may not be the same as in reality. Moreover, even when representing the same parts, the dimensions or proportions may sometimes differ depending on the drawings. Furthermore, in this specification and in the drawings, the same reference numerals are used for elements that are the same as those described with respect to existing drawings, and detailed descriptions are appropriately omitted.
[0014] Furthermore, to facilitate understanding, the following explanation uses an XYZ orthogonal coordinate system to illustrate the configuration and structure of each part. The X-axis, Y-axis, and Z-axis are mutually orthogonal. Additionally, the direction in which the X-axis extends is designated as the "X direction," the direction in which the Y-axis extends is designated as the "Y direction," and the direction in which the Z-axis extends is designated as the "Z direction." Furthermore, to facilitate understanding, the arrows in the Z-direction are designated upwards, and their opposite direction is designated downwards, but their directions are independent of the direction of gravity.
[0015] Furthermore, the following + and - markings indicate the relative levels of impurity concentration for each conductivity type. Specifically, a marking with "+" indicates a higher impurity concentration compared to a marking without "+" and "-". A marking with "-" indicates a lower impurity concentration compared to a marking without "+" and "-". Here, in cases where each region contains both donor and acceptor impurities, "impurity concentration" refers to the net impurity concentration after these impurities have been neutralized.
[0016] <First Implementation>
[0017] First, the first embodiment will be described.
[0018] Figure 1 This is a top view showing the semiconductor device according to this embodiment.
[0019] Figure 2 yes Figure 1 A cross-sectional view of line A-A'.
[0020] The semiconductor device 100 in this embodiment is an RC-IGBT. In the semiconductor device 100, such as... Figure 1 As shown, multiple diode regions S1 and multiple IGBT regions S2 are provided. The multiple diode regions S1 and multiple IGBT regions S2 are arranged alternately in the X direction.
[0021] Semiconductor device 100, such as Figure 2 As shown, in this embodiment, a lower electrode 110 and an n are provided. + Type 121, p + Collector layer 122 of type n, semiconductor layer 123 of type n, semiconductor layer 124 of type p, and semiconductor layer n + The semiconductor device 100 includes an emitter layer 126, multiple internal electrodes 130, multiple gate electrodes 140, an upper electrode 150, multiple insulating films 161, and multiple insulating films 162. The various parts of the semiconductor device 100 will be described in detail below.
[0022] The lower electrode 110 is made of a conductive material such as a metal. The lower electrode 110 is disposed over approximately the entire area of the lower surface of the semiconductor device 100. That is, the lower electrode 110 spans both the diode region S1 and the IGBT region S2. In the diode region S1, the lower electrode 110 functions as a cathode electrode, and in the IGBT region S2, it functions as a collector electrode. The upper and lower surfaces of the lower electrode 110 are approximately parallel to the XY plane.
[0023] n + In this embodiment, the cathode layer 121 is disposed on the portion of the lower electrode 110 located in the diode region S1.
[0024] p + In this embodiment, the collector layer 122 is disposed on the portion of the lower electrode 110 located in the IGBT region S2. + Type 122 collector layer and n + The cathode layers 121 of type n are adjacent in the X direction. However, n + A portion of the cathode layer of this type can also be located within the IGBT region, p + A portion of the collector layer of a diode can also be located within the diode region.
[0025] An n-type semiconductor section 123 is disposed across the diode region S1 and the IGBT region S2. In this embodiment, the semiconductor section 123 is disposed in the diode region S1. + On the cathode layer 121 of the type, p is disposed in the IGBT region. + On the collector layer 122 of the type.
[0026] Semiconductor section 123 has n + Type 123a, n buffer layer - Type 123b drift layer and type n barrier layer 123c.
[0027] n + A buffer layer 123a of type [type] is provided spanning the diode region S1 and the IGBT region S2. Furthermore, n + The buffer layer 123a of the type is disposed in the diode region S1 at n + On the cathode layer 121 of the type, a p-type cathode is disposed in the IGBT region S2. + On the collector layer 122 of type n. + The impurity concentration of buffer layer 123a of type n is higher than that of n. + The n-type cathode layer 121 has a low impurity concentration. However, in semiconductor devices, the n-type buffer layer may not be provided.
[0028] n -The drift layer 123b of the type is disposed in the diode region S1 and the IGBT region S2 in n + On type 123a buffer layer. - The impurity concentration of drift layer 123b of type n is higher than that of n. + The impurity concentration of the buffer layer 123a is low.
[0029] like Figure 1 As shown, diode region S1 includes a first region S1a adjacent to IGBT region S2 and a second region S1b separated from IGBT region S2. In diode region S1 located between two IGBT regions S2, one second region S1b is located between two first regions S1a. Therefore, in diode region S1 located between two IGBT regions S2, the first region S1a is the region near IGBT region S2 in diode region S1, and the second region S1b is the central region in diode region S1.
[0030] n-type barrier layer 123c, such as Figure 2 As shown, n is configured in region S1b and IGBT region S2. - The upper part of the drift layer 123b is n-type. In this embodiment, the n-type blocking layer 123c is not provided in the diode region S1 and the first region S1a. The impurity concentration of the n-type blocking layer 123c is higher than that of the n-type barrier layer 123c. - The impurity concentration of the n-type drift layer 123b is high. Furthermore, the impurity concentration of the n-type barrier layer 123c is higher than that of the n-type barrier layer. + Type 121 and n cathode layer + The impurity concentration of the n-type buffer layer 123a is low. However, the impurity concentration of the n-type barrier layer is similar to that of the n-type barrier layer. + Type of cathode layer and n + The relationship between the impurity concentration in the buffer layer is not limited to the above description.
[0031] Thus, in this embodiment, since an n-type barrier layer 123c is provided in the second region S1b, the impurity concentration of the portion of the upper layer of the semiconductor portion 123 located in the first region S1a is lower than the impurity concentration of the portion located in the second region S1b. The impurity concentration of the n-type barrier layer 123c is lower than that of the n-type barrier layer 123c. - The difference in impurity concentration in the drift layer 123b of type 1 is not particularly limited, for example, it is 3 × 10 13 cm -3 Above 1×10 14 cm -3 the following.
[0032] However, the method of setting the impurity concentration in the portion of the upper layer of the n-type semiconductor region located in the first region to be lower than the impurity concentration in the portion located in the second region is not limited to the above description. For example, the upper layer of the n-type semiconductor region may also be configured such that the impurity concentration gradually increases or increases in stages from the boundary between the diode region and the IGBT region toward the center of the diode region.
[0033] In this embodiment, such as Figure 1 As shown, the width L1 of the first region S1a in the X direction is shorter than the width L2 of the second region S1b in the X direction. However, the relationship between the widths of the first and second regions is not limited to the above description. For example, the width of the first region may be approximately the same as the width of the second region, or the width of the first region may be longer than the width of the second region.
[0034] p-type semiconductor layer 124, as shown Figure 2 As shown, it is disposed in the diode region S1 and the IGBT region S2. The p-type semiconductor layer 124 is disposed in the n-type region S2. - On the drift layer 123b of type n, with n - The p-type drift layer 123b is in contact with the n-type barrier layer 123c. In addition, the p-type semiconductor layer 124 is disposed on the n-type barrier layer 123c in the second region S1b and the IGBT region S2, and is in contact with the n-type barrier layer 123c.
[0035] n + The emitter layer 126 is disposed on the upper part of the p-type semiconductor layer 124 in the IGBT region S2, and is not disposed in the diode region S1.
[0036] n + Type 121, p + The collector layer 122 of type n, the semiconductor layer 123 of type n, the semiconductor layer 124 of type p, and the semiconductor layer 125 of type n + The emitter layer 126 of the type contains, for example, a semiconductor material such as silicon and impurities corresponding to each layer.
[0037] Additionally, in the diode region S1, a p-type semiconductor layer 124 may also be partially disposed on its upper portion. + The contact layer has a higher impurity concentration than the p-type semiconductor layer 124 and makes a 150-ohm contact with the upper electrode 150 described later.
[0038] Multiple trenches T1 are formed in the diode region S1. The multiple trenches T1 are arranged in the X direction. Each trench T1 extends from the upper surface of the p-type semiconductor layer 124 to the n-type semiconductor layer 124. - A drift layer 123b of type n. Furthermore, each trench T1 extends in the Y direction. The lower end of each trench T1 is located below the lower surface of the type n barrier layer 123c, and below the lower surface of the type n barrier layer 123c.- The lower surface of the drift layer 123b is located at the top.
[0039] An internal electrode 130 is disposed within each trench T1. Each internal electrode 130 is made of a conductive material such as metal or polysilicon. Each internal electrode 130 extends from the upper surface of the p-type semiconductor layer 124 to the n-type semiconductor layer 124. - The drift layer 123b is of the n-type type. The lower end of each internal electrode 130 is located below the lower surface of the n-type barrier layer 123c, and is lower than the n-type barrier layer 123c. - The lower surface of the drift layer 123b is located at the top. The internal electrodes 130 within region S1a are connected to the p-type semiconductor layer 124 and the n-type semiconductor layer 123b. - The p-type drift layer 123b is adjacent to each other in the X direction. Within the second region S1b, each internal electrode 130 is adjacent to the p-type semiconductor layer 124, the n-type barrier layer 123c, and the n-type... - The drift layers 123b of the type are adjacent in the X direction.
[0040] Multiple trenches T2 are provided in the IGBT region S2. The multiple trenches T2 are arranged in the X direction. Each trench T2 starts from n... + The upper surface of the emitter layer 126 extends to n - Type 123b drift layer. The lower end of each trench T2 is located at a point greater than n. - The upper surface of the drift layer 123b is located at the bottom, compared to n. - The lower surface of the drift layer 123b is located at the top.
[0041] Within each trench T2, a gate electrode 140 is disposed. Each gate electrode 140 is made of a conductive material such as metal or polysilicon. Each gate electrode 140 is connected from n + The upper surface of the emitter layer 126 extends to n - A drift layer 123b of type n. The lower end of each gate electrode 140 is located at a position greater than n. - The lower surface of the drift layer 123b is located at the top. Each gate electrode 140 and n + The emitter layer 126, the p-type semiconductor layer 124, the n-type barrier layer 123c, and the n-type semiconductor layer 124 are all present. - The drift layers 123b of the type are adjacent in the X direction.
[0042] The upper electrode 150 is made of a conductive material such as a metal. The upper electrode 150 spans the diode region S1 and the IGBT region S2. The upper electrode 150 is disposed on the p-type semiconductor layer 124 in the diode region S1. Furthermore, the upper electrode 150 is disposed on the n-type semiconductor layer 124 in the IGBT region S2. +The upper electrode 150 functions as an anode electrode in the diode region S1 and as an emitter electrode in the IGBT region S2. Furthermore, the upper electrode 150 is electrically connected to each of the internal electrodes 130. That is, the potential of the upper electrode 150 is approximately equal to the potential of the internal electrodes 130.
[0043] Each insulating film 161 is disposed in the diode region S1 between each internal electrode 130 and the upper electrode 150, between each internal electrode 130 and the p-type semiconductor layer 124, and between each internal electrode 130 and the n-type semiconductor section 123.
[0044] Each insulating film 162 is disposed in the IGBT region S2 between each gate electrode 140 and the upper electrode 150, and between each gate electrode 140 and n + Between the emitter layer 126 of the type, between each gate electrode 140 and the p-type semiconductor layer 124, and between each gate electrode 140 and the n-type semiconductor layer 123.
[0045] Each insulating film 161 and 162 is made of insulating materials such as silicon oxide or silicon nitride.
[0046] Next, the effects of the semiconductor device 100 of this embodiment will be explained.
[0047] Figure 3 (a) is a schematic diagram showing the direction of carrier movement within the semiconductor device according to this embodiment. Figure 3 (b) is a schematic diagram showing the direction of carrier movement in the semiconductor device of the reference example.
[0048] Figure 4 (a) is a graph showing the simulation results of the relationship between the voltage Vak applied between the upper electrode and the lower electrode and the return current Iak in the diode region of the semiconductor device of the present embodiment and the semiconductor device of the reference example. Figure 4 (b) is a graph showing the simulation results of the carrier density of the semiconductor device of this embodiment and the semiconductor device of the reference example.
[0049] In addition, Figure 3 (a) and Figure 3 In (b), a circle encloses h to represent a hole, and a circle encloses e to represent an electron. Furthermore, Figure 4 In (a), the horizontal axis represents voltage Vak, and the vertical axis represents return current Iak. Furthermore, Figure 4 (b) The horizontal axis represents the position in the X direction, and the vertical axis represents the carrier density.
[0050] In the semiconductor device 100 of this embodiment, such as Figure 3As shown in (a), no n-type blocking layer 123c is provided in the first region S1a of the diode region S1. In contrast, in the semiconductor device 900 of the relevant reference example, such as... Figure 3 As shown in (b), in the first region S1a of the diode region S1, an n-type blocking layer 123c is provided in the n-type semiconductor portion 923.
[0051] With the IGBT region S2 off and the diode region S1 on, a return current Iak flows through the diode region S1. For example... Figure 4 As shown in (a), in the semiconductor device 900 of the relevant reference example, as the voltage Vak applied between the lower electrode 110 and the upper electrode 150 increases, the return current Iak increases. Furthermore, after the voltage Vak reaches the peak voltage Vsn2, the return current Iak increases, and the voltage Vak drops sharply. This phenomenon is called "snapback".
[0052] Similarly, in the semiconductor device 100 of this embodiment, as the voltage Vak applied between the lower electrode 110 and the upper electrode 150 increases, the return current Iak increases. Furthermore, after the voltage Vak reaches its peak voltage Vsn1, the return current Iak increases, and the voltage Vak decreases. However, the peak voltage Vsn1 of this embodiment is lower than the peak voltage Vsn2 of the reference example. Moreover, in this embodiment, a larger return current Iak can flow at a lower voltage Vak than in the reference example. That is, in the semiconductor device 100 of this embodiment, bounce can be suppressed compared to the semiconductor device 900 of the reference example.
[0053] In the semiconductor device 900 of the relevant reference example, such as Figure 3 As shown in (b), an n-type blocking layer 123c is provided in the first region S1a, so it is difficult for holes to be injected from the upper electrode 150 into the n-type hole in the first region S1a. - The drift layer 123b of this type has a small amount of holes discharged from the portion of the lower electrode 110 located within the first region S1a. Therefore, it is difficult for electrons to be injected from the lower electrode 110 into the n in the first region S1a. - Type 123b drift layer. Therefore, n in the first region S1a - The carrier density within the drift layer 123b of the type is low. As a result, the n-type carrier density within the first region S1a is low. - The effect of conductivity modulation of the drift layer 123b, that is, to make n in the first region S1a... -The effect of reducing the resistance of the drift layer 123b is reduced. Consequently, holes are more easily eroded from the first region S1a towards the IGBT region S2. Therefore, the amount of holes discharged from the lower electrode 110 from the portion located in the first region S1a is further reduced, and the amount of holes eroded from the lower electrode 110 towards the portion located in the first region S1a is further reduced. - The amount of electrons injected into the drift layer 123b of the type is further reduced. Therefore, it can be considered that when a voltage Vak is applied between the lower electrode 110 and the upper electrode 150, it is difficult for the return current Iak to flow, resulting in a bounce.
[0054] On the other hand, in the semiconductor device 100 of this embodiment, such as Figure 3 As shown in (a), since no n-type blocking layer 123c is provided in the first region S1a, holes can easily be injected from the upper electrode 150 into the n-type region S1a. - The drift layer 123b of this type has a large number of holes discharged from the portion of the lower electrode 110 located in the first region S1a. Therefore, electrons can be easily injected from the lower electrode 110 into the n in the first region S1a. - Type 123b drift layer. Therefore, n in the first region S1a - The carrier density within the drift layer 123b of the type increases. As a result, the n-carrier density increases within the first region S1a. - The effect of conductivity modulation of the drift layer 123b, that is, making n - The resistance reduction effect of the drift layer 123b is amplified. Consequently, holes find it difficult to erode from the first region S1a towards the IGBT region S2, and holes become easier to escape from the portion of the lower electrode 110 located within the first region S1a. Therefore, the n-holes from the lower electrode 110 into the first region S1a... - The amount of electrons injected into the drift layer 123b of the type is further increased. Therefore, it can be considered that when a voltage Vak is applied between the lower electrode 110 and the upper electrode 150, the return current Iak becomes easier to flow, and bounce can be suppressed.
[0055] Therefore, such as Figure 4 As shown in (b), the carrier density in the IGBT region S2 of this embodiment is lower than the carrier density in the IGBT region S2 of the reference example, and the carrier density in the first region S1a of this embodiment is higher than the carrier density in the first region S1a of the reference example. Furthermore, as... Figure 4 As shown in (a), it can be considered that in this embodiment, the peak voltage Vsn1 becomes lower than the peak voltage Vsn2 of the reference example, and a larger return current Iak can flow under the lower voltage Vak than in the reference example.
[0056] Furthermore, in this embodiment, an n-type blocking layer 123c is provided in the second region S1b of the diode region S1. Therefore, when the diode region S1 is conducting, holes are difficult to inject from the upper electrode 150 into the n-type blocking layer in the second region S1b. - The drift layer 123b is of this type. Therefore, it is difficult for electrons to be injected from the lower electrode 110 into the second region S1b. - Type 123b drift layer. Therefore, n in the second region S1b - The carrier density within the drift layer 123b of the type becomes lower. Therefore, the diode region S1 becomes disconnected, which reduces the loss during recovery.
[0057] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 100 with low recovery loss while suppressing bounce can be provided.
[0058] Furthermore, in this embodiment, the width L1 of the first region S1a is shorter than the width L2 of the second region S1b. Thus, by confining the region that promotes carrier injection to the vicinity of the IGBT region S2, recovery loss can be appropriately reduced while suppressing bounce.
[0059] <Second Implementation Method>
[0060] Next, the second embodiment will be described.
[0061] Figure 5 This is a cross-sectional view showing the semiconductor device according to this embodiment.
[0062] In this embodiment, the semiconductor device 200 implants n in the first region S1a and the second region S1b within the diode region S1. - The method for differentiating the amount of charge carriers in the drift layer 123b of the type is different from that of the semiconductor device 100 of the first embodiment.
[0063] Furthermore, the following description will only focus on the differences from the first embodiment. Everything else is the same as the first embodiment, except for the matters described below. The same applies to the other embodiments described below.
[0064] In the semiconductor section 223 of the semiconductor device 200, an n-type barrier layer 123c is not provided in the second region S1b. That is, the impurity concentration of the portion of the upper layer of the semiconductor section 223 located in the first region S1a is approximately equal to the impurity concentration of the portion of the upper layer of the semiconductor section 223 located in the second region S1b.
[0065] The impurity concentration of the first portion 224a of the p-type semiconductor layer 224 located in the first region S1a of the diode region S1 of the semiconductor device 200 is higher than that of the second portion 224b located in the second region S1b. Furthermore, in this embodiment, the impurity concentration of the first portion 224a is lower than that of the third portion 224c of the p-type semiconductor layer 224 located in the IGBT region S2. However, the relationship between the impurity concentrations of the first and third portions is not limited to the above description. For example, the upper layer of the n-type semiconductor portion may also be configured such that the impurity concentration gradually increases or increases in stages from the boundary between the diode region and the IGBT region toward the center of the diode region. Furthermore, for example, the p-type semiconductor layer may also be configured such that the impurity concentration gradually decreases or decreases in stages from the boundary between the diode region and the IGBT region toward the center of the diode region.
[0066] Next, the effects of this implementation method will be explained.
[0067] Because of the high impurity concentration in part 224a, holes can easily be injected from the upper electrode 150 into the n in region S1a. - The drift layer 123b is of the type. Therefore, rebound can be suppressed. On the other hand, since the impurity concentration of the second part 224b is low, it is difficult for holes to be injected from the upper electrode 150 into the second region S1b. - The drift layer 123b is of the type. Therefore, the recovery loss of the diode region S1 can be reduced.
[0068] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 200 with low recovery loss while suppressing bounce can be provided.
[0069] <Third Implementation Method>
[0070] Next, the third embodiment will be described.
[0071] Figure 6 This is a cross-sectional view showing the semiconductor device according to this embodiment.
[0072] Figure 7 (a) is along the p-type semiconductor layer and p in the first region of the diode region. + A cross-sectional view of the upper surface of the contact layer of the type. Figure 7 (b) is along the p-type semiconductor layer and p in the second region of the diode region. + A cross-sectional view of the upper surface of the contact layer of the type.
[0073] In this embodiment, the semiconductor device 300 injects n into the first region S1a and the second region S1b within the diode region S1. - The method for differentiating the amount of charge carriers in the drift layer 123b of the type is different from that of the semiconductor device 100 of the first embodiment.
[0074] In the semiconductor section 323 of the semiconductor device 300, such as Figure 6 As shown, no n-type barrier layer 123c is provided in the second region S1b. That is, the impurity concentration of the portion of the upper layer of the semiconductor section 323 located in the first region S1a is approximately equal to the impurity concentration of the portion of the upper layer of the semiconductor section 323 located in the second region S1b.
[0075] Semiconductor device 300 has a p-type semiconductor layer 124 disposed on the upper part of the p-type semiconductor layer 124. + Type 325 contact layer. p + Type 325 contact layer Figure 7 (a) and Figure 7 As shown in (b), it includes a plurality of extensions 325a. Each extension 325a extends in the X direction. The plurality of extensions 325a are spaced apart from each other and arranged in the Y direction. That is, p + The contact layer of this type is configured in a striped pattern. However, p + The structure of the contact layer is not limited to the description above. For example, the extensions may extend in the Y direction or other directions instead of the X direction, and multiple extensions may be arranged in the X direction or other directions instead of the Y direction. Furthermore, p + The configuration pattern of the contact layer can also be different from stripes.
[0076] p + The impurity concentration of the p-type contact layer 325 is higher than that of the p-type semiconductor layer 124. The impurity concentration of the p-type semiconductor layer 124 is not particularly limited, for example, it can be 1 × 10⁻⁶. 17 cm -3 Left and right. p + The impurity concentration of the contact layer 325 is not particularly limited, for example, it is 1×10 18 cm -3 ~1×10 19 cm -3 Left and right. The p-type semiconductor layer 124 is in Schottky contact with the upper electrode 150. In contrast, p... + The contact layer 325 of the type is in contact with the upper electrode 150 ohms.
[0077] In this embodiment, the width L3 in the Y direction of each extension 325a provided in the first region S1a is wider than the width L4 in the Y direction of each extension 325a provided in the second region S1b. Therefore, viewed from above, in the first region S1a, the p provided per unit area + The area of the contact layer 325 of the type is greater than that of the p set per unit area in the second region S1b. + The contact layer 325 has a large area.
[0078] Next, the effects of this implementation method will be explained.
[0079] p in region S1a, which is in 150-ohm contact with the upper electrode + The area per unit area of the contact layer 325 of type 325 is greater than that of the p-type contact layer in the second region S1b with the upper electrode 150 ohms. + The contact layer 325 of this type has a large area per unit area. Therefore, holes can be easily injected from the upper electrode 150 into the n in the first region S1a. - A drift layer 123b of this type is formed. This suppresses bounce. On the other hand, holes are difficult to inject from the upper electrode 150 into the second region S1b. - A drift layer 123b is formed. This reduces the recovery loss in the diode region S1.
[0080] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 300 with low recovery loss while suppressing bounce can be provided.
[0081] Additionally, make p in region 1 + The area per unit area of the contact layer of the type is greater than that of p in the second region. + The method of increasing the area per unit area of the contact layer is not limited to the above description. For example, it is also possible to make the spacing between the multiple extensions in the first region narrower than the spacing between the multiple extensions in the second region, thereby increasing the area of p in the first region. + The area per unit area of the contact layer of the type is greater than that of p in the second region. + The contact layer of this type has a large area per unit area.
[0082] The above describes several embodiments, but they can be combined with each other. For example, the p-type semiconductor layer 224 of the second embodiment can also be applied to the semiconductor device 100 of the first embodiment and the semiconductor device 300 of the third embodiment. Furthermore, the p-type semiconductor layer 224 of the third embodiment can also be applied to the semiconductor device 100 of the first embodiment and the semiconductor device 200 of the second embodiment.+ Type 325 contact layer.
[0083] The implementation methods include the following forms.
[0084] (Postscript 1)
[0085] A semiconductor device having a diode region and an IGBT region, comprising:
[0086] The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region;
[0087] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;
[0088] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;
[0089] The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer. The impurity concentration in the first region of the upper layer, which is located in the diode region and adjacent to the IGBT region, is lower than the impurity concentration in the second region, which is located in the diode region and separated from the IGBT region.
[0090] The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region.
[0091] The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region;
[0092] The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion.
[0093] The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and
[0094] An insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode.
[0095] (Postscript 2)
[0096] Semiconductor devices as described in Appendix 1
[0097] The aforementioned semiconductor section has:
[0098] A fifth semiconductor layer, spanning the diode region and the IGBT region, has a lower impurity concentration than the first semiconductor layer, and is in contact with the third semiconductor layer in the first region of the diode region; and
[0099] The sixth semiconductor layer is disposed in the second region above the fifth semiconductor layer, has an impurity concentration higher than that of the fifth semiconductor layer, and is in contact with the third semiconductor layer.
[0100] (Note 3)
[0101] A semiconductor device having a diode region and an IGBT region, comprising:
[0102] The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region;
[0103] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;
[0104] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;
[0105] The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer;
[0106] The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region. The impurity concentration of the first region located in the diode region and adjacent to the IGBT region is higher than the impurity concentration of the second region located in the diode region and separated from the IGBT region.
[0107] The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region;
[0108] The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion.
[0109] The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and
[0110] An insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode.
[0111] (Note 4)
[0112] A semiconductor device having a diode region and an IGBT region, comprising:
[0113] The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region;
[0114] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;
[0115] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;
[0116] The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer;
[0117] The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region.
[0118] The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region;
[0119] The fifth semiconductor layer of the second conductivity type is disposed on the upper part of the third semiconductor layer in the diode region and has an impurity concentration higher than that of the third semiconductor layer. When viewed from above, the area per unit area of the first region located in the diode region and adjacent to the IGBT region is larger than the area per unit area of the second region located in the diode region and separated from the IGBT region.
[0120] The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion.
[0121] The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and
[0122] An insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode.
[0123] (Note 5)
[0124] Semiconductor devices as described in Appendix 4
[0125] The aforementioned fifth semiconductor layer includes a plurality of extensions that extend in a first direction and are arranged in a second direction intersecting the first direction when viewed from above;
[0126] The width of the extension in the second direction located in the first region is longer than the width of the extension in the second direction located in the second region.
[0127] (Note 6)
[0128] The semiconductor device as described in any one of Appendix 1 to 5,
[0129] The width of the first region in the direction from the diode region toward the IGBT region is shorter than the width of the second region in the direction from the diode region toward the IGBT region.
[0130] The embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.
Claims
1. A semiconductor device comprising a diode region and an IGBT region, wherein the device has: The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region; A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer. The impurity concentration in the first region of the upper layer, which is located in the diode region and adjacent to the IGBT region, is lower than the impurity concentration in the second region, which is located in the diode region and separated from the IGBT region. The impurity concentration in the first region is lower than the impurity concentration in the third region of the upper layer, which is located in the IGBT region. The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region. The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region; The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion. The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and An insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode.
2. The semiconductor device of claim 1, wherein, The aforementioned semiconductor section has: The fifth semiconductor layer is disposed across the diode region and the IGBT region, and has an impurity concentration lower than that of the first semiconductor layer. It is in contact with the third semiconductor layer in the first region of the diode region. as well as The sixth semiconductor layer is disposed above the fifth semiconductor layer in the second and third regions, has a higher impurity concentration than the fifth semiconductor layer, and is in contact with the third semiconductor layer.
3. A semiconductor device comprising a diode region and an IGBT region, wherein the device has: The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region; A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer; The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region. The impurity concentration in the first region located in the diode region and adjacent to the IGBT region is higher than the impurity concentration in the second region located in the diode region and separated from the IGBT region. The first region and the second region are arranged along the first direction and extend in the second direction intersecting the first direction. The impurity concentration in the first region is lower than the impurity concentration in the third region located in the IGBT region. The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region; The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion. The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; and An insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode.
4. A semiconductor device comprising a diode region and an IGBT region, wherein the device has: The first electrode is disposed across the aforementioned diode region and the aforementioned IGBT region; A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The semiconductor portion of the first conductivity type is disposed on the first semiconductor layer and the second semiconductor layer; The third semiconductor layer of the second conductivity type is disposed on the semiconductor portion in the diode region and the IGBT region. The fourth semiconductor layer of the first conductivity type is disposed above the third semiconductor layer in the IGBT region; The fifth semiconductor layer of the second conductivity type is disposed on the upper part of the third semiconductor layer in the diode region and has an impurity concentration higher than that of the third semiconductor layer. When viewed from above, the area per unit area of the first region located in the diode region and adjacent to the IGBT region is larger than the area per unit area of the second region located in the diode region and separated from the IGBT region. The second electrode extends in the IGBT region in the direction from the fourth semiconductor layer toward the semiconductor portion and is adjacent to the fourth semiconductor layer, the third semiconductor layer and the semiconductor portion. The third electrode is located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; A plurality of fourth electrodes extend in the diode region in a direction from the fifth semiconductor layer toward the semiconductor portion, are arranged in a first direction, extend in a second direction intersecting the first direction, and are adjacent to the fifth semiconductor layer, the third semiconductor layer and the semiconductor portion. A first insulating film is disposed between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; and The second insulating film is disposed between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the third semiconductor layer, between the fourth electrode and the semiconductor portion, and between the fourth electrode and the third electrode. The fifth semiconductor layer is in contact with the second insulating film at both ends in the first direction. The aforementioned fifth semiconductor layer includes a plurality of extensions that extend in the aforementioned first direction and are arranged in the aforementioned second direction when viewed from above; The width of the extension in the second direction located in the first region is longer than the width of the extension in the second direction located in the second region.
5. The semiconductor device according to any one of claims 1 to 4, wherein, The width of the first region in the direction from the diode region toward the IGBT region is shorter than the width of the second region in the direction from the diode region toward the IGBT region.
Citation Information
Patent Citations
Ado-resistant cysteamine analogs and uses thereof
JP2021152087A
Semiconductor device
CN103765582A
Semiconductor device
CN105826316A
Semiconductor device and semiconductor device manufacturing method
US20140070270A1