Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which comprises the following steps: firstly, providing a first substrate and a second substrate, wherein the second substrate comprises a second substrate layer, and the first substrate comprises a first substrate layer, a first preliminary top silicon layer and a buried oxygen layer which are sequentially stacked, and the first substrate further comprises a groove which penetrates through the buried oxygen layer and reaches the first preliminary top silicon layer; then, bonding the first substrate and the second substrate by taking the buried oxygen layer and the second substrate layer as a bonding interface, and removing the first substrate layer to obtain an initial semiconductor device; finally, processing the initial semiconductor device by using a GAA technology to obtain a final semiconductor device. The groove penetrates through the buried oxygen layer and reaches the first preliminary top silicon layer, and the position and shape of the groove can be controlled before bonding, so that a first groove with regular appearance can be obtained before the GAA structure is formed, and the reliability and performance of the final semiconductor device obtained after the GAA technology is used for processing are high.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the advent of the 5nm node, higher requirements have been placed on the gate control capability, size and power consumption of transistors. This also means that 3D FinFET (Fin Field Effect Transistor) will reach its limit. The reason is that the fins are too close together, leakage current reappears, and the fins are difficult to keep upright under the action of internal stress after reaching a certain height. All these physical material limitations have led to 3D FinFET gradually withdrawing from the stage of history.

[0003] GAA (Gate All Around) nanotechnology, compared to the current 3D FinFET three-gate structure, redesigns the underlying transistor structure, overcoming the physical and performance limitations of current technology, enhancing gate control, and significantly improving performance. This technology is characterized by achieving a four-sided gate enclosure of the channel. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). This design largely solves various problems arising from reducing the gate pitch, including capacitance effects. Furthermore, with the channel enclosed on all four sides by the gate, channel current flows more smoothly than with the three-sided enclosure of FinFETs. Industry experts estimate that the application of GAA technology can essentially solve the semiconductor manufacturing problems of 5nm and below.

[0004] Existing GAA technology is basically integrated on planar Si by continuously stacking SiGe or Si materials, while there is very little information on SOI (Silicon On Insulator) substrate integration technology, which undoubtedly poses a great challenge to the reliability and performance expansion of SOI MOSFETs.

[0005] Existing techniques for etching an oxide layer beneath the top silicon layer to create trenches cannot achieve good control over the pattern. This is because while wet lateral etching offers good selectivity, it suffers from poor anisotropy, resulting in an arc-shaped etch profile. Figure 1As shown in the figure, if the etching time and rate are not precise, the etched profile will be smaller than the linewidth of the top silicon layer, as shown by the dotted line in the figure. This will result in the failure to obtain a GAA structure. In addition, if the etchant chemical is changed frequently to maintain the same initial etching rate, this will undoubtedly pose a great challenge to profitability and production capacity.

[0006] Therefore, there is an urgent need for a method to integrate GAA structures on SOI substrates to make up for the shortage of SOI MOSFETs in this field and solve the problem of poor device reliability and performance caused by the instability of etching process in the existing technology. Summary of the Invention

[0007] The main objective of this application is to provide a method for fabricating a semiconductor device and a semiconductor device in order to solve the problem of poor reliability and performance of the device caused by the instability of the etching process in the prior art.

[0008] To achieve the aforementioned objective, according to one aspect of this application, a method for fabricating a semiconductor device is provided. The method includes: providing a first substrate and a second substrate, the second substrate including a second substrate layer, the first substrate including a first substrate layer, a first preliminary top silicon layer, and a buried oxide layer stacked sequentially, the first substrate further including a trench extending from the buried oxide layer into the first preliminary top silicon layer; bonding the first substrate and the second substrate using the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and processing the initial semiconductor device using GAA technology to obtain a final semiconductor device.

[0009] Optionally, the initial semiconductor device is processed using GAA technology, including: removing a portion of the first preliminary top silicon layer, with the remaining first preliminary top silicon layer forming a top silicon layer, the top silicon layer including a plurality of top silicon portions and at least one nanowire, each of the top silicon portions being located on the buried oxide layer on both sides of the trench, the two ends of the nanowire contacting the two top silicon portions located on both sides of the trench respectively, and the nanowire being located on the side of the trench away from the second substrate layer; forming a gate structure in the trench, on a partially exposed surface of the buried oxide layer and on a partially exposed surface of the nanowire, the gate structure surrounding a portion of the side surface of the nanowire.

[0010] Optionally, after forming a gate structure in the trench, on the partially exposed surface of the buried oxide layer, and on the partially exposed surface of the nanowire, the method further includes: oxidizing and ion implanting the plurality of top silicon portions respectively to obtain a drain and a source; and ion implanting the exposed nanowire to form an LDD structure.

[0011] Optionally, removing a portion of the first preparatory top silicon layer, with the remaining first preparatory top silicon layer forming the top silicon layer, includes: removing a portion of the first preparatory top silicon layer using electron beam lithography and reactive ion etching processes to obtain the top silicon layer.

[0012] Optionally, a first substrate is provided, comprising: providing a first pre-substrate, the first pre-substrate including a first substrate layer, a second pre-top silicon layer, and a pre-buried oxide layer, the first substrate layer and the second pre-top silicon layer being stacked sequentially, the pre-buried oxide layer covering all exposed surfaces of the first substrate layer and the second pre-top silicon layer; removing a portion of the second pre-top silicon layer and a portion of the pre-buried oxide layer to form a plurality of trenches penetrating a portion of the pre-buried oxide layer into the second pre-top silicon layer, such that the remaining pre-buried oxide layer is located only on the surface of the second pre-top silicon layer away from the first substrate layer, the remaining pre-buried oxide layer forming the buried oxide layer, and the remaining second pre-top silicon layer forming the first pre-top silicon layer, thereby obtaining the first substrate.

[0013] Optionally, a first pre-substrate is provided, comprising: providing a silicon wafer; oxidizing all exposed surfaces of the silicon wafer to form the pre-buried oxide layer, with the remaining silicon wafer forming a first pre-substrate layer; forming a second pre-top silicon layer in the first pre-substrate layer using an ion implantation process, with the remaining first pre-substrate layer forming the first substrate layer, thereby obtaining the first pre-substrate.

[0014] Optionally, after bonding the first substrate and the second substrate, the method further includes: removing the first substrate layer using grinding and polishing processes; etching away a portion of the first preliminary top silicon layer, such that the thickness of the remaining first preliminary top silicon layer is within a predetermined range.

[0015] Optionally, the predetermined range is 12nm-15nm.

[0016] Optionally, the thickness of the buried oxide layer ranges from 140nm to 150nm.

[0017] According to another aspect of this application, a semiconductor device is provided, said semiconductor device being manufactured using any of the methods described.

[0018] According to the technical solution of this application, in the method for fabricating a semiconductor device, firstly, a first substrate and a second substrate are provided. The second substrate includes a second substrate layer. The first substrate includes a first substrate layer, a first pre-top silicon layer, and a buried oxide layer stacked sequentially. The first substrate also includes a trench that extends from the buried oxide layer to the first pre-top silicon layer. Then, the first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces, and the first substrate layer is removed to obtain an initial semiconductor device. Finally, the initial semiconductor device is processed using GAA technology to obtain a final semiconductor device. Compared to existing technologies where the instability of etching processes leads to poor device reliability and performance, the semiconductor device fabrication method of this application provides a first substrate comprising a first substrate layer, a first pre-top silicon layer, a buried oxide layer, and a trench, and a second substrate comprising a second substrate layer. The first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces. Since the trench extends from the buried oxide layer into the first pre-top silicon layer, and the position and shape of the trench can be effectively controlled before bonding, a regular-shaped first trench can be obtained before forming the GAA structure. This avoids the problem in existing technologies where trenches located between the first pre-top silicon layer and the substrate need to be etched through the first pre-top silicon layer during GAA structure formation. The instability of the etching process causes the morphology and contour of the trench to fail to meet expectations, resulting in poor device reliability and performance. Therefore, the method ensures that the final semiconductor device obtained after GAA technology processing has high reliability and performance. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 This diagram illustrates the structure obtained after etching to form trenches in the prior art.

[0021] Figure 2 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0022] Figures 3 to 9 The diagrams show the structural schematics obtained after each process step of the method for fabricating a semiconductor device according to an embodiment of this application.

[0023] Figure 10A schematic diagram of a cross-section of a semiconductor device according to an embodiment of this application is shown.

[0024] The above figures include the following reference numerals:

[0025] 10. First substrate; 20. Second substrate; 30. Gate structure; 40. Drain; 50. Source; 60. LDD structure; 101. First substrate layer; 102. First pre-top silicon layer; 103. Buried oxide layer; 104. Trench; 105. Top silicon layer; 106. Top silicon layer; 107. Nanowire; 108. First pre-substrate; 109. Second pre-top silicon layer; 110. Pre-buried oxide layer; 111. Silicon wafer; 112. First pre-substrate layer; 201. Second substrate layer; 300. Gate oxide layer; 301. Gate. Detailed Implementation

[0026] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0027] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] As described in the background section, the instability of etching processes in the prior art leads to poor device reliability and performance. In order to solve the above problems, this application proposes a method for fabricating a semiconductor device and a semiconductor device.

[0030] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.

[0031] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 2 As shown, the method includes the following steps:

[0032] Step S101, as follows Figure 6 As shown, a first substrate 10 and a second substrate 20 are provided. The second substrate 20 includes a second substrate layer 201. The first substrate 10 includes a first substrate layer 101, a first pre-top silicon layer 102 and a buried oxide layer 103 stacked sequentially. The first substrate 10 also includes a trench 104 that extends from the buried oxide layer 103 into the first pre-top silicon layer 102.

[0033] Step S102, as follows Figure 7 As shown, the buried oxide layer 103 and the second substrate layer 201 are used as bonding interfaces to bond the first substrate 10 and the second substrate 20, and the first substrate layer 101 is removed to obtain an initial semiconductor device.

[0034] Step S103: Process the initial semiconductor device using GAA technology, such as... Figure 9 As shown, the final semiconductor device is obtained.

[0035] In the above-described method for fabricating a semiconductor device, firstly, a first substrate and a second substrate are provided. The second substrate includes a second substrate layer. The first substrate includes a first substrate layer, a first pre-top silicon layer, and a buried oxide layer stacked sequentially. The first substrate also includes a trench that extends from the buried oxide layer into the first pre-top silicon layer. Then, the first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces, and the first substrate layer is removed to obtain an initial semiconductor device. Finally, the initial semiconductor device is processed using GAA technology to obtain a final semiconductor device. Compared to the problems of poor device reliability and performance caused by the instability of etching processes in existing technologies, the semiconductor device fabrication method of this application provides a first substrate including the first substrate layer, the first pre-top silicon layer, the buried oxide layer, and the trench, and then provides a second substrate including the second substrate layer. The first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces. Since the trench extends from the buried oxide layer into the first pre-top silicon layer, and the position and shape of the trench can be effectively controlled before bonding, it ensures that the first trench with a regular morphology can be obtained before the formation of the GAA structure. This avoids the problem in existing technologies where trenches located between the first pre-top silicon layer and the substrate need to be etched through the first pre-top silicon layer during the formation of the GAA structure. Due to the instability of the etching process, the morphology and contour of the trench cannot meet the expected requirements, resulting in poor device reliability and performance. This method ensures that the final semiconductor device obtained after GAA technology processing has high reliability and performance.

[0036] In one specific embodiment, the first substrate and the second substrate are bonded at a high temperature.

[0037] Specifically, in the prior art, the methods for etching the buried oxide layer are relatively simple, mainly focusing on wet etching. This etching is subject to the control of etching rate and time. Therefore, the pattern of the trench formed by etching the buried oxide layer under the top silicon layer using BHF (Buffered Hydro Fluoric) cannot be well controlled. This is mainly because although wet lateral etching has good selectivity, it has poor anisotropy, resulting in an arc-shaped etching profile. If the etching time and rate are not precise, the etching profile will be smaller than the linewidth of the top silicon layer, thus failing to obtain a GAA structure. In addition, if the etchant chemical is changed frequently to maintain the same initial etching rate, it will undoubtedly pose a great challenge to profitability and production capacity. In the fabrication process of the semiconductor device of this application, "embedded voids" are prepared before integrating the GAA structure, that is, the buried oxide layer is etched by dry etching so that a GAA structure with controllable structure and profile can be formed subsequently.

[0038] According to a specific embodiment of this application, the above-mentioned initial semiconductor device is processed using GAA technology, including: as follows Figure 8 As shown, after removing a portion of the first preparatory top silicon layer 102, the remaining first preparatory top silicon layer 102 forms a top silicon layer 105. The top silicon layer 105 includes a plurality of top silicon portions 106 and at least one nanowire 107. Each of the top silicon portions 106 is located on the buried oxide layer 103 on both sides of the trench 104. The two ends of the nanowire 107 are in contact with two of the top silicon portions 106 located on both sides of the trench 104, and the nanowire 107 is located on the side of the trench 104 away from the second substrate layer 201. Figure 9 As shown, a gate structure is formed within the trench 104, on a portion of the exposed surface of the buried oxide layer 103, and on a portion of the exposed surface of the nanowire 107. The gate structure surrounds a portion of the side surface of the nanowire 107. By removing a portion of the first preparatory top silicon layer, multiple top silicon portions and at least one nanowire are obtained, ensuring that the nanowire is located on the side of the trench away from the second substrate layer. After forming the gate structure, the gate structure can wrap around a portion of the nanowire along the predetermined direction, ensuring good control performance of the gate structure over the nanowire, and further ensuring high reliability and performance of the final semiconductor device.

[0039] The aforementioned gate structure includes a gate oxide layer and a gate, such as Figure 9As shown, a gate structure is formed in the trench 104, on a partially exposed surface of the buried oxide layer 103, and on a partially exposed surface of the nanowire 107. This includes: forming a gate oxide layer (not shown) in the trench 104, on a partially exposed surface of the buried oxide layer 103, and on a partially exposed side surface of the nanowire 107; forming the gate on the exposed surface of the gate oxide layer, wherein the gate fills the remaining trench, and a first distance is greater than a second distance, wherein the first distance is the distance between the surface of the gate away from the second substrate 20 and the second substrate 20, and the second distance is the distance between the surface of the nanowire 107 away from the second substrate 20 and the second substrate 20. The gate and the gate oxide layer constitute the gate structure 30.

[0040] Specifically, the nanowires can also be configured as nanosheets. Since the nanowires or nanosheets are included on all four sides by the gate structure, the control capability of the gate structure over the nanowires or nanosheets is improved, which can overcome the physical scaling ratio and performance limitations in the prior art. Specifically, since the channel control capability of the GAA structure is enhanced, it can meet the requirements of certain gate widths. This is mainly reflected in the fact that under the same size structure, the GAA structure provides the possibility for further miniaturization.

[0041] In one specific embodiment, the above-mentioned gate structure is grown by thermal oxidation and LPCVD (Low Pressure Chemical Vapor Deposition), and the above-mentioned GAA structure is formed by photolithography and etching processes.

[0042] According to another specific embodiment of this application, after forming a gate structure in the trench, on the partially exposed surface of the buried oxide layer, and on the partially exposed surface of the nanowire, the method further includes: Figure 9 As shown, multiple top silicon layers 106 are oxidized and ion-implanted to obtain a drain 40 and a source 50; the exposed nanowires 107 are ion-implanted to form an LDD structure 60. By oxidizing and ion-implanting the top silicon layers to obtain the drain and source, and by ion-implanting the exposed nanowires to obtain the LDD structure, the reliability and performance of the final semiconductor device are further ensured.

[0043] Specifically, the LDD structure described above involves setting a low-doped drain region near the drain electrode of the nanowire, allowing the low-doped drain region to withstand a portion of the voltage. This prevents the hot electron degradation effect and further ensures the high reliability and performance of the final semiconductor device.

[0044] In one specific embodiment, along Figure 9The cross section of AA' is as follows Figure 10 As shown, the nanowire 107 is wrapped on all four sides of the gate structure 30. Specifically, the nanowire 107 is wrapped on all four sides of the gate oxide layer 300 and the gate 301 in sequence, and the gate structure is in contact with the second substrate layer 201.

[0045] According to another specific embodiment of this application, removing a portion of the first preliminary top silicon layer, with the remaining first preliminary top silicon layer forming the top silicon layer, includes: removing a portion of the first preliminary top silicon layer using electron beam lithography and reactive ion etching processes to obtain the top silicon layer. By using electron beam lithography and reactive ion etching processes to remove a portion of the first preliminary top silicon layer to obtain the top silicon layer, the nanowires and the top silicon structure can be obtained. This allows the subsequently formed gate structure to wrap a portion of the nanowires along the predetermined direction, resulting in better control performance of the gate structure over the nanowires, further ensuring the high reliability and performance of the final semiconductor device.

[0046] According to a specific embodiment of this application, a first substrate is provided, comprising: as shown in the example... Figure 5 As shown, a first pre-substrate 108 is provided, which includes a first substrate layer 101, a second pre-top silicon layer 109, and a pre-buried oxide layer 110. The first substrate layer 101 and the second pre-top silicon layer 109 are stacked sequentially, and the pre-buried oxide layer 110 covers all exposed surfaces of the first substrate layer 101 and the second pre-top silicon layer 109. Figure 6As shown, a portion of the second pre-top silicon layer 109 and a portion of the pre-buried oxide layer 110 are removed to form a plurality of trenches 104 penetrating from the pre-buried oxide layer 110 to the second pre-top silicon layer 109, such that the remaining pre-buried oxide layer 110 is located only on the surface of the second pre-top silicon layer 109 away from the first substrate layer 101. The remaining pre-buried oxide layer 110 forms the buried oxide layer 103, and the remaining second pre-top silicon layer 109 forms the first pre-top silicon layer 102, thus obtaining the first substrate 10. By providing the first pre-substrate comprising the first substrate layer, the second pre-top silicon layer, and the pre-buried oxide layer, and then removing a portion of the second pre-top silicon layer and a portion of the pre-buried oxide layer, multiple trenches penetrating from the pre-buried oxide layer to the second pre-top silicon layer can be formed. Since the trenches penetrate from the pre-buried oxide layer to the second pre-top silicon layer, and the position and shape of the trenches can be effectively controlled before bonding, it ensures that the first trenches with regular morphology can be obtained before forming the GAA structure. This further avoids the problem in the prior art where trenches located between the first pre-top silicon layer and the substrate need to be etched through the first pre-top silicon layer during the formation of the GAA structure. Due to the instability of the etching process, the morphology and contour of the trenches do not meet the expected requirements, resulting in poor device reliability and performance. This further ensures that the semiconductor device obtained after processing with GAA technology has high reliability and performance.

[0047] Specifically, the trenches are formed by photolithography and one-step dry etching processes. The thickness of the second preparatory top silicon layer is 30 angstroms to 50 angstroms. Then, the photoresist and polymer on the surface are removed by a dry and wet photoresist removal process.

[0048] According to another specific embodiment of this application, a first pre-prepared substrate is provided, comprising: as shown in the figure. Figure 3 As shown, silicon wafer 111 is provided; as Figure 4 As shown, all exposed surfaces of the silicon wafer 111 are oxidized to form the pre-buried oxide layer 110, and the remaining silicon wafer 111 forms the first pre-substrate layer 112; as Figure 5 As shown, the second preliminary top silicon layer 109 is formed in the first preliminary substrate layer 112 using an ion implantation process, and the remaining portion of the first preliminary substrate layer 112 forms the first substrate layer 101, resulting in the first preliminary substrate 108. By oxidizing the silicon wafer to obtain the preliminary buried oxide layer, and then forming the second preliminary top silicon layer in the first preliminary substrate layer using an ion implantation process, the first preliminary substrate is obtained. This ensures that the first preliminary substrate can be easily obtained, thus ensuring a low cost for the semiconductor device.

[0049] Specifically, the oxidation temperature of the silicon wafer is 900-950℃, and the ion implantation process uses boron (B) element, with an ion implantation dose of 10. 17 / cm 2 about.

[0050] According to another specific embodiment of this application, after bonding the first substrate and the second substrate, the method further includes: removing the first substrate layer using a grinding and polishing process; and etching away a portion of the first preliminary top silicon layer, such that the remaining thickness of the first preliminary top silicon layer is within a predetermined range. By removing the first substrate layer through grinding and polishing, and then etching away a portion of the first preliminary top silicon layer, the thickness of the remaining first preliminary top silicon layer is kept within a predetermined range. This ensures that the thickness of the subsequently obtained nanowires and the top silicon portion is within a predetermined range, further guaranteeing the high reliability and performance of the final semiconductor device.

[0051] According to a specific embodiment of this application, the predetermined range is 12nm-15nm.

[0052] According to another specific embodiment of this application, the thickness of the buried oxide layer ranges from 140nm to 150nm.

[0053] In one specific embodiment, after forming the source and drain as described above, inter-level dielectric (ILD), via fabrication, and metal wiring are performed to obtain the final semiconductor device.

[0054] According to an embodiment of this application, a semiconductor device is also provided, which is manufactured using any of the methods described above.

[0055] The aforementioned semiconductor device is fabricated using any of the methods described above. Compared to the prior art, which suffers from poor reliability and performance due to the instability of the etching process, the semiconductor device of this application provides a first substrate comprising the first substrate layer, the first pre-top silicon layer, the buried oxide layer, and the trench, and a second substrate comprising the second substrate layer. The first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces. Since the trench extends from the buried oxide layer into the first pre-top silicon layer, and the position and shape of the trench can be effectively controlled before bonding, it ensures that a regular first trench can be obtained before the formation of the GAA structure. This avoids the prior art where trenches located between the first pre-top silicon layer and the substrate need to be etched through the first pre-top silicon layer during the formation of the GAA structure. Due to the instability of the etching process, the morphology and contour of the trenches do not meet the expected requirements, resulting in poor device reliability and performance. This ensures that the final semiconductor device obtained after GAA technology processing has high reliability and performance.

[0056] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0057] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0058] 1) In the semiconductor device fabrication method described above in this application, firstly, a first substrate and a second substrate are provided. The second substrate includes a second substrate layer. The first substrate includes a first substrate layer, a first pre-top silicon layer, and a buried oxide layer stacked sequentially. The first substrate also includes a trench that extends from the buried oxide layer to the first pre-top silicon layer. Then, the first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces, and the first substrate layer is removed to obtain an initial semiconductor device. Finally, the initial semiconductor device is processed using GAA technology to obtain a final semiconductor device. Compared to the problems of poor device reliability and performance caused by the instability of etching processes in existing technologies, the semiconductor device fabrication method of this application provides a first substrate including the first substrate layer, the first pre-top silicon layer, the buried oxide layer, and the trench, and then provides a second substrate including the second substrate layer. The first substrate and the second substrate are bonded together using the buried oxide layer and the second substrate layer as bonding interfaces. Since the trench extends from the buried oxide layer into the first pre-top silicon layer, and the position and shape of the trench can be effectively controlled before bonding, it ensures that the first trench with a regular morphology can be obtained before the formation of the GAA structure. This avoids the problem in existing technologies where trenches located between the first pre-top silicon layer and the substrate need to be etched through the first pre-top silicon layer during the formation of the GAA structure. Due to the instability of the etching process, the morphology and contour of the trench cannot meet the expected requirements, resulting in poor device reliability and performance. This method ensures that the final semiconductor device obtained after GAA technology processing has high reliability and performance.

[0059] 2) The semiconductor device described in this application is fabricated using any of the above methods. Compared to the prior art, which suffers from poor reliability and performance due to the instability of the etching process, the semiconductor device described in this application provides a first substrate including the first substrate layer, the first pre-top silicon layer, the buried oxide layer, and the trench, and then provides a second substrate including the second substrate layer. The buried oxide layer and the second substrate layer serve as bonding interfaces to bond the first substrate and the second substrate. Since the trench extends from the buried oxide layer to the first pre-top silicon layer, the device achieves superior performance. In the top silicon layer, the position and shape of the trench can be effectively controlled before bonding, ensuring that the first trench with a regular morphology can be obtained before the formation of the GAA structure. This avoids the problem in the prior art where trenches located between the first preparatory top silicon layer and the substrate need to be etched through the first preparatory top silicon layer during the formation of the GAA structure. Due to the instability of the etching process, the morphology and contour of the trench do not meet the expected requirements, resulting in poor device reliability and performance. This ensures that the final semiconductor device obtained after processing with GAA technology has high reliability and performance.

[0060] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A first substrate and a second substrate are provided. The second substrate includes a second substrate layer. The first substrate includes a first substrate layer, a first pre-top silicon layer and a buried oxide layer stacked sequentially. The first substrate also includes a trench that extends from the buried oxide layer to the first pre-top silicon layer. Using the buried oxide layer and the second substrate layer as bonding interfaces, the first substrate and the second substrate are bonded together, and the first substrate layer is removed to obtain an initial semiconductor device. The initial semiconductor device is processed using GAA technology to obtain the final semiconductor device.

2. The method according to claim 1, characterized in that, Processing the initial semiconductor device using GAA technology includes: A portion of the first preparatory top silicon layer is removed, and the remaining first preparatory top silicon layer forms a top silicon layer. The top silicon layer includes a plurality of top silicon portions and at least one nanowire. Each of the top silicon portions is located on the buried oxide layer on both sides of the trench. The two ends of the nanowire are in contact with the two top silicon portions located on both sides of the trench, and the nanowire is located on the side of the trench away from the second substrate layer. A gate structure is formed within the trench, on a partially exposed surface of the buried oxide layer, and on a partially exposed surface of the nanowire, the gate structure surrounding a portion of the side surface of the nanowire.

3. The method according to claim 2, characterized in that, After forming a gate structure within the trench, on the partially exposed surface of the buried oxide layer, and on the partially exposed surface of the nanowire, the method further includes: The multiple top silicon sections are oxidized and ion implanted to obtain drain and source electrodes; The exposed nanowires are ion implanted to form an LDD structure.

4. The method according to claim 2, characterized in that, Removing a portion of the first preparatory top silicon layer, leaving the remaining first preparatory top silicon layer to form the top silicon layer, includes: The first preliminary top silicon layer is removed using electron beam lithography and reactive ion etching processes to obtain the top silicon layer.

5. The method according to claim 1, characterized in that, Provide a first substrate, including: A first pre-substrate is provided, the first pre-substrate comprising a first substrate layer, a second pre-top silicon layer and a pre-buried oxide layer, the first substrate layer and the second pre-top silicon layer being stacked sequentially, and the pre-buried oxide layer covering all exposed surfaces of the first substrate layer and the second pre-top silicon layer; A portion of the second pre-top silicon layer and a portion of the pre-buried oxide layer are removed to form a plurality of trenches penetrating from a portion of the pre-buried oxide layer to the second pre-top silicon layer, such that the remaining pre-buried oxide layer is located only on the surface of the second pre-top silicon layer away from the first substrate layer, the remaining pre-buried oxide layer forms the buried oxide layer, and the remaining second pre-top silicon layer forms the first pre-top silicon layer, thus obtaining the first substrate.

6. The method according to claim 5, characterized in that, Provide a first preparatory substrate, including: Silicon wafers are supplied; All exposed surfaces of the silicon wafer are oxidized to form the pre-buried oxide layer, and the remaining silicon wafer forms the first pre-substrate layer; The second pre-top silicon layer is formed in the first pre-substrate layer using an ion implantation process, and the remaining first pre-substrate layer forms the first substrate layer, thus obtaining the first pre-substrate.

7. The method according to claim 1, characterized in that, After bonding the first substrate and the second substrate, the method further includes: The first substrate layer was removed using grinding and polishing processes; Part of the first preparatory top silicon layer is etched away, so that the thickness of the remaining first preparatory top silicon layer is within a predetermined range.

8. The method according to claim 7, characterized in that, The predetermined range is 12nm-15nm.

9. The method according to any one of claims 1 to 8, characterized in that, The thickness of the buried oxide layer ranges from 140nm to 150nm.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 9.

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