Semiconductor device

Abstract

The distance in the direction along the upper surface of the P-type semiconductor substrate from the first reference position to the end of the P-type diffusion region below the end of the N-type drain region toward the P-type body region is set to be 0.35 MV / cm or less in intensity of the electric field in the region including the end of the N-type drift region and the region between the end of the P-type diffusion region of the P-type diffusion region and the N-type drain region.

Description

Technical Field

[0001] One aspect of the present invention relates to high-voltage transistors, such as LDMOS (Late Rally Diffused MOS) transistors. Background Technology

[0002] As high-voltage MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), various types of MOSFETs are known. For example, LDMOS transistors are devices that achieve both high voltage withstand and low on-resistance, featuring fast switching speed and ease of use in voltage-driven systems. Therefore, LDMOS transistors leverage these characteristics and are used in switching regulators, various drivers, DC-DC converters, etc., becoming key devices in fields requiring high power and high voltage withstand.

[0003] Therefore, LDMOS transistors are required to ensure a high breakdown voltage while maintaining low on-resistance to reduce losses during conduction. However, there is generally a trade-off between breakdown voltage and on-resistance; increasing the breakdown voltage inevitably increases the on-resistance. Consequently, long-term research has been conducted to find a balance between high breakdown voltage and low on-resistance.

[0004] LDMOS transistors have a laterally extended drain region to mitigate electric field concentration between the drain and gate and between the source and drain. Because LDMOS transistors apply a high voltage to the drain region when used with high current, the electric field tends to concentrate at the gate terminal on the drain side and at the source / drain junction. Mitigating this electric field concentration is a useful technique for improving the transistor's breakdown voltage.

[0005] For example, Japanese Patent Application Publication No. 2009-059949 discloses an N-type LDMOS transistor formed in an N-type diffusion region, wherein a P-type diffusion region is disposed below a P-type body region.

[0006] Therefore, the concentration of the electric field is mitigated in the region where the gate overlaps with the LOCOS oxide film. As a result, the breakdown voltage of the LDMOS transistor can be improved. Summary of the Invention

[0007] In the LDMOS transistor structure disclosed in Japanese Patent Application Publication No. 2009-059949, if the P-type diffusion region is extended and positioned below the N-type drift region, the electric field strength between the P-type diffusion region and the N-type drain region is enhanced. As a result, an undesirable situation occurs, such as a decrease in breakdown voltage due to avalanche breakdown.

[0008] One objective of this invention is to realize a semiconductor device that can improve the breakdown voltage of LDMOS transistors and easily avoid breakdown voltage reduction caused by avalanche breakdown.

[0009] To address the aforementioned issues, a semiconductor device according to one aspect of the present invention comprises: a semiconductor substrate of a first conductivity type; a main region of the first conductivity type formed on the surface layer of the semiconductor substrate; a source region of a second conductivity type formed in contact with the main region; a drain region of the second conductivity type formed spaced apart from the main region; a gate formed between the source region and the drain region; a drift region of the second conductivity type formed on the surface layer of the semiconductor substrate in contact with the drain region and having an end between the main region and the drain region; a buried oxide film formed to at least overlap with the end of the gate on the drain region side and buried from the upper surface of the semiconductor substrate, thereby mitigating the electric field; and a first conductivity type... A semiconductor region, formed at a depth deeper than the main body region to contact the bottom surface of the main body region, is formed to extend along the upper surface of the semiconductor substrate. The semiconductor region has a first distance along the upper surface of the semiconductor substrate from a first reference position below the end of the main body region toward the drain region to the end of the semiconductor region, and a second distance along the upper surface of the semiconductor substrate from a second reference position below the end of the drain region on the buried oxide side to the end of the semiconductor region. The electric field strength in the first region including the end of the drift region and the second region between the end of the semiconductor region and the drain region is set to be 0.35 MV / cm or less.

[0010] According to one aspect of the present invention, the breakdown voltage of LDMOS transistors can be improved and the breakdown voltage reduction caused by avalanche breakdown can be easily avoided. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view showing the cross-sectional structure of a semiconductor device according to an embodiment of the present invention. Figure 2 This is a diagram showing the simulated potential distribution of the aforementioned semiconductor device. Figure 3 It is shown in magnification Figure 1 The above potential distribution in region A is shown in the figure. Figure 4 It is shown in magnification Figure 1 The above potential distribution is shown in region B. Figure 5This is a graph showing the relationship between the maximum electric field value and the withstand voltage at two distances relative to the end of a specified P-type diffusion region in the aforementioned semiconductor device. Detailed Implementation

[0012] (Structure of semiconductor device 1) The following is for reference Figures 1 to 5 A specific embodiment of the present invention will be described in detail.

[0013] Figure 1 This is a cross-sectional view showing the cross-sectional structure of a semiconductor device 1 according to an embodiment of the present invention.

[0014] In this embodiment, an N-channel LDMOS transistor (laterally diffused MOS transistor) with a withstand voltage of 60V will be described as semiconductor device 1.

[0015] like Figure 1 As shown, the semiconductor device 1 includes a P-type semiconductor substrate 2 (semiconductor substrate), a P-type diffusion region 3 (semiconductor region), a P-type body region 4 (body region), an N-type drift region 5 (drift region), an N-type source region 6 (source region), a source 6a, a P-type body contact region 7, an N-type drain region 8 (drain region), a drain 8a, a gate 9, a gate insulating film 10, a thick film oxide film 11, and an STI (Shallow Trench Isolation) structure 12.

[0016] In addition, Figure 1 In this design, the layer containing P-type impurities is labeled "p", and the layer containing N-type impurities is labeled "n". Furthermore, layers containing a higher concentration of P-type impurities compared to layers containing "p" are labeled with "p". + In layers containing a high concentration of N-type impurities compared to layers containing "n", "n" is recorded. + ".

[0017] The P-type main body region 4 is P-type (first conductivity type). The P-type main body region 4 is formed by, for example, boron ions (11B). + The ion implantation was performed by injecting the surface layer of a p-type semiconductor substrate 2 with several different accelerating energies (60–500 keV). The ion implantation dose was 1.0E12–1.0E13 / cm². 2 The range. The P-type main body region 4 is formed as a part of it and exposed on the upper surface 2a of the P-type semiconductor substrate 2.

[0018] The P-type diffusion region 3 is P-type. The P-type diffusion region 3 is disposed in the P-type semiconductor substrate 2 at a deep position where its upper surface is in contact with the bottom surface of the P-type main body region 4. The P-type diffusion region 3 is formed to extend from below the P-type main body region 4 along the upper surface 2a of the P-type semiconductor substrate 2 to below the gate insulating film 10, the thick oxide film 11, and the STI structure 12 (described later). The P-type diffusion region 3 is, for example, implanted with boron ions (I1B) at an acceleration energy of 500–5000 keV. + This process is achieved through ion implantation. The ion implantation dose is 5.0E11–5.0E12 / cm². 2 The range.

[0019] The N-type source region 6 is N-type (second conductivity type). The N-type source region 6 is formed on the surface of the P-type semiconductor substrate 2, in contact with the P-type main body region 4, and exposed on the upper surface 2a of the P-type semiconductor substrate 2. The N-type source region 6 is implanted, for example, with phosphorus ions (31P) at an acceleration energy of 35–60 keV. + It is formed by ).

[0020] The P-type main contact region 7 is P-type. The P-type main contact region 7 is formed on the surface layer of the P-type semiconductor substrate 2, in contact with the P-type main contact region 4, and exposed on the upper surface 2a of the P-type semiconductor substrate 2. The P-type main contact region 7 is adjacent to the N-type source region 6. The P-type main contact region 7 is, for example, formed by boron ions (I1B). + It is formed by injecting accelerating energy of 5–30 keV.

[0021] The source electrode 6a is formed on the N-type source electrode region 6 and the P-type host contact region 7.

[0022] The N-type drift region 5 is N-type. The N-type drift region 5 is disposed on the surface layer of the P-type semiconductor substrate 2, closer to the upper surface 2a of the semiconductor substrate than the P-type diffusion region 3. The N-type drift region 5 is formed in contact with the N-type drain region 8. The N-type drift region 5 has an end 5a located between the P-type main region 4 and the N-type drain region 5. The upper surface of the end 5a is exposed on the upper surface 2a of the P-type semiconductor substrate 2. This configuration of the N-type drift region 5 prevents the P-type diffusion region 3, which has a higher concentration, from contacting the N-type drift region 5.

[0023] Furthermore, the impurity concentration in the N-type drift region 5 is lower than that in the N-type drain region 8. The N-type drift region 5 is, for example, implanted with phosphorus ions (31P) at several different acceleration energies (140–540 keV). + It is formed by ion implantation. The dose of ion implantation is in the range of 7.5E11 to 3.5E12 / cm2.

[0024] In addition, during the injection that forms the N-type drift region 5 and the P-type diffusion region 3 respectively, the acceleration energy of each injection is adjusted so that the N-type drift region 5 does not come into contact with the P-type diffusion region 3 in the depth direction.

[0025] The N-type drain region 8 is N-type. The N-type drain region 8 is disposed separately from the P-type body region 4 on the surface layer of the P-type semiconductor substrate 2. The N-type drain region 8 and the N-type source region 6 are formed simultaneously.

[0026] Drain 8a is formed on N-type drain region 8.

[0027] The gate insulating film 10 is formed within the area of ​​the upper surface 2a of the P-type semiconductor substrate 2, the upper surface of the P-type body region 4, and the upper surface of the end of the N-type drift region 5. The gate insulating film 10 is not formed on the upper surface of the N-type source region 6, the P-type body contact region 7, the N-type drain region 8, and the STI structure 12.

[0028] The thick oxide film 11 is formed on the upper surface of the N-type drift region 5, extending from the end of the gate insulating film 10 to the N-type drain region 8 side. As the thick oxide film 11, for example, a LOCOS (Local Oxidation of Silicon) oxide film formed by thermal oxidation, or an oxide film formed by high-temperature oxidation using CVD (Chemical Vapor Deposition) (HTO (High Temperature Oxidation) film) is preferably used. The thick oxide film 11 is provided to mitigate the electric field. The thick oxide film 11 is formed to be thicker than the gate insulating film 10.

[0029] Gate 9 is disposed between N-type source region 6 and N-type drain region 8 on P-type semiconductor substrate 2. Gate 9 is formed on gate insulating film 10 and thick oxide film 11. Therefore, gate 9 is formed such that the upper surface of the portion overlapping with thick oxide film 11 and the portion overlapping with it on gate insulating film 10 is located at a higher position than the upper surface of the other portions. Thus, gate 9 has a step in the middle portion.

[0030] The STI structure 12 is formed such that at least the end of the N-type drain region 8 of the gate 9, separated from the thick oxide film 11, overlaps in the thickness direction of the P-type semiconductor substrate 2. Furthermore, the STI structure 12 is formed to be buried to a predetermined depth from the upper surface 2a of the P-type semiconductor substrate 2 (more precisely, the upper surface of the N-type drain region 8). Additionally, the STI structure 12 is formed within a range from a position slightly offset from the boundary between the gate insulating film 10 and the thick oxide film 11 towards the N-type drain region 8 to the end of the N-type drain region 8. The STI structure 12 is provided for the purpose of mitigating the electric field.

[0031] In addition, in this embodiment, the P-type main body region 4 and the N-type source region 6 are connected at the same potential through the source 6a.

[0032] Here, regarding the P-type diffusion region 3, the position of the end of the P-type diffusion region 3, which defines its extension range, is determined by distance L1 (first distance) and distance L2 (second distance).

[0033] Distance L1 is the distance along the upper surface 2a of the P-type semiconductor substrate 2 from the first reference position P1 to one end of the P-type diffusion region 3, located below the end of the P-type main body region 4 facing the N-type drain region 8. Distance L2 is the distance along the upper surface 2a of the P-type semiconductor substrate 2 from the second reference position P2 to one end of the P-type diffusion region 3, located below the end of the STI structure 12 side of the N-type drain region 8. The sum of distances L1 and L2 is a predetermined value.

[0034] (Operation of semiconductor device 1) Here, the operation of semiconductor device 1 will be explained.

[0035] By applying a positive potential to the P-type body region 4 of the gate 9, a channel is formed between the N-type source region 6 and the N-type drift region 5, specifically in the P-type body region 4 directly below the gate 9 and a portion of the P-type semiconductor substrate 2. As a result, electrons move through the channel along the path from the source 6a to the drain 8a. Consequently, current flows between the source 6a and the drain 8a.

[0036] (Improved voltage withstand capability of semiconductor device 1) In a semiconductor device 1 with a withstand voltage of 60V, a potential distribution was simulated with the source 6a and gate 9 given a GND potential and the drain 8a subjected to a voltage of 60V. In the following description, the case where the sum of the distances L1 and L2 is 3.7μm is considered.

[0037] Figure 2 This is a graph showing the simulated potential distribution based on semiconductor device 1 at distances of 1.2 μm from L1 and 2.5 μm from L2. Figure 3 It is shown in magnification Figure 1 The diagram shows the potential distribution in region A under the above conditions. Figure 4 It is shown in magnification Figure 1 The diagram shows the potential distribution in region B under the above conditions.

[0038] When the distance L1 is 1.2 μm and the distance L2 is 2.5 μm, as follows: Figure 2 as well as Figure 3As shown, the equipotential lines in region A (the first region), which includes the end 5a of the N-type drift region 5, are relatively widely spaced, and the potential distribution in region A is sparse. In contrast, although not shown in the figure, when the distance L1 is -0.3 μm and the distance L2 is 4.0 μm, the spacing of the equipotential lines in region A is narrower than in the case of distance L1 = 1.2 μm and distance L2 = 2.5 μm, and the potential distribution is denser.

[0039] As described above, the potential distribution in region A is relatively sparse when the distance L1 = 1.2 μm and the distance L2 = 2.5 μm. This indicates that the concentration of the electric field in region A is mitigated, and the surface electric field of semiconductor device 1 is also mitigated. This implies an improvement in breakdown voltage. Therefore, by extending the distance L1 to a certain extent, an improvement in the breakdown voltage of region A can be anticipated. When this improvement in breakdown voltage is sufficient, the breakdown voltage of semiconductor device 1 is not determined by the breakdown voltage of region A, but is limited by… Figure 1 The withstand voltage of region B (second region) between the end of the P-type diffusion region 3 and the N-type drain region 8.

[0040] Next, when the distance L1 is 1.2 μm and the distance L2 is 2.5 μm, as... Figure 2 and Figure 4 As shown, the spacing between the equipotential lines in region B becomes wider, indicating that the potential distribution in region B is sparser. In contrast, when the distance L1 is 3.7 μm and the distance L2 is 0 μm, although not shown in the figure, the spacing between the equipotential lines in region B is narrower than in the case where the distance L1 = 1.2 μm and the distance L2 = 2.5 μm, indicating a denser potential distribution.

[0041] As mentioned above, the potential distribution in region B is relatively sparse at distances L1 = 1.2 μm and L2 = 2.5 μm. This indicates that the concentration of the electric field in region B is mitigated. This implies that increasing the distance L2 improves the withstand voltage.

[0042] Given the improved pressure resistance in regions A and B, the desired pressure resistance can be obtained by appropriately setting distances L1 and L2.

[0043] Next, the optimized pressure resistance improvement effect based on the settings of distances L1 and L2 will be explained. Figure 5 This is a graph showing the relationship between the maximum electric field value and the withstand voltage in regions A and B, at distances L1 and L2 relative to the end of the specified P-type diffusion region 3. Figure 5 In the diagram, the upper horizontal axis represents distance L1, the lower horizontal axis represents distance L2, the left vertical axis represents the maximum electric field value, and the right vertical axis represents the withstand voltage. The sum of the values ​​of the opposing distances L1 and L2 on the upper and lower horizontal axes is 3.7 μm.

[0044] like Figure 5 As shown by the solid line, the maximum electric field value indicates a decreasing trend with increasing distance from L1, starting from L1 = -0.3 μm and L2 = 4 μm, reaching its minimum at L1 = 1 μm and L2 = 2.7 μm, and then increasing further with increasing distance from L1. On the other hand, as... Figure 5 As shown by the dashed line, the withstand voltage increases with increasing distance from L1, starting from L1 = -0.3μm and L2 = 4μm, reaching its maximum at L1 = 1μm and L2 = 2.7μm, and then decreases with further increasing distance from L1.

[0045] Based on this relationship between the maximum electric field value and the withstand voltage, the withstand voltage of 60V or higher is determined within the range of combinations of distances L1 and L2 where the maximum electric field value in regions A and B is below 0.35 MV / cm. This range extends from combinations of L1 = -0.2 μm and L2 = 3.9 μm to combinations of L1 = 2.45 μm and L2 = 1.25 μm. The optimal electric field value yields the highest withstand voltage within the combination of L1 = 1 μm and L2 = 2.7 μm.

[0046] Thus, in this embodiment, the electric field strengths of regions A and B are appropriately selected and set to a combination of distances L1 and L2 below 0.35 MV / cm. This easily avoids the reduction in withstand voltage caused by avalanche breakdown in regions A and B, achieving a withstand voltage of 60V or higher.

[0047] Furthermore, this embodiment is not limited to the examples described above, but also includes various modifications. For example, the semiconductor device 1 described above has been given a detailed structure to facilitate understanding of one aspect of the present invention, and is not necessarily limited to having all the structures described. For example, the ion implantation conditions used to form each semiconductor layer are an example and can be appropriately modified.

[0048] In this case, the optimal distances L1 and L2 vary within the range of combinations where their sum is constant and distance L1 is a first lower limit and distance L2 is a second upper limit, and within the range of combinations where distance L1 is the first upper limit and distance L2 is the second lower limit. Specifically, distances L1 and L2 vary within the range of the aforementioned combinations, which is a preferred example, from a combination of L1 = -0.2 μm (first lower limit) and L2 = 3.9 μm (second upper limit) to a combination of L1 = 2.45 μm (first upper limit) and L2 = 1.25 μm (second lower limit). Thus, since distances L1 and L2 can take values ​​from all combinations within the aforementioned range, the optimal distances L1 and L2 can be selected within this range.

[0049] Furthermore, a portion of a structure in one embodiment can be replaced with another structure in another embodiment, or another structure in another embodiment can be added to a structure in one embodiment. Additionally, regarding a portion of the structure in one embodiment, at least one of adding, deleting, or replacing other structures is possible. The semiconductor device 1 of this embodiment, as an example of this, is not limited to an N-channel LDMOS transistor, but can also be a structure applied to a P-channel LDMOS transistor. Furthermore, the voltage withstand capability of the target device is not particularly limited, and the lateral dimensions of each component, including the distances L1 and L2, are not limited. Additionally, the semiconductor device 1 can also have LDD (Light-Doped Diode) implantation, etc., added to its structure for forming other transistors.

[0050] Furthermore, in this embodiment, the semiconductor device 1 (N-channel LDMOS transistor) is formed on a P-type semiconductor substrate 2. However, the P-type semiconductor substrate 2 can also exist as a P-type semiconductor region formed on an N-type epitaxial buried layer. In this case, the source and the P-type semiconductor region can be set to potentials different from those of the P-type semiconductor substrate separated by the N-type epitaxial buried layer. Here, it is assumed that the semiconductor device 1 operates as a high-side switch, in which case the breakdown voltage is defined by the potential difference between the drain and the source.

[0051] Furthermore, in this embodiment, it is presumed that even in the N-channel LDMOS transistor within the N-type diffusion region described in Japanese Patent Application Publication No. 2009-059949, the effects of one aspect of the present invention can be obtained.

[0052] Furthermore, the thick oxide film 11 is configured to be offset further towards the N-type source region 6 than the STI structure 12. As a result, the electric field distribution in region A changes, thus improving the breakdown voltage.

[0053] 〔Summarize〕 The semiconductor device 1 according to Embodiment 1 of the present invention comprises: a semiconductor substrate of a first conductivity type; a main region of the first conductivity type formed on the surface layer of the semiconductor substrate; a source region of a second conductivity type formed in contact with the main region; a drain region of the second conductivity type formed spaced apart from the main region; a gate formed between the source region and the drain region; a drift region of the second conductivity type formed on the surface layer of the semiconductor substrate in contact with the drain region and having an end between the main region and the drain region; a buried oxide film formed to at least overlap with the end of the gate on the drain region side and buried from the upper surface of the semiconductor substrate to mitigate the electric field; and a semiconductor region of the first conductivity type. A semiconductor region is formed at a depth deeper than the main body region to contact the bottom surface of the main body region. The semiconductor region is formed to extend in a direction along the upper surface of the semiconductor substrate, with a first distance along the upper surface of the semiconductor substrate from a first reference position below the end of the main body region toward the drain region to the end of the semiconductor region, and a second distance along the upper surface of the semiconductor substrate from a second reference position below the end of the drain region on the buried oxide side to the end of the semiconductor region. The electric field strength in the first region including the end of the drift region and the second region between the end of the semiconductor region and the drain region is set to be less than 0.35 MV / cm.

[0054] Based on the above structure, a withstand voltage above the desired voltage can be obtained when the electric field strength in the first and second regions is reduced to below 0.35 MV / cm.

[0055] In the semiconductor device according to Embodiment 2 of the present invention, in Embodiment 1 above, the drift region may also be configured at a position closer to the upper surface of the semiconductor substrate than the semiconductor region.

[0056] Based on the above structure, contact between semiconductor regions with higher concentrations and drift regions can be avoided.

[0057] In the semiconductor device involved in the third aspect of the present invention, in the above-described aspects 1 or 2, the sum of the first distance and the second distance may be fixed, and the value may be taken within the following range: from the combination of the first distance being the lower limit of the first distance and the second distance being the upper limit of the second distance, to the combination of the first distance being the upper limit of the first distance and the second distance being the lower limit of the second distance.

[0058] Based on the above structure, it is possible to select the optimal combination of the first distance and the second distance within this range.

[0059] [Additional Items] This invention is not limited to the embodiments described above, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the technical methods disclosed in different embodiments are also included within the technical scope of this invention. Furthermore, new technical features can be formed by combining the technical methods disclosed in each embodiment.

Claims

1. A semiconductor device, characterized in that, have: First conductivity type semiconductor substrate; The main region of the first conductivity type is formed on the surface of the semiconductor substrate; The source region of the second conductivity type is formed in a manner that is connected to the main body region; The drain region of the second conductivity type is formed separately from the main body region; A gate is formed between the source region and the drain region; A drift region of the second conductivity type is formed on the surface of the semiconductor substrate to contact the drain region and has an end between the body region and the drain region; An embedded oxide film is formed to at least overlap with the end of the gate on the drain region side and is embedded from the upper surface of the semiconductor substrate, thereby mitigating the electric field. as well as A semiconductor region of a first conductivity type is formed at a depth greater than the main body region to contact the bottom surface of the main body region. The semiconductor region is formed to extend in a direction along the upper surface of the semiconductor substrate. The first distance is defined as the distance along the upper surface of the semiconductor substrate from a first reference position below the end of the main body region toward the drain region to the end of the semiconductor region. The second distance is defined as the distance along the upper surface of the semiconductor substrate from a second reference position below the end of the buried oxide film side of the drain region to the end of the semiconductor region. The combination of the first distance and the second distance is set such that the electric field strength in the first region containing the end of the drift region and the second region between the end of the semiconductor region and the drain region is below 0.35 MV / cm, and the withstand voltage reduction in the first region and the second region due to avalanche breakdown can be avoided.

2. The semiconductor device as claimed in claim 1, characterized in that, The drift region is positioned closer to the upper surface of the semiconductor substrate than the semiconductor region.

3. The semiconductor device as claimed in claim 1, characterized in that, The sum of the first distance and the second distance is fixed and takes values ​​within the following range: from the first distance being a combination of the lower limit of the first distance and the second distance being a combination of the upper limit of the second distance, to the combination of the upper limit of the first distance and the lower limit of the second distance.

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