Charge-discharge detection circuit and power management chip

Abstract

The application discloses a charging and discharging detection circuit and a power management chip. The charging and discharging detection circuit comprises a voltage biasing module, a high-level comparator and a high-voltage blocking tube. The voltage biasing module is adapted to generate a power rail voltage according to a system voltage. A first input end of the high-level comparator is adapted to receive the system voltage, and a second input end is adapted to receive a battery voltage. The high-level comparator is used for comparing the battery voltage and the system voltage, and outputting a charging indication signal according to a comparison result. The high-voltage blocking tube keeps off state when a voltage difference between the system voltage and the battery voltage is too large, so as to protect an input tube pair of the high-level comparator and improve circuit stability.

Claims

1. A charge / discharge detection circuit, comprising: A voltage biasing module, suitable for generating a power rail voltage based on the system voltage; A high-order comparator has a first input terminal adapted to receive the system voltage and a second input terminal adapted to receive the battery voltage. The high-order comparator is used to compare the battery voltage and the system voltage and output a charging indication signal according to the comparison result. as well as A high-voltage blocking transistor has its gate connected to the power rail voltage, and its drain and source connected to the second input terminal of the high-order comparator and the battery voltage, respectively. The high-voltage blocking transistor is adapted to remain in a turned-off state when the voltage difference between the system voltage and the battery voltage is too large, so as to protect the input transistor in the high-order comparator. The voltage bias module includes: A first Zener diode has a cathode connected to the system voltage and an anode connected to a first bias current; The first NMOS transistor has its drain connected to the system voltage and its gate connected to the anode of the first Zener diode; A first PMOS transistor, whose source is connected to the source of the first NMOS transistor, whose drain is connected to a reference ground, and whose gate is connected to the anode of the first Zener diode; and A first capacitor has a first terminal connected to the system voltage and a second terminal connected to the intermediate node between the first NMOS transistor and the first PMOS transistor. The intermediate node between the first NMOS transistor and the first PMOS transistor is used to provide the power rail voltage.

2. The charge / discharge detection circuit according to claim 1 further includes: The hysteresis control module, connected to the first and second input terminals of the high-order comparator, is adapted to provide different hysteresis voltages according to the state of the charging indication signal.

3. The charge / discharge detection circuit according to claim 1, wherein The high-order comparator includes: A differential input stage is used to receive the system voltage and battery voltage and convert them into current signals; A common-source, common-gate amplifier stage, connected to the differential input stage, is used to obtain a difference signal based on the current signal; and The output stage, connected to the common-source cascode amplifier stage, is used to output the charging indication signal based on the difference signal.

4. The charge / discharge detection circuit according to claim 3, wherein The differential input stage includes: The second and third NMOS transistors are connected in parallel. The gate of the second NMOS transistor serves as the first input terminal of the high-order comparator to receive the system voltage, and the gate of the third NMOS transistor serves as the second input terminal of the high-order comparator to receive the battery voltage. The drains of the second and third NMOS transistors are respectively connected to the common-source, common-gate amplifier stage. The fourth and fifth NMOS transistors are connected sequentially between the common node of the second and third NMOS transistors and the power rail voltage. The fourth and fifth NMOS transistors are used to obtain the third bias current by mirroring.

5. The charge / discharge detection circuit according to claim 4, wherein, The common-source, common-gate amplifier stage includes: second to fifth PMOS transistors and sixth and seventh NMOS transistors. In this configuration, the second PMOS transistor, the fourth PMOS transistor, and the sixth NMOS transistor are sequentially connected to the first branch between the system voltage and the reference ground, and the common node of the second and fourth PMOS transistors is connected to the drain of the second NMOS transistor. The third PMOS transistor, the fifth PMOS transistor, and the seventh NMOS transistor are sequentially connected to the second branch between the system voltage and the reference ground, and the common node of the third and fifth PMOS transistors is connected to the drain of the third NMOS transistor. The gates of the second and third PMOS transistors are used to receive the first bias voltage, and the gates of the fourth and fifth PMOS transistors are used to receive the second bias voltage. The sixth and seventh NMOS transistors form a current mirror, and the drain of the seventh NMOS transistor is used to output the difference signal.

6. The charge / discharge detection circuit according to claim 5, wherein, The output stage includes: sixth and seventh PMOS transistors, eighth to tenth NMOS transistors, and first and second inverters. The sixth PMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are sequentially connected to the third branch between the power supply voltage and the reference ground. The eighth and ninth NMOS transistors are used to obtain the fifth bias current through mirroring. The seventh PMOS transistor and the tenth NMOS transistor are sequentially connected to the fourth branch between the power supply voltage and the reference ground. The seventh PMOS transistor and the sixth PMOS transistor form a current mirror. The gate of the tenth NMOS transistor is connected to the drain of the seventh NMOS transistor. The first and second inverters are connected in sequence to the common node of the seventh PMOS transistor and the tenth NMOS transistor. The output terminal of the first inverter is used to output the inverted signal of the charging indication signal, and the output terminal of the second inverter is used to output the charging indication signal.

7. The charge / discharge detection circuit according to claim 2, wherein, The hysteresis control module includes: A first resistor, the first end of which is connected to the system voltage, and the second end of which is connected to the first input terminal of the high-order comparator; The second resistor has its first end connected to the battery voltage and its second end connected to the source of the high-voltage blocking transistor. The first feedback transistor has its drain connected to the second input terminal of the high-order comparator, its source connected to the fourth bias current, and its gate connected to the inverted signal of the charging indication signal. The second feedback transistor has its drain connected to the first input terminal of the high-order comparator, its source connected to the fourth bias current, and its gate connected to the charging indication signal; and The eleventh and twelfth NMOS transistors are connected sequentially between the sources of the first and second feedback transistors and the reference ground. The eleventh and twelfth NMOS transistors are used to obtain the fourth bias current through mirroring.

8. The charge / discharge detection circuit according to claim 2 further includes: A current bias module is used to provide bias current to the voltage bias module, the high-order comparator, and the hysteresis control module, respectively.

9. The charge / discharge detection circuit according to claim 8, wherein, The current biasing module includes: The first current mirror has a main current port for receiving a reference current, a first replica current port for providing a first bias current to the voltage bias module, a second replica current port for providing a second bias current, and a first power supply port for connection to a reference ground. The second current mirror has a main current port for receiving the second bias current, a third replica current port for providing the third bias current, a second power supply port for connection to the system voltage, and a third power supply port for connection to the power rail voltage.

10. The charge / discharge detection circuit according to claim 9, wherein, The first current mirror and the second current mirror are basic current mirrors.

11. The charge / discharge detection circuit according to claim 10, wherein, The first current mirror and the second current mirror are common-source, common-gate current mirrors.

12. The charge / discharge detection circuit according to claim 11, wherein, The first current mirror and the second current mirror are low-voltage common-source cascode current mirrors.

13. The charge / discharge detection circuit according to claim 12, wherein, The first current mirror includes a third resistor and the thirteenth to eighteenth NMOS transistors. The first end of the third resistor serves as the main current port of the first current mirror and is connected to the reference current. The second end is connected to the drain of the thirteenth NMOS transistor, and the source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor. The drain of the fifteenth NMOS transistor serves as the first replication current port to provide the first bias current, and the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor. The drain of the seventeenth NMOS transistor serves as the second replication current port to provide the second bias current, and the source of the seventeenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor. The sources of the fourteenth, sixteenth, and eighteenth NMOS transistors are connected to the reference ground as the first power supply port. The first end of the third resistor is also connected to the gates of the thirteenth, fifteenth and seventeenth NMOS transistors, and the second end of the third resistor is also connected to the gates of the fourteenth, sixteenth and eighteenth NMOS transistors.

14. The charge / discharge detection circuit according to claim 12, wherein, The second current mirror includes fourth and fifth resistors, eighth to eleventh PMOS transistors, and nineteenth and twentieth NMOS transistors. The sources of the eighth and ninth PMOS transistors are connected to the system voltage as the second power supply port. The drain of the eighth PMOS transistor is connected to the source of the tenth PMOS transistor. The drain of the tenth PMOS transistor is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the second bias current as the main current port of the second current mirror. The drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the eleventh PMOS transistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the drain of the nineteenth NMOS transistor, the source of the nineteenth NMOS transistor is connected to the drain of the twentieth NMOS transistor, and the source of the twentieth NMOS transistor serves as the third current port connected to the power rail voltage. The first terminal of the fourth resistor is also connected to the gates of the eighth and ninth PMOS transistors, and the second terminal of the fourth resistor is also connected to the gates of the tenth and eleventh PMOS transistors. The first end of the fifth resistor is also connected to the gate of the nineteenth NMOS transistor, and the second end of the fifth resistor is also connected to the gate of the twentieth NMOS transistor.

15. The charge / discharge detection circuit according to claim 8, further comprising: A high-voltage clamping module is connected to the voltage biasing module, the current biasing module, the hysteresis control module, and the high-level comparator. The high-voltage clamping module includes multiple high-voltage transistors for protecting the low-voltage transistors in the voltage biasing module, the current biasing module, the hysteresis control module, and the high-level comparator.

16. The charge / discharge detection circuit according to claim 1, further comprising: The second Zener diode has its anode connected to the gate of the high-voltage blocking diode and its cathode connected to the drain of the high-voltage blocking diode.

17. The charge / discharge detection circuit according to claim 1, further comprising: The first and second MOS diodes are respectively connected to the first and second input terminals of the high-order comparator, and the first and second MOS diodes are used to protect the differential input stage of the high-order comparator.

18. A power management chip, wherein, Includes the charge / discharge detection circuit as described in any one of claims 1 to 17.

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