Power management system

Abstract

A power management system is provided, comprising a power factor correction (PFC) circuit and a primary side feedback control (PSR) circuit, wherein the PFC circuit comprises a PFC chip, the PSR circuit comprises a PSR chip, a first chip of the PFC chip and the PSR chip comprises a high-voltage power supply module and a low-power control module, a chip power supply pin of the first chip is connected together with a chip power supply pin or a chip enable pin of a second chip of the PFC chip and the PSR chip, and the low-power control module is configured to control the voltage at the chip power supply pin of the first chip to be less than a chip start voltage or a chip enable voltage of the second chip and greater than a chip start voltage of the first chip by controlling the connection and disconnection of the high-voltage power supply module and the chip power supply pin of the first chip when the power management system is in a system idle state or a protection state.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to a power management system. Background Technology

[0002] Power management systems are an essential component of electronic devices, typically requiring two or more chips to achieve complex functions and superior performance. For power management systems used in LED lighting systems, power consumption under no-load and protection states is a crucial performance indicator. Each chip usually needs to reduce its power consumption to meet the overall low-power requirements of the system, which significantly increases the complexity of low-power chip design and thus increases chip design costs. Summary of the Invention

[0003] According to an embodiment of the present invention, a power management system includes a power factor correction (PFC) circuit and a primary-side feedback control (PSR) circuit. The PFC circuit includes a PFC chip, and the PSR circuit includes a PSR chip. A first chip in the PFC chip and the PSR chip includes a high-voltage power supply module and a low-power control module. The power supply pin of the first chip is connected to the power supply pin or enable pin of the second chip in the PFC chip and the PSR chip. The low-power control module is configured to control the voltage at the power supply pin of the first chip to be less than the chip startup voltage or the chip enable voltage of the second chip and greater than the chip startup voltage of the first chip when the power management system is in a system no-load or protection state by controlling the connection and disconnection of the high-voltage power supply module and the chip power supply pin of the first chip. Attached Figure Description

[0004] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein:

[0005] Figure 1 The circuit schematic of a traditional dual-chip power management system is shown.

[0006] Figure 2 An example circuit diagram of a dual-chip power management system according to an embodiment of the present invention is shown.

[0007] Figure 3 It shows Figure 2 The waveform of the voltage at the VDD pin of the PSR chip in the dual-chip power management system is shown.

[0008] Figure 4 Another example circuit diagram of a dual-chip power management system according to an embodiment of the present invention is shown.

[0009] Figure 5 It shows Figure 4The waveform of the voltage at the VDD pin of the PSR chip in the dual-chip power management system is shown.

[0010] Figure 6 It shows Figure 2 and Figure 4 The example circuit implementation of the high-voltage power supply module and the low-power control module is shown.

[0011] Figure 7 It shows Figure 6 The waveform diagrams of multiple signals in the low-power control module are shown.

[0012] Figure 8 A flowchart of a low-power control method used in a dual-chip power management system according to an embodiment of the present invention is shown. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention.

[0014] Figure 1 The circuit schematic of a traditional dual-chip power management system is shown. (Example) Figure 1 As shown, the dual-chip power management system 100 can be applied in LED lighting systems and may include a PFC circuit 102 and a PSR circuit 104. The PFC circuit 102 includes an inductor L1, a freewheeling diode D1, an output capacitor Cout, a power switch MOS1, and a PFC chip, which are used to achieve the high power factor characteristics of the entire system. The PSR circuit 104 includes an inductor L2, a freewheeling diode D2, a power switch MOS2, and a PSR chip, which are used to achieve the constant current output characteristics of the entire system.

[0015] Figure 1The dual-chip power management system 100 shown typically needs to exhibit low overall system power consumption when the system is in an idle or protection state, for example, less than 0.5W. Traditionally, to achieve low overall system power consumption, each chip must implement low power consumption and constantly detect when the system is under load or exiting protection (e.g., each chip's power consumption needs to be less than 0.25W), or a communication port needs to be added between each chip to enable other chips to enter a low-power standby state when one chip detects an idle or protection state. However, the low-power design or communication port design for each chip increases the chip design complexity and thus increases the chip design cost.

[0016] In view of one or more of the above problems, a power management system according to an embodiment of the present invention is proposed, which can reduce the design complexity of the chips used therein, thereby reducing the design cost of the chips, while achieving lower overall system standby power consumption.

[0017] Figure 2 An example circuit diagram of a dual-chip power management system according to an embodiment of the present invention is shown. Figure 2 As shown, the dual-chip power management system 200 can be applied in LED lighting systems and may include a PFC circuit 202 and a PSR circuit 204, wherein: the PFC circuit 202 includes a PFC chip, and the PSR circuit 204 includes a PSR chip; the PSR chip includes a high-voltage power supply module 2042 and a low-power control module 2044; the chip power supply pin (i.e., VDD pin) of the PSR chip and the chip enable pin (i.e., ENA pin) of the PFC chip are connected together; and the low-power control module 2044 is configured to control the voltage at the VDD pin of the PSR chip to be less than the chip enable voltage of the PFC chip and greater than the chip startup voltage of the PSR chip by controlling the connection and disconnection of the high-voltage power supply module 2042 and the VDD pin of the PSR chip when the dual-chip power management system 200 is in a system no-load or protection state.

[0018] exist Figure 2 In the dual-chip power management system 200 shown, when the PSR chip detects a system no-load or protection state, the low-power control module 2044 controls the voltage at the VDD pin of the PSR chip to be less than the chip enable voltage of the PFC chip and greater than the chip startup voltage of the PSR chip, so that the PFC chip is in a completely off state and the PSR chip is in a low-power standby state. In this way, when the dual-chip power management system 200 is in a system no-load or protection state, it can meet the overall low-power requirements of the system while also eliminating the need for low-power chip design.

[0019] In some embodiments, the low-power control module 2044 is further configured to control the voltage at the VDD pin of the PSR chip to be greater than the chip enable voltage of the PFC chip by controlling the connection and disconnection of the high-voltage power supply module 2042 and the VDD pin of the PSR chip when the dual-chip power management system 200 is in normal operation.

[0020] It should be understood that the other aspects of the circuit composition and connection relationships of PFC circuit 202 and PSR circuit 204 are similar to those of PFC circuit 202 and PSR circuit 204. Figure 1 The dual-chip power management system 100 shown here will not be described in detail.

[0021] Figure 3 It shows Figure 2 The waveform of the voltage at the VDD pin of the PSR chip in the dual-chip power management system is shown. (Combined with...) Figure 2 and Figure 3 As can be seen, when the dual-chip power management system 200 is in normal operation, the voltage at the VDD pin of the PSR chip is higher than the chip enable voltage of the PFC chip (e.g., within the normal operating voltage range of both the PFC and PSR chips). Therefore, the voltage at the VDD pin of the PSR chip does not affect the operation of the PFC chip. When the PSR chip detects a system no-load or protection state, the low-power control module 2044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip enable voltage of the PFC chip but higher than the chip startup voltage of the PSR chip (e.g., decreasing and maintaining within the voltage range V1-V2 during system no-load or protection states). This completely shuts down the PFC chip, resulting in almost no power consumption. The PSR chip does not restart and remains in a low-power operating state for an extended period to detect when the system is under load or exits the protection state. Therefore, when the dual-chip power management system 200 is in a system no-load or protection state, the overall system power consumption is the power consumption of the PSR chip in its low-power operating state.

[0022] Figure 4 Another example circuit diagram of a dual-chip power management system according to an embodiment of the present invention is shown. Figure 4 The dual-chip power management system 400 shown is... Figure 2The difference between the dual-chip power management system 200 shown is as follows: 1) The VDD pin of the PFC chip and the VDD pin of the PSR chip are connected together; 2) When the dual power management system 400 is in a system no-load or protection state, the low-power control module 4044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip startup voltage of the PFC chip and higher than the chip startup voltage of the PSR chip, so that the PFC chip is in a completely off state and the PSR chip is in a low-power standby state; and 3) When the dual-chip power management system 400 is in a normal operating state, the low-power control module 4044 controls the voltage at the VDD pin of the PSR chip to be greater than the chip startup voltage of the PFC chip.

[0023] Figure 5 It shows Figure 4 The waveform of the voltage at the VDD pin of the PSR chip in the dual-chip power management system is shown. (Combined with...) Figure 4 and Figure 5 As can be seen, when the dual-chip power management system 400 is in normal operation, the voltage at the VDD pin of the PSR chip is within the normal operating voltage range of both the PSR chip and the PFC chip, and both the PSR chip and the PFC chip are operating normally. When the PSR chip detects a system no-load or protection state, the low-power control module 4044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip startup voltage of the PFC chip but higher than the chip startup voltage of the PSR chip (e.g., decreasing and maintaining it within the voltage range V1-V2 when the system is in no-load or protection state), so that the PFC chip is in a completely off state and therefore consumes almost no power. The PSR chip will not restart and remains in a low-power operating state for a long time to detect when the system is under load or exits the protection state. Therefore, when the dual-chip power management system 400 is in a system no-load or protection state, the overall system power consumption is the power consumption of the PSR chip in a low-power operating state.

[0024] Figure 6 It shows Figure 2 and Figure 4 The example circuit implementation of the high-voltage power supply module and the low-power control module is shown. Figure 6 As shown, the voltage at the VDD pin of the PSR chip is generated by the high-voltage power supply module 602 charging the chip power supply capacitor Cvdd; the low-power control module 604 is configured to control the connection and disconnection of the high-voltage power supply module 602 and the VDD pin of the PSR chip by controlling the on and off of the switching transistor M1 located between the high-voltage power supply module 602 and the VDD pin of the PSR chip (and control the connection and disconnection of the high-voltage power supply module 602 and the chip power supply capacitor Cvdd).

[0025] like Figure 6As shown, in some embodiments, the low-power control module 604 is further configured to: control the switching transistor M1 to turn on and off by comparing the voltage at the first circuit node fb1 between the VDD pin of the PSR chip and ground with the first and second reference voltages Vref1 and Vref2 when the dual-chip power management system 200 / 400 is in a system no-load or protection state; and / or control the switching transistor M1 to turn on and off by comparing the voltage at the second circuit node fb2 between the VDD pin of the PSR chip and ground with the first and second reference voltages Vref1 and Vref2 when the dual-chip power management system 200 / 400 is in a normal operating state.

[0026] like Figure 6 As shown, in some embodiments, control signal A is used to control the on and off of switch M1; control signal Control is used to characterize whether the dual-chip power management system 200 / 400 is in a system no-load or protection state; when the dual-chip power management system 200 / 400 is in a system no-load or protection state, control signal Control is high, control signal Controlb (which is the inverted signal of control signal Control) is low, operational amplifier amp compares the voltage at the first circuit node fb1 with the first and second reference voltages Vref1 and Vref2, and outputs control signal A to control the on and off of switch M1, ultimately controlling the VDD pin of the PSR chip. The voltage is maintained within the voltage range V1-V2 when the dual-chip power management system 200 / 400 is in a no-load or protection state, thereby completely shutting it off through the ENA or VDD pin of the PFC chip. When the dual-chip power management system 200 / 400 is in normal operation, the control signal Control is low and the control signal Controlb is high. The operational amplifier amp compares the voltage at the second circuit node fb2 with the first and second reference voltages Vref1 and Vref2, and outputs the control signal A to control the switching transistor M1 to turn on and off, ultimately controlling the voltage at the VDD pin of the PSR chip to be within the normal operating voltage range of the PFC chip and the PSR chip.

[0027] Figure 7 It shows Figure 6 The waveforms of multiple signals in the low-power control module are shown below. Combined with... Figure 6 and Figure 7It can be seen that when the dual-chip power management system 200 / 400 enters the system no-load or protection state, the control signal Control jumps from low level to high level, the switching transistor M4 changes from off to on, and the switching transistor M3 changes from on to off. The operational amplifier amp compares the voltage at the first circuit node fb1 with the first and second reference voltages Vref1 and Vref2 and outputs the control signal A to control the on and off of the switching transistor M1. Finally, it controls the voltage at the VDD pin of the PSR chip to remain within the voltage range V when the dual-chip power management system 200 / 400 is in the system no-load or protection state. Within 1-V2, the PFC chip is in a completely off state and the PSR chip is in a low-power operating state. When the dual-chip power management system 200 / 400 is in normal operation, the control signal Control is low, the switch M4 is off, the switch M3 is on, the operational amplifier amp compares the voltage at the second circuit node fb2 with the first and second reference voltages Vref1 and vref2 and outputs the control signal A to control the on and off of the switch M1, and finally controls the voltage at the VDD pin of the PSR chip to be within the normal operating voltage range of the PFC chip and the PSR chip.

[0028] Combination Figure 6 and Figure 7 As can be seen, in some embodiments, the low-power control module 604 is further configured to: control the switch M1 to be in the off state during the process of the voltage at the first circuit node fb1 increasing from the second reference voltage Vref2 to the first reference voltage Vref1; and / or control the switch M1 to be in the on state during the process of the voltage at the first circuit node fb1 decreasing from the first reference voltage Vref1 to the second reference voltage Vref2.

[0029] Combination Figure 6 and Figure 7 As can be seen, in some embodiments, the low-power control module 604 is further configured to control the switch 1 to be in the off state during the process of the voltage at the second circuit node fb2 increasing from the second reference voltage Vref2 to the first reference voltage Vref1; and / or to control the switch M1 to be in the on state during the process of the voltage at the second circuit node fb2 decreasing from the first reference voltage Vref1 to the second reference voltage Vref2.

[0030] Combination Figure 6 and Figure 7 As can be seen, in some embodiments, the low-power control module 604 is further configured to control the switch M1 to switch from the off state to the on state when the dual-chip power management system 200 / 400 switches from the normal operation state to the system no-load or protection state.

[0031] Figure 8A flowchart illustrating a low-power power control method employed in a dual-chip power management system according to an embodiment of the present invention is shown. Figure 8 As shown, when the dual-chip power management system 200 / 400 is in a system no-load or protection state, the low-power control module 204 / 404 controls the voltage at the VDD pin of the PSR chip to be reduced to a range that is lower than the chip enable voltage or chip start-up voltage of the PFC chip but higher than the chip start-up voltage of the PSR chip. This keeps the PSR chip in a low-power standby state and detects in real time when the system is under load or exits the protection state. The PFC chip is in a completely off state and therefore consumes almost no power.

[0032] Those skilled in the art should understand that, in the case where the PFC chip includes a high-voltage power supply module, a low-power control module can also be added inside it, and the voltage at the VDD pin of the PFC chip can be used as the input of the ENA pin or VDD pin of the PSR chip. Similar operations can be adopted to achieve overall low power consumption of the dual-chip power management system 200 / 400 when the system is in no-load or protection state.

[0033] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. A power management system, comprising a PFC circuit and a PSR circuit, wherein, The PFC circuit includes a PFC chip, and the PSR circuit includes a PSR chip, characterized in that: The first chip in the PFC chip and the PSR chip includes a high-voltage power supply module and a low-power control module. The power supply pin of the first chip is connected to the power supply pin or enable pin of the second chip in the PFC chip and the PSR chip, wherein the first chip is the PFC chip and the second chip is the PSR chip, or the first chip is the PSR chip and the second chip is the PFC chip. The low-power control module is configured to, when the power management system is in a system no-load or protection state, control the connection and disconnection between the high-voltage power supply module and the chip power supply pin of the first chip, so that the voltage at the chip power supply pin of the first chip is less than the chip startup voltage or chip enable voltage of the second chip and greater than the chip startup voltage of the first chip.

2. The power management system as described in claim 1, characterized in that, The low-power control module is further configured to, when the power management system is in normal working condition, control the connection and disconnection between the high-voltage power supply module and the chip power supply pin of the first chip, thereby controlling the voltage at the chip power supply pin of the first chip to be greater than the chip startup voltage or chip enable voltage of the second chip.

3. The power management system as described in claim 2, characterized in that, The low-power control module is further configured to control the connection and disconnection of the high-voltage power supply module and the chip power supply pin of the first chip by controlling the on and off of the switching transistor located between the high-voltage power supply module and the chip power supply pin of the first chip.

4. The power management system as described in claim 3, characterized in that, The low-power control module is further configured to control the switching transistor located between the high-voltage power supply module and the chip power supply pin of the first chip when the power management system is in a system no-load or protection state by comparing the voltage at the first circuit node between the chip power supply pin of the first chip and ground with a first reference voltage and a second reference voltage.

5. The power management system as described in claim 4, characterized in that, The low-power control module is further configured to control the switching transistor located between the high-voltage power supply module and the chip power supply pin of the first chip by comparing the voltage at the second circuit node between the chip power supply pin of the first chip and ground with the first and second reference voltages when the power management system is in normal operation.

6. The power management system as described in claim 4, characterized in that, The low-power control module is further configured to control the switch located between the high-voltage power supply module and the chip power supply pin of the first chip to be in a turned-off state during the process of the voltage at the first circuit node increasing from the second reference voltage to the first reference voltage.

7. The power management system as described in claim 4, characterized in that, The low-power control module is further configured to control the switching transistor located between the high-voltage power supply module and the chip power supply pin of the first chip to be in a conducting state during the process of the voltage at the first circuit node decreasing from the first reference voltage to the second reference voltage.

8. The power management system as described in claim 5, characterized in that, The low-power control module is further configured to control the switch located between the high-voltage power supply module and the chip power supply pin of the first chip to be in a turned-off state during the process of the voltage at the second circuit node increasing from the second reference voltage to the first reference voltage.

9. The power management system as described in claim 5, characterized in that, The low-power control module is further configured to control the switch located between the high-voltage power supply module and the chip power supply pin of the first chip to be in a conducting state during the process of the voltage at the second circuit node decreasing from the first reference voltage to the second reference voltage.

10. The power management system as described in claim 5, characterized in that, The low-power control module is further configured to control the switch located between the high-voltage power supply module and the chip power supply pin of the first chip to switch from the off state to the on state when the power management system switches from the normal operation state to the system no-load or protection state.

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