PWM wave generation and duty cycle control methods, systems, timers, and storage media

Abstract

This application provides a PWM wave generation and duty cycle control method, comprising the following steps: obtaining the first state duty cycle of the three-phase signal; obtaining the second state duty cycle of the three-phase signal after commutation; determining the maximum count value of the MCU timer; configuring the timer for the three-phase signal in the first state based on the first state duty cycle and the maximum count value of the MCU timer; configuring the timer for the three-phase signal in the second state based on the second state duty cycle and the maximum count value of the MCU timer; generating a PWM waveform with a specific duty cycle based on the timer for the three-phase signal in the first state and the timer for the three-phase signal in the second state. The PWM wave generated by this application can be used to detect whether a short circuit has occurred in the three-phase signal, reducing the number of inrush current occurrences and protecting the safety of the inverter power module; it has low computational complexity, high reliability, and is easy to implement in software; the PWM wave output in each phase within a single cycle is centrally symmetrical, which helps to reduce the generation of harmonic currents.

Description

Technical Field

[0001] This application belongs to the field of pulse width modulation technology, and in particular relates to a PWM wave generation and duty cycle control method, system, timer and storage medium. Background Technology

[0002] In a brushless DC motor control system, a microcontroller unit (MCU) applies control signals to the switching transistors of the upper and lower arms of the three-phase inverter, causing the three-phase inverter bridge to output three-phase pulse width modulation (PWM) signals with controllable widths to the three-phase motor, driving the motor to rotate in a specified direction and speed. The ratio of the PWM signal's on-time to the period time within a single cycle is called the PWM duty cycle. The magnitude of the PWM duty cycle determines the power; for example, when controlling the motor's speed, a larger PWM duty cycle results in a faster motor speed.

[0003] In practical applications, motors may experience phase-to-phase or turn-to-turn short circuits due to prolonged overload or overvoltage operation. Multiple large inrush currents generated in a short period can damage the upper and lower bridge arms of the motor inverter and pose a safety hazard to the entire brushless DC motor control system. While motor drivers are typically designed with hardware overcurrent protection circuits, the response time of these circuits is in the microsecond range. If the phase-to-phase conduction time is shorter than the response time of the hardware overcurrent protection circuit, it cannot be triggered immediately, still resulting in a short circuit fault between the three phase pulses.

[0004] Therefore, how to generate a PWM signal with a specific duty cycle to ensure that the phase-to-phase conduction time is not less than the response time of the hardware overcurrent protection circuit, thereby protecting the driver and compressor from damage, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a PWM wave generation and duty cycle control method, system, timer, and storage medium for generating PWM signals with a specific duty cycle to avoid phase-to-phase short circuit faults.

[0006] In a first aspect, this application provides a PWM wave generation and duty cycle control method, comprising the following steps: obtaining the first state duty cycle of a three-phase signal; obtaining the second state duty cycle of the three-phase signal after commutation; determining the maximum count value of an MCU timer; configuring a timer for the three-phase signal in the first state based on the first state duty cycle and the maximum count value of the MCU timer; configuring a timer for the three-phase signal in the second state based on the second state duty cycle and the maximum count value of the MCU timer; and generating a PWM waveform with a specific duty cycle based on the timer for the three-phase signal in the first state and the timer for the three-phase signal in the second state.

[0007] The PWM wave generated by this application can be used to detect whether a short circuit has occurred in the three-phase signal, reducing the number of inrush current occurrences and protecting the safety of the inverter power module.

[0008] In one implementation of the first aspect, obtaining the first state duty cycle of the three-phase signal includes calculating the first state duty cycle of the three-phase signal using the following formula when current flows into the second and third phases and out of the first phase:

[0009] Duty_AH1 = 50% - t1 / T;

[0010] Duty_BH1 = 50% + t1 / T;

[0011] Duty_CH1 = 50% + t1 / T;

[0012] Where t1 is the shortest phase-to-phase conduction time in the first state; T is the carrier period; Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; and Duty_CH1 is the duty cycle of the third phase in the first state.

[0013] In one implementation of the first aspect, obtaining the second state duty cycle of the three-phase signal after commutation includes calculating the second state duty cycle of the three-phase signal using the following formula when current flows into the first and third phases and out of the second phase:

[0014] Duty_AH2 = 50% + t2 / T;

[0015] Duty_BH2 = 50% - t2 / T;

[0016] Duty_CH2 = 50% + t2 / T;

[0017] Where t2 is the shortest phase-to-phase conduction time in the second state; T is the carrier period; Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; and Duty_CH2 is the duty cycle of the third phase in the second state.

[0018] In one implementation of the first aspect, the first state duty cycle and the second state duty cycle of the three-phase signal are the upper arm duty cycles of the three-phase signal.

[0019] In one implementation of the first aspect, determining the maximum value of the MCU timer count includes calculating the maximum value of the MCU timer count using an up-down counting mode.

[0020] In one implementation of the first aspect, configuring the timer for the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the first state using the following formula:

[0021] CMPValue_A1=TCRmax*(1-Duty_AH1);

[0022] CMPValue_B1=TCRmax*(1-Duty_BH1);

[0023] CMPValue_C1=TCRmax*(1-Duty_CH1);

[0024] Where Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; Duty_CH1 is the duty cycle of the third phase in the first state; TCRmax is the maximum count value of the MCU timer; CMPValue_A1 is the timer for the first phase in the first state; CMPValue_B1 is the timer for the second phase in the first state; and CMPValue_C1 is the timer for the third phase in the first state.

[0025] In one implementation of the first aspect, configuring the timer for the three-phase signal in the second state based on the duty cycle of the second state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the second state using the following formula:

[0026] CMPValue_A2=TCRmax*(1-Duty_AH2);

[0027] CMPValue_B2=TCRmax*(1-Duty_BH2);

[0028] CMPValue_C2=TCRmax*(1-Duty_CH2);

[0029] Where Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; Duty_CH2 is the duty cycle of the third phase in the second state; TCRmax is the maximum count value of the MCU timer; CMPValue_A2 is the timer for the first phase in the second state; CMPValue_B2 is the timer for the second phase in the second state; and CMPValue_C2 is the timer for the third phase in the second state.

[0030] In this implementation, a PWM wave can be generated based on the minimum trigger time of the hardware overcurrent circuit obtained from the frequency converter. It has low computational load, high reliability, and is easy to implement in software.

[0031] Secondly, this application provides a PWM wave generation and duty cycle control system, comprising:

[0032] The first acquisition module is used to acquire the first state duty cycle of the three-phase signal;

[0033] The second acquisition module is used to acquire the second state duty cycle of the three-phase signal after commutation;

[0034] The counter module is used to determine the maximum count value of the MCU timer;

[0035] The first configuration module is used to configure the timer of the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer;

[0036] The second configuration module is used to configure the timer of the three-phase signal in the second state based on the duty cycle of the second state and the maximum value of the MCU timer count;

[0037] The PWM wave generation module is used to generate a PWM waveform with a specific duty cycle based on the timers of the three-phase signals in the first state and the second state.

[0038] Thirdly, this application provides a timer, characterized in that it includes: a processor and a memory;

[0039] The memory is used to store computer programs;

[0040] The processor is used to execute the computer program stored in the memory to cause the timer to perform the PWM wave generation and duty cycle control method described above.

[0041] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when executed by a processor, the program implements the PWM wave generation and duty cycle control method as described in any of the preceding claims.

[0042] As described above, the PWM wave generation and duty cycle control method, system, timer, and storage medium described in this application have the following beneficial effects:

[0043] (1) The generated PWM wave can be used to detect whether a short circuit has occurred in the three-phase signal, reducing the number of inrush current occurrences and protecting the safety of the inverter power module;

[0044] (2) The minimum time for triggering the hardware overcurrent circuit based on the frequency converter can generate a PWM wave, which has low computational load, high reliability, and is easy to implement in software.

[0045] (3) Each phase of the PWM wave output within a single cycle is centrally symmetrical, which helps to reduce the generation of harmonic current. Attached Figure Description

[0046] Figure 1 The flowchart shown is a PWM wave generation and duty cycle control method described in an embodiment of this application.

[0047] Figure 2 The diagram shown is a schematic of a three-phase upper bridge PWM in the first state of the PWM wave generation and duty cycle control method described in the embodiments of this application.

[0048] Figure 3 The diagram shown is a schematic of a three-phase upper bridge PWM in the second state of the PWM wave generation and duty cycle control method described in the embodiments of this application.

[0049] Figure 4 The diagram shows a PWM waveform with a specific duty cycle generated by a timer in the PWM waveform generation and duty cycle control method described in the embodiments of this application.

[0050] Figure 5 The diagram shown is a schematic diagram of the PWM wave generation and duty cycle control system structure described in an embodiment of this application.

[0051] Figure 6 The diagram shown is a schematic diagram of the timer structure described in an embodiment of this application.

[0052] Component designation explanation

[0053] 5. PWM Wave Generation and Duty Cycle Control System

[0054] 51 First Acquisition Module

[0055] 52 Second Acquisition Module

[0056] 53 Counter Module

[0057] 54 First Configuration Module

[0058] 55 Second Configuration Module

[0059] 56 PWM Wave Generation Module

[0060] 6 Timers

[0061] 61 processor

[0062] 62 Memory

[0063] 63 Multimedia Components

[0064] 64 I / O interfaces

[0065] 65 Communication Components

[0066] Steps S1 to S6 Detailed Implementation

[0067] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0068] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0070] The following embodiments of this application provide a PWM wave generation and duty cycle control method, system, timer, and storage medium for use as timers and counters in MCU chips, including but not limited to PWM wave signal generators. PWM control of drivers typically employs seven-segment SVPWM, which generates symmetrical PWM waveforms with the advantage of low current harmonic content. This application generates PWM waves based on seven-segment SVPWM, and the generated PWM waves can be used to detect whether a short circuit has occurred in the three-phase signal, reducing the frequency of inrush currents and protecting the safety of the inverter power module.

[0071] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0072] like Figure 1 As shown, this embodiment provides a method for PWM wave generation and duty cycle control, including the following steps:

[0073] S1. Obtain the first state duty cycle of the three-phase signal.

[0074] The driver's three-phase bridge inverter circuit includes six IGBT (Insulated Gate Bipolar Transistor) power switches, presented in a three-phase half-bridge structure with three sets of bridge arms. Each set of bridge arms has an upper and lower arm corresponding to a switching element. The three-phase current of the motor is controlled by controlling the switching states of the bridge arms. For example, the six power switches are denoted as UH, UL, VH, VL, WH, and WL. UH-UL, VH-VL, and WH-WL constitute three sets of switches. The first set of switches, UH-UL, controls the U phase; the second set, VH-VL, controls the V phase; and the third set, WH-WL, controls the W phase.

[0075] In one embodiment, obtaining the first state duty cycle of the three-phase signal includes calculating the first state duty cycle of the three-phase signal using the following formula when current flows into the second and third phases and out of the first phase:

[0076] Duty_AH1 = 50% - t1 / T;

[0077] Duty_BH1 = 50% + t1 / T;

[0078] Duty_CH1 = 50% + t1 / T;

[0079] Where t1 is the shortest phase-to-phase conduction time in the first state; T is the carrier period; Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; and Duty_CH1 is the duty cycle of the third phase in the first state.

[0080] In the embodiments of this application, the first phase can correspond to any one of the U phase, V phase, and W phase, and the second phase can correspond to any one of the remaining two phases besides the first phase. For example, when the first phase is the U phase and the second phase is the V phase, then the third phase is the W phase.

[0081] like Figure 2 As shown, assuming the carrier period T = 250µs and the shortest phase-to-phase conduction time t1 = 10µs, that is, 10µs is sufficient to trigger the hardware overcurrent protection circuit to generate a protection signal. When current flows in from phases V and W and flows out from phase U, the first state duty cycle of the three-phase signal can be obtained using the above formula as follows:

[0082] Duty_UH1=50%-10 / 250=46%;

[0083] Duty_VH1=50%+10 / 250=54%;

[0084] Duty_WH1=50%+10 / 250=54%.

[0085] During motor startup, if the three-phase signal is continuously output for two to three cycles at the aforementioned duty cycle, the conduction time between the UV phases and between the UW phases can be guaranteed to be at least 10µs. This ensures that if a short circuit occurs between the UV phases or between the UW phases, the hardware overcurrent protection circuit will have sufficient time to trigger protection and simultaneously feed back a fault signal to the driver, informing the user of the short circuit fault.

[0086] In one embodiment, the shortest phase-to-phase conduction time or the shortest time required to trigger hardware overcurrent protection can be obtained through a frequency converter.

[0087] S2. Obtain the second state duty cycle of the three-phase signal after commutation.

[0088] In one embodiment, obtaining the second state duty cycle of the three-phase signal after commutation includes calculating the second state duty cycle of the three-phase signal using the following formula when current flows into the first and third phases and out of the second phase:

[0089] Duty_AH2 = 50% + t2 / T;

[0090] Duty_BH2 = 50% - t2 / T;

[0091] Duty_CH2 = 50% + t2 / T;

[0092] Where t2 is the shortest phase-to-phase conduction time in the second state; T is the carrier period; Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; and Duty_CH2 is the duty cycle of the third phase in the second state.

[0093] like Figure 3 As shown, assuming the carrier period T = 250µs and the shortest phase-to-phase conduction time t2 = 10µs, that is, 10µs is sufficient to trigger the hardware overcurrent protection circuit to generate a protection signal. When current flows in from phases U and W and flows out from phase V, the second state duty cycle of the three-phase signal can be obtained using the above formula as follows:

[0094] Duty_UH1=50%+10 / 250=54%;

[0095] Duty_VH1=50%-10 / 250=46%;

[0096] Duty_WH1=50%+10 / 250=54%.

[0097] During motor startup, if the three-phase signals are continuously output for two to three cycles at the aforementioned duty cycle, the conduction time between phases VU and VW can be guaranteed to be at least 10µs. This ensures that if a short circuit occurs between phases VU or VW, the hardware overcurrent protection circuit will have sufficient time to trigger protection and simultaneously feed back a fault signal to the driver, informing the user of the short circuit fault.

[0098] In one embodiment, the first state duty cycle and the second state duty cycle of the three-phase signal are the upper arm duty cycles of the three-phase signal.

[0099] In a three-phase bridge inverter circuit, each upper bridge arm and its corresponding lower bridge arm in the three bridge arms are turned on alternately. That is, when the upper bridge arm power transistor in each group is in the on state, the lower bridge arm power transistor is in the off state. Moreover, the duty cycles of the upper and lower bridge arms in the same group are complementary. For example, when the duty cycles of the three-phase upper bridge arms UH, VH, and WH are Duty_UH, Duty_VH, and Duty_WH, respectively, the duty cycles of the three-phase lower bridge arms UL, VL, and WL are (100% - Duty_UH), (100% - Duty_VH), and (100% - Duty_WH), respectively.

[0100] It should be noted that the embodiment of this application obtains the duty cycle of the three-phase signal on the upper bridge arm. Similarly, obtaining the duty cycle of the three-phase signal on the lower bridge arm in other embodiments can also be used to solve the technical problem of this application and is also within the scope of protection of this application.

[0101] S3. Determine the maximum value of the MCU timer count.

[0102] In one embodiment, determining the maximum value of the MCU timer count includes calculating the maximum value of the MCU timer count using an up-down counting mode.

[0103] Specifically, in the upward and downward counting mode, the maximum count value of the MCU timer is calculated using the formula TCRmax = 1 / 2 * (f_timer / f_pwm); where f_timer is the counting frequency of the MCU timer; f_pwm is the carrier frequency; and TCRmax is the maximum count value of the MCU timer.

[0104] For example, when the counting frequency of the MCU timer is f_timer = 1000MHz and the carrier frequency is f_pwm = 4KHz, the maximum count value of the MCU timer is TCRmax = 1 / 2 * (1000MHz / 4KHz) = 12500.

[0105] S4. Configure the timer for the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer.

[0106] In one embodiment, configuring the timer for the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the first state using the following formula:

[0107] CMPValue_A1=TCRmax*(1-Duty_AH1);

[0108] CMPValue_B1=TCRmax*(1-Duty_BH1);

[0109] CMPValue_C1=TCRmax*(1-Duty_CH1);

[0110] Where Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; Duty_CH1 is the duty cycle of the third phase in the first state; TCRmax is the maximum value of the MCU timer count; CMPValue_A1 is the timer for the first phase in the first state; CMPValue_B1 is the timer for the second phase in the first state; and CMPValue_C1 is the timer for the third phase in the first state. CMPValue_A1, CMPValue_B1, and CMPValue_C1 are used to compare with the timer count TCR.

[0111] For example, assuming the carrier period T = 250µs, the shortest phase-to-phase conduction time t1 = 10µs, the MCU timer counting frequency f_timer = 1000MHz, and the carrier frequency f_pwm = 4kHz, where the carrier frequency f_pwm and the carrier period T are reciprocals, the timer for the three-phase signal in the first state can be obtained using the above formula:

[0112] CMPValue_U1=12500*(1-46%)=6750;

[0113] CMPValue_V1=12500*(1-54%)=5750;

[0114] CMPValue_W1=12500*(1-54%)=5750.

[0115] S5. Configure the timer for the three-phase signal in the second state based on the duty cycle of the second state and the maximum count value of the MCU timer.

[0116] In one embodiment, configuring the timer for the three-phase signal in the second state based on the duty cycle of the second state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the second state using the following formula:

[0117] CMPValue_A2=TCRmax*(1-Duty_AH2);

[0118] CMPValue_B2=TCRmax*(1-Duty_BH2);

[0119] CMPValue_C2=TCRmax*(1-Duty_CH2);

[0120] Where Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; Duty_CH2 is the duty cycle of the third phase in the second state; TCRmax is the maximum value of the MCU timer count; CMPValue_A2 is the timer for the first phase in the second state; CMPValue_B2 is the timer for the second phase in the second state; and CMPValue_C2 is the timer for the third phase in the second state. CMPValue_A1, CMPValue_B1, and CMPValue_C1 are used for comparison with the timer count TCR.

[0121] For example, assuming the carrier period T = 250µs, the shortest phase-to-phase conduction time t2 = 10µs, the MCU timer counting frequency f_timer = 1000MHz, and the carrier frequency f_pwm = 4kHz, where the carrier frequency f_pwm and the carrier period T are reciprocals, the timer for the three-phase signal in the second state can be obtained using the above formula:

[0122] CMPValue_U2=12500*(1-54%)=5750;

[0123] CMPValue_V2=12500*(1-46%)=6750;

[0124] CMPValue_W2 = 12500 * (1 - 54%) = 5750.

[0125] In this implementation, the PWM wave can be generated based on the minimum time triggered by the hardware overcurrent circuit obtained from the frequency converter, with small computational complexity, high reliability, and easy software implementation.

[0126] S6. Generate a PWM waveform with a specific duty cycle based on the timers of the three-phase signals in the first state and the timers of the three-phase signals in the second state.

[0127] In one embodiment, within a single cycle, generating a PWM waveform with a specific duty cycle based on the timers of the three-phase signals in the first state includes the following steps:

[0128] S61. When the count value TCR of the MCU timer is 0, synchronize the count values of the three timers in the first state.

[0129] Specifically, taking any one of the three phases as a reference, if the count value TCR1 of the MCU timer of this phase is 0, then force the count values TCR2 = 0 and TCR3 = 0 of the other two phases, so as to ensure that the three-phase count values are completely synchronized without phase shift.

[0130] S62. During the rising stage of counting, output the levels of the upper and lower arms of the three phases.

[0131] Specifically, during the rising stage of counting, if the TCR of any one phase < CMPValue, the upper arm of this phase outputs a low level and the lower arm outputs a high level; if TCR >= CMPValue, the upper arm outputs a high level and the lower arm outputs a low level.

[0132] S63. During the falling stage of counting, output the levels of the upper and lower arms of the three phases.

[0133] Specifically, during the falling stage of counting, if the TCR of any one phase >= CMPValue, the upper arm of this phase outputs a high level and the lower arm outputs a low level; if TCR < CMPValue, the upper arm outputs a low level and the lower arm outputs a high level.

[0134] As Figure 4 shown, within a single PWM cycle, the count value TCR of the timer increases from zero to TCRmax and then decreases from TCRmax to zero, thereby generating a triangular carrier wave. In this implementation, each phase of the PWM wave output within a single cycle is centrosymmetric, which helps to reduce the generation of harmonic currents.

[0135] Similarly, according to the above execution steps, a PWM waveform with a specific duty cycle can be generated based on the timers of the three-phase signals in the second state, which will not be elaborated here.

[0136] It should be noted that the protection scope of the PWM wave generation and duty cycle control method described in the embodiments of this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the protection scope of this application.

[0137] like Figure 5 As shown, this embodiment provides a PWM wave generation and duty cycle control system, including:

[0138] The first acquisition module 51 is used to acquire the first state duty cycle of the three-phase signal.

[0139] The second acquisition module 52 is used to acquire the second state duty cycle of the three-phase signal after commutation.

[0140] Counter module 53 is used to determine the maximum count value of the MCU timer.

[0141] The first configuration module 54 is used to configure the timer of the three-phase signal in the first state based on the duty cycle of the first state and the maximum value of the MCU timer count.

[0142] The second configuration module 55 is used to configure the timer of the three-phase signal in the second state based on the duty cycle of the second state and the maximum value of the MCU timer count.

[0143] The PWM wave generation module 56 is used to generate a PWM waveform with a specific duty cycle based on the timer of the three-phase signal in the first state and the timer of the three-phase signal in the second state.

[0144] It should be noted that the structure and principle of the first acquisition module 51, the second acquisition module 52, the counter module 53, the first configuration module 54, the second configuration module 55 and the PWM wave generation module 56 correspond one-to-one with the steps and embodiments in the above-mentioned PWM wave generation and duty cycle control method, so they will not be repeated here.

[0145] The PWM wave generation and duty cycle control system provided in this application can realize the PWM wave generation and duty cycle control method described in this application. However, the implementation device of the PWM wave generation and duty cycle control method described in this application includes, but is not limited to, the structure of the PWM wave generation and duty cycle control system listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principles of this application are included within the protection scope of this application.

[0146] like Figure 6 As shown, this embodiment provides a timer, including a processor and a memory.

[0147] The memory 62 is used to store computer programs.

[0148] The processor 61 is used to execute the computer program stored in the memory to cause the timer to perform the PWM wave generation and duty cycle control method described above.

[0149] Preferably, the processor 61 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The memory 62 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0150] This embodiment also includes one or more of a multimedia component 63, an input / output (I / O) interface 64, and a communication component 65.

[0151] The multimedia component 63 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 62 or transmitted via communication component 65. The audio component also includes at least one speaker for outputting audio signals. I / O interface 64 provides an interface between processor 61 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 65 is used for wired or wireless communication between the timer and other devices. Wireless communication may include Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination thereof; therefore, the corresponding communication component 505 may include a Wi-Fi module, a Bluetooth module, or an NFC module.

[0152] In one embodiment, the timer may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the PWM wave generation and duty cycle control methods described above.

[0153] This application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when the program is executed by a processor, it implements the PWM wave generation and duty cycle control method described in any of the above claims.

[0154] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. This available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0155] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0156] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0157] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0158] This application embodiment may also provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application embodiment are generated. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0159] When the computer program product is executed by a computer, the computer performs the method described in the foregoing method embodiments. The computer program product can be a software installation package; when the foregoing method is required, the computer program product can be downloaded and executed on the computer.

[0160] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0161] In summary, the PWM wave generation and duty cycle control method, system, timer, and storage medium of this application can be used to detect whether a short circuit has occurred in the three-phase signal, reducing the number of inrush current occurrences and protecting the safety of the inverter power module. The PWM wave can be generated based on the minimum trigger time of the hardware overcurrent circuit obtained from the frequency converter, which has low computational load, high reliability, and is easy to implement in software. The PWM wave output of each phase in a single cycle is centrally symmetrical, which helps to reduce the generation of harmonic currents.

[0162] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for generating and controlling the duty cycle of a PWM wave, characterized in that, Includes the following steps: Obtain the first state duty cycle of the three-phase signal; After commutation, the second state duty cycle of the three-phase signal is obtained; Determine the maximum count value of the MCU timer; Configure the timer for the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer; Configure the timer for the three-phase signal in the second state based on the duty cycle of the second state and the maximum count value of the MCU timer; Based on the timer of the three-phase signal in the first state and the timer of the three-phase signal in the second state, a PWM waveform with a specific duty cycle is generated; The timer generating a PWM waveform with a specific duty cycle based on the three-phase signals in the first state includes: When the MCU timer count value is equal to 0, synchronize the three-phase timer count value in the first state; During the counting rise phase, if the timer count value TCR of any phase is less than CMPValue, the upper bridge arm of that phase outputs a low level and the lower bridge arm outputs a high level; if TCR is greater than or equal to CMPValue, the upper bridge arm outputs a high level and the lower bridge arm outputs a low level. During the count-down phase, if the timer count value TCR of any phase is greater than or equal to CMPValue, the upper bridge arm of that phase outputs a high level and the lower bridge arm outputs a low level; if TCR is less than CMPValue, the upper bridge arm outputs a low level and the lower bridge arm outputs a high level; CMPValue is the timer value for that phase signal. The timer generating a PWM waveform with a specific duty cycle based on the three-phase signals in the second state includes: When the MCU timer count value is equal to 0, synchronize the three-phase timer count value in the second state; During the counting rise phase, if the timer count value TCR of any phase is less than CMPValue, the upper bridge arm of that phase outputs a low level and the lower bridge arm outputs a high level; if TCR is greater than or equal to CMPValue, the upper bridge arm outputs a high level and the lower bridge arm outputs a low level. During the count-down phase, if the timer count value TCR of any phase is greater than or equal to CMPValue, the upper bridge arm of that phase outputs a high level and the lower bridge arm outputs a low level; if TCR is less than CMPValue, the upper bridge arm outputs a low level and the lower bridge arm outputs a high level; CMPValue is the timer value for that phase signal.

2. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, Obtaining the first-state duty cycle of the three-phase signal involves calculating the first-state duty cycle of the three-phase signal using the following formula when current flows into the second and third phases and out of the first phase: Duty_AH1 = 50% - t1 / T; Duty_BH1 = 50% + t1 / T; Duty_CH1 = 50% + t1 / T; Where t1 is the shortest phase-to-phase conduction time in the first state; T is the carrier period; Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; Duty_CH1 is the duty cycle of the third phase in the first state.

3. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, The second state duty cycle of the three-phase signal after commutation is obtained by calculating the second state duty cycle of the three-phase signal using the following formula when current flows into the first and third phases and flows out of the second phase: Duty_AH2 = 50% + t2 / T; Duty_BH2 = 50% - t2 / T; Duty_CH2 = 50% + t2 / T; Where t2 is the shortest phase-to-phase conduction time in the second state; T is the carrier period; Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; Duty_CH2 is the duty cycle of the third phase in the second state.

4. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, The duty cycle of the first state and the duty cycle of the second state of the three-phase signal are the duty cycles of the upper arm of the three-phase signal.

5. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, Determining the maximum value of the MCU timer count includes calculating the maximum value of the MCU timer count using an up-down counting mode.

6. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, Configuring the timer for the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the first state using the following formula: CMPValue_A1= TCRmax * (1 - Duty_AH1); CMPValue_B1= TCRmax * (1 - Duty_BH1); CMPValue_C1= TCRmax * (1 - Duty_CH1); Where Duty_AH1 is the duty cycle of the first phase in the first state; Duty_BH1 is the duty cycle of the second phase in the first state; Duty_CH1 is the duty cycle of the third phase in the first state; TCRmax is the maximum count value of the MCU timer; CMPValue_A1 is the timer for the first phase in the first state; CMPValue_B1 is the timer for the second phase in the first state; and CMPValue_C1 is the timer for the third phase in the first state.

7. The PWM wave generation and duty cycle control method according to claim 1, characterized in that, Configuring the timer for the three-phase signal in the second state based on the duty cycle of the second state and the maximum count value of the MCU timer includes configuring the timer for the three-phase signal in the second state using the following formula: CMPValue_A2 = TCRmax * (1 - Duty_AH2); CMPValue_B2 = TCRmax * (1 - Duty_BH2); CMPValue_C2 = TCRmax * (1 - Duty_CH2); Where Duty_AH2 is the duty cycle of the first phase in the second state; Duty_BH2 is the duty cycle of the second phase in the second state; Duty_CH2 is the duty cycle of the third phase in the second state; TCRmax is the maximum count value of the MCU timer; CMPValue_A2 is the timer for the first phase in the second state; CMPValue_B2 is the timer for the second phase in the second state; and CMPValue_C2 is the timer for the third phase in the second state.

8. A PWM wave generation and duty cycle control system, characterized in that, include: The first acquisition module is used to acquire the first state duty cycle of the three-phase signal; The second acquisition module is used to acquire the second state duty cycle of the three-phase signal after commutation; The counter module is used to determine the maximum count value of the MCU timer; The first configuration module is used to configure the timer of the three-phase signal in the first state based on the duty cycle of the first state and the maximum count value of the MCU timer; The second configuration module is used to configure the timer of the three-phase signal in the second state based on the duty cycle of the second state and the maximum value of the MCU timer count; The PWM wave generation module is used to generate a PWM waveform with a specific duty cycle based on the timer of the three-phase signal in the first state and the timer of the three-phase signal in the second state. The PWM waveform generation module generates a PWM waveform with a specific duty cycle based on the timer of the three-phase signal in the first state, including: When the MCU timer count value is equal to 0, synchronize the three-phase timer count value in the first state; During the counting rise phase, if the timer count value TCR of any phase is less than CMPValue, the upper bridge arm of that phase outputs a low level and the lower bridge arm outputs a high level; if TCR is greater than or equal to CMPValue, the upper bridge arm outputs a high level and the lower bridge arm outputs a low level. During the count-down phase, if the timer count value TCR of any phase is greater than or equal to CMPValue, the upper bridge arm of that phase outputs a high level and the lower bridge arm outputs a low level; if TCR is less than CMPValue, the upper bridge arm outputs a low level and the lower bridge arm outputs a high level; CMPValue is the timer value for that phase signal. The PWM wave generation module generates a PWM waveform with a specific duty cycle based on the timer of the three-phase signal in the second state, including: When the MCU timer count value is equal to 0, synchronize the three-phase timer count value in the second state; During the counting rise phase, if the timer count value TCR of any phase is less than CMPValue, the upper bridge arm of that phase outputs a low level and the lower bridge arm outputs a high level; if TCR is greater than or equal to CMPValue, the upper bridge arm outputs a high level and the lower bridge arm outputs a low level. During the count-down phase, if the timer count value TCR of any phase is greater than or equal to CMPValue, the upper bridge arm of that phase outputs a high level and the lower bridge arm outputs a low level; if TCR is less than CMPValue, the upper bridge arm outputs a low level and the lower bridge arm outputs a high level; CMPValue is the timer value for that phase signal.

9. A timer, characterized in that, include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory to cause the timer to perform the PWM wave generation and duty cycle control method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the PWM wave generation and duty cycle control method as described in any one of claims 1 to 7.

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