Multi-core oscillator with enhanced mode robustness

Abstract

The present invention relates to a multi-core oscillator with enhanced mode robustness. The present invention relates to a voltage controlled oscillation circuit comprising a plurality of cores and a plurality of mode or gain boosters coupled between the plurality of cores. To prevent an undesired mode of operation of the voltage controlled oscillation circuit from dominating a desired mode of operation (e.g., an in-phase mode of operation or an out-of-phase mode of operation), the mode boosters can increase a desired gain of the desired mode of operation and decrease an undesired gain of the undesired mode of operation. Specifically, a mode booster coupled to a terminal of a core associated with the desired mode of operation can be enabled, while a mode booster coupled to a terminal of a core associated with the undesired mode of operation can be disabled.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 245,470, filed September 17, 2021, entitled “MULTI-CORE OSCILLATOR WITH ENHANCED MODE ROBUSTNESS,” the disclosure of which is incorporated herein by reference in its entirety for all purposes. Background Technology

[0003] This disclosure relates in general to wireless communication, and more specifically to improving the performance of wireless communication.

[0004] In an electronic device, a transceiver may be coupled to one or more antennas to enable the electronic device to transmit and receive wireless signals. The transceiver may include a local oscillator with voltage-controlled oscillation circuitry that generates a local oscillator signal. The local oscillator signal may be mixed with a data signal to upconvert the data signal (e.g., upconvert to a higher frequency or radio frequency) to generate a transmit signal to be transmitted via one or more antennas, or to downconvert a receive signal received via one or more antennas (e.g., downconvert to a lower frequency or baseband frequency) to generate a data signal.

[0005] In some cases, a voltage-controlled oscillator circuit may include multiple cores (e.g., each core is coupled to a corresponding inductor and provides a corresponding terminal for the signal output from the corresponding core) and operate in multiple modes to generate signals with different frequencies. However, in some cases, when the voltage-controlled oscillator circuit operates in the desired mode, another undesired mode may dominate the desired mode, resulting in the voltage-controlled oscillator circuit outputting a signal with undesired frequency and / or undesired phase noise. Summary of the Invention

[0006] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects not set forth below.

[0007] In one embodiment, the voltage-controlled oscillator circuit includes a first core having a first inductor, a first positive terminal, and a first negative terminal. The voltage-controlled oscillator circuit also includes a second core having a second inductor, a second positive terminal, and a second negative terminal. The voltage-controlled oscillator circuit further includes: a first-mode boost converter coupling the first positive terminal of the first core to the second positive terminal of the second core; a second-mode boost converter coupling the first negative terminal of the first core to the second positive terminal of the second core; a third-mode boost converter coupling the first positive terminal of the first core to the second negative terminal of the second core; and a fourth-mode boost converter coupling the first negative terminal of the first core to the second negative terminal of the second core.

[0008] In another embodiment, a method includes receiving at a processing circuit an indication of an operating mode for a voltage-controlled oscillator circuit having a plurality of cores and a plurality of gain boosters coupled between the cores. The method further includes enabling, via the processing circuit, a first set of gain boosters disposed between the cores based on the operating mode. Additionally, the method includes disabling, via the processing circuit, a second set of gain boosters disposed between the cores based on the operating mode.

[0009] In yet another embodiment, the electronic device includes a transceiver having a voltage-controlled oscillator circuit comprising a plurality of cores and a plurality of mode boost converters coupled between the cores. The electronic device also includes processing circuitry that operates the mode boost converters to increase the desired gain of a desired operating mode of the cores and decrease the undesired gain of an undesired operating mode of the cores.

[0010] Various modifications to the above-described features may exist with respect to various aspects of the invention. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, various features discussed below relating to one or more illustrated embodiments may be incorporated individually or in any combination into any of the above aspects of the invention. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of the embodiments disclosed herein and does not limit the claimed subject matter. Attached Figure Description

[0011] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0012] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure; Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic devices; Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the transmitter of an electronic device; Figure 4 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the receiver of an electronic device; Figure 5 It refers to two core components with identical operation according to the implementation scheme of this disclosure. Figure 1 A schematic diagram of a portion of the voltage-controlled oscillator (VCO) circuit of an electronic device; Figure 6 It refers to two core components with out-of-phase operation according to the implementation scheme of this disclosure. Figure 5 A partial schematic diagram of the VCO circuit; Figure 7 It is a mode booster having a coupling between two cores according to an embodiment of this disclosure. Figure 1 A circuit diagram of a portion of the VCO circuit of an electronic device; Figure 8 An embodiment according to this disclosure is shown. Figure 7 Circuit diagram of the mode boost converter; Figure 9A It is a transconductance amplifier in the form of a voltage input and a current output according to an embodiment of this disclosure. Figure 8 Circuit diagram of the mode boost converter; Figure 9B It is a transimpedance amplifier with current input and voltage output according to an embodiment of this disclosure. Figure 8 Circuit diagram of the mode boost converter; Figure 9C It is a voltage amplifier in the form of a voltage input and a voltage output according to an embodiment of this disclosure. Figure 8 Circuit diagram of the mode boost converter; Figure 9D It is a current amplifier in the form of a current input and a current output according to an embodiment of this disclosure. Figure 8 Circuit diagram of the mode boost converter; Figure 10 It operates in the same mode according to the implementation scheme of this disclosure. Figure 7 The VCO circuit section; Figure 11 This illustrates the implementation of the present disclosure when operating in in-phase mode. Figure 10 The equivalent half-circuit model of the expected non-inverting mode startup gain of the core VCO circuit. Figure 12This illustrates the implementation of the present disclosure when operating in in-phase mode. Figure 10 The equivalent half-circuit model of the startup gain of the core of the VCO circuit in the undesirable out-of-phase mode. Figure 13 It operates in an out-of-phase mode according to the implementation scheme of this disclosure. Figure 7 The VCO circuit section; Figure 14 This is a flowchart of a method for increasing the gain of a desired mode and decreasing the gain of an undesired mode according to an embodiment of this disclosure; Figure 15A The four-core and mode booster described herein operates in a first mode (e.g., mode 0) according to an embodiment of this disclosure. Figure 1 Exemplary specific implementation of the VCO circuit of an electronic device; Figure 15B It operates in a second mode (e.g., mode 1) according to the embodiments of this disclosure. Figure 15A Exemplary specific implementation of the VCO circuit; Figure 15C It operates in a third mode (e.g., mode 2) according to the embodiments of this disclosure. Figure 15A Exemplary specific implementation of the VCO circuit; Figure 15D It operates in a fourth mode (e.g., mode 3) according to the embodiments of this disclosure. Figure 15A Exemplary specific implementation of the VCO circuit; Figure 16 It shows that there is none. Figure 7 The diagram shows the operation curves of the VCO circuit of the boost converter. Figure 17 This illustrates an embodiment according to this disclosure. Figures 15A to 15D A graph illustrating the specific operation of an example VCO circuit; and Figure 18 It is a boost converter with N cores and corresponding modes according to the implementation scheme of this disclosure. Figure 1 A representative diagram of the VCO circuit of an electronic device. Detailed Implementation

[0013] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0014] When describing elements of various embodiments of this disclosure, the articles “a” and “the” are intended to refer to one or more of the elements present. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms “generally,” “approximately,” “about,” “close to,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). Furthermore, it should be understood that any exact values, figures, measurements, etc. provided herein may be envisioned as approximations of such exact values, figures, measurements, etc. (e.g., within limits of suitable or conceivable error).

[0015] Reducing or minimizing phase noise in wireless signals transmitted or received by wireless communication devices can lead to lower data error vector amplitude, improved spectral purity, and ultimately superior performance. Since the implementation of resonators with on-chip inductors and capacitors can be limited by the quality factor on lossy silicon substrates, multi-core architectures are a promising approach, particularly for fifth-generation (5G) millimeter-wave (mmWave) applications. Theoretically, phase noise can be reduced to 10 using N coupled oscillators. log 10 (N) one-third.

[0016] Specifically, a wireless communication device may include a transceiver coupled to one or more antennas, enabling the device to transmit and receive wireless signals. The transceiver may include a local oscillator with voltage-controlled oscillation circuitry that generates a local oscillator signal. The local oscillator signal may be mixed with a data signal to upconvert the data signal (e.g., upconvert to a higher frequency or radio frequency) to generate a transmit signal to be transmitted via one or more antennas, or to downconvert a receive signal received via one or more antennas (e.g., downconvert to a lower frequency or baseband frequency) to generate a data signal.

[0017] A voltage-controlled oscillator circuit may include multiple cores (e.g., each core has its own LC energy storage circuit) and operate in multiple modes to generate signals with different frequencies, thereby expanding the tuning range. For different operating modes, the oscillator is coupled to different load capacitors, so the oscillation frequency can vary with the mode. However, when the voltage-controlled oscillator circuit operates in the desired mode, another undesired mode may overtake and even dominate the desired mode. This may be because the undesired mode has a larger gain than the desired mode (e.g., a larger loop gain), which causes the undesired mode to increase faster than the desired mode. "Loop gain" can refer to the total gain of the feedback loop or the total gain around the feedback loop that feeds the output back to the input, measured in decibels, and indicating the start-up strength in a positive feedback-based oscillator. In practice, this may depend on the initial conditions of the system dynamics and / or external disturbances to the voltage-controlled oscillator circuit. As a result of this dominant undesired operating mode, the voltage-controlled oscillator circuit may output a signal with undesired frequency and / or undesired phase noise.

[0018] With this in mind, Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry for convenience), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine-executable instructions), or combinations of hardware and software elements (which may be referred to as logic). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, communication bus, network) to transmit and / or receive data between them. It should be noted that... Figure 1This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0019] For example, electronic device 10 may include any suitable computing device, including desktop computers or laptops (e.g., a MacBook available from Apple Inc. in Cupertino, California). ® MacBook ® Pro, MacBook Air ® iMac ® Mac ® mini or Mac Pro ® Portable or handheld electronic devices, such as wireless electronic devices or smartphones (e.g., iPhones available from Apple Inc. in Cupertino, California), are examples of such devices. ® (Model form), tablet computers (e.g., the iPad available from Apple in Cupertino, California) ® (in the form of a model), wearable electronic devices (e.g., the Apple Watch available from Apple Inc. in Cupertino, California). ® (in the form of) and other similar devices. It should be noted that, Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be embodied wholly or partially in software, hardware, or both. Furthermore, the processor 12 and... Figure 1 Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other manipulation of information. Processor 12 may include one or more application processors, one or more baseband processors, or both, and performs the various functions described herein.

[0020] exist Figure 1In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0021] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0022] The input structure 22 of electronic device 10 allows a user to interact with electronic device 10 (e.g., press a button to increase or decrease the volume level). Like network interface 26, I / O interface 24 enables electronic device 10 to interact with a variety of other electronic devices. In some embodiments, I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. Network interface 26 may include one or more interfaces, for example, for personal area networks (PANs) such as Ultra Wideband (UWB) or BlueTooth. ® Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN) such as a protocol using one of the IEEE 802.11x series of protocols (e.g., Wi-Fi). ® Networks; and / or wide area networks (WANs) such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) networks, and wide area networks (WANs). ®This includes cellular networks, Long Term Evolution License Assisted Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or new radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 26 may include, for example, one or more interfaces for using the version 15 cellular communication standard of the 5G specification, which includes millimeter-wave (mmWave) frequency ranges (e.g., 24.25-300 GHz), and / or any other version of the cellular communication standard (e.g., version 16, version 17, any future version) that defines and / or implements frequency ranges for wireless communication. Network interface 26 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0023] Network interface 26 may also include one or more interfaces for, for example, broadband fixed wireless access networks (e.g., WiMAX). ® Mobile broadband wireless network (Mobile WiMAX) ® Asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video terrestrial broadcasting (DVB-T) ® Network and its extension DVB handheld (DVB-H) ® Networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0024] As shown in the figure, network interface 26 may include transceiver 30. In some embodiments, all or part of transceiver 30 may be located within processor 12. Transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and therefore may include transmitters and receivers. Power supply 29 of electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0025] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic device 10. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) may be directly or indirectly communicatively coupled to each other (e.g., via or through another component, communication bus, network) to transmit and / or receive data between each other.

[0026] Electronic device 10 may include transmitter 52 and / or receiver 54, which respectively enable the transmission and reception of data between electronic device 10 and external devices via, for example, a network (e.g., including a base station) or a direct connection. As shown, transmitter 52 and receiver 54 may be combined into transceiver 30. Electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to transceiver 30. Antennas 55A-55N may be configured in omnidirectional or directional configurations, single-beam, dual-beam, or multi-beam arrangements, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in antennas 55A-55N of an antenna group or module may be communicatively coupled to a respective transceiver 30 and each transmits radio frequency signals that can be advantageously and / or destructively combined to form a beam. Applicable to various communication standards, electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas. In some implementations, transmitter 52 and receiver 54 may transmit and receive information via other wired or wired systems or devices.

[0027] As shown in the figure, various components of electronic device 10 can be coupled together via bus system 56. Bus system 56 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 can be coupled together or use some other mechanism to accept or provide input to each other.

[0028] Figure 3 This is a block diagram of a transmitter 52 (e.g., a transmitting circuitry) that may be part of a transceiver 30 according to an embodiment of the present disclosure. As shown, the transmitter 52 can receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. A digital-to-analog converter (DAC) 62 of the transmitter 52 can convert the digital signal into an analog signal, and a modulator 63 can combine the converted analog signal with a carrier signal. A mixer 64 can combine the carrier signal with a local oscillator signal 65 from a local oscillator 66 to generate a radio frequency signal. Specifically, the local oscillator 66 may include a voltage-controlled oscillator (VCO) circuit 67 that generates or contributes to the generation of the local oscillator signal 65.

[0029] A power amplifier (PA) 68 receives an RF signal from a mixer 64 and amplifies the modulated signal to a suitable level to drive its transmission via one or more antennas 55. A filter 69 (e.g., filter circuitry and / or software) of the transmitter 52 then removes unwanted noise from the amplified signal to generate transmitted data 70 to be transmitted via one or more antennas 55. The filter 69 may include one or more suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise from the amplified signal. Additionally, the transmitter 52 may include any suitable additional components not shown, or may exclude some of the components shown, such that the transmitter 52 can transmit the transmitted data 60 via one or more antennas 55. For example, the transmitter 52 may include additional mixers and / or digital up-converters (e.g., for converting the input signal from a baseband frequency to an intermediate frequency). As another example, if the power amplifier 68 outputs the amplified signal within or approximately within the desired frequency range, then the transmitter 52 may not include the filter 69 (so that the amplified signal does not need to be filtered).

[0030] Figure 4This is a schematic diagram of a receiver 54 (e.g., receiving circuitry) that may be part of a transceiver 30 according to an embodiment of this disclosure. As shown, receiver 54 may receive received data 80 from one or more antennas 55 in the form of an analog signal. A low-noise amplifier (LNA) 81 may amplify the received analog signal to a suitable level for processing by receiver 54. A mixer 82 may combine the amplified signal with a local oscillation signal 83 from a local oscillator 84 to generate an intermediate or baseband frequency signal. Similar to the local oscillator 66 of transmitter 52, the local oscillator 84 of receiver 54 may include VCO circuitry 85 that generates or contributes to the generation of the local oscillation signal 83. A filter 86 (e.g., filter circuitry and / or software) may remove unwanted noise, such as cross-channel interference, from the signal. Filter 86 may also remove additional signals received by one or more antennas 55 at frequencies other than the desired signal. Filter 86 may include one or more suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise or signals from the received signal. Demodulator 87 may remove the radio frequency envelope from the filtered signal and / or extract the demodulated signal from the filtered signal for processing. Analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert it into a digital signal of incoming data 90 for further processing by electronics 10. Additionally, receiver 54 may include any suitable additional components not shown, or may exclude some of the components shown, such that receiver 54 may receive the received data 80 via one or more antennas 55. For example, receiver 54 may include an additional mixer and / or digital down-converter (e.g., for converting the input signal from an intermediate frequency to a baseband frequency).

[0031] Figure 5 This is a schematic diagram of a portion 100 of a VCO circuit 67, 85, which may be part of a transceiver 30, according to an embodiment of this disclosure. The VCO circuit may have multiple cores 102A, 102B (collectively referred to as 102). Although in Figure 5Two cores 102A and 102B are shown, but it should be understood that VCO circuits 67 and 85 may include any suitable number of cores 102, such as three or more cores 102, four or more cores 102, eight or more cores 102, etc. Each core 102A and 102B may include first terminals 104A and 104B and second terminals 106A and 106B, which can provide tap points for outputting signals from cores 102A and 102B. Specifically, the first terminals 104A and 104B (collectively referred to as 104) and the second terminals 106A and 106B (collectively referred to as 106) enable the output of differential signal pairs. As shown, each core 102A and 102B is also coupled to a corresponding inductor 108A and 108B (collectively referred to as 108). In addition, the two cores 102 may be coupled via one or more capacitors 110A and 110B (collectively referred to as 110). Figure 5 The capacitor pair is shown in the diagram. It should be understood that capacitor 110 can be provided by any suitable device or component, such as one or more capacitors.

[0032] As shown in the figure, the first current 112A in the inductor 108A of the first core 102A has a clockwise current direction and a 0° phase, and the second current 112B in the inductor 108B of the second core 102B has a counterclockwise current direction and a 180° phase. Therefore, the first terminal 104A of the inductor 108A is negative (denoted as "-"), and subsequently the second terminal 104A of the inductor 108A is positive (denoted as "+"). Similarly, the first terminal 104B of the inductor 108B is positive, while the second terminal 106B of the inductor 108B is negative. Therefore, the energy storage circuit voltage (e.g., the voltage at cores 102A and 102B) is in phase. In other words, for two adjacent oscillator cores (e.g., cores 102A and 102B), if the inductor currents 112A and 112B have opposite current directions, the energy storage circuit voltage is in phase; if the inductor currents 112A and 112B have the same current direction, the energy storage circuit voltage is out of phase. When adjacent cores 102A and 102B are in phase (e.g., have the same phase or have a phase difference of 0°), capacitor 110 can provide a lower capacitance (e.g., compared to when adjacent cores 102A and 102B are out of phase), such as reduced or minimal (e.g., zero or near zero) capacitance, and appears "invisible," thus acting as a short circuit between cores 102A and 102B. Therefore, capacitor 110 is shown as a dashed line instead of a solid line. Furthermore, when adjacent cores 102A and 102B are in phase, the energy storage circuit impedance (e.g., the impedance at cores 102A and 102B) may have a larger impedance (e.g., compared to when adjacent cores 102A and 102B are out of phase), such as an increased or maximum impedance. This operating mode may be referred to herein as the first mode or "mode 0".

[0033] On the other hand, when adjacent cores 102A and 102B are out of phase, capacitor 110 can provide a larger capacitance between cores 102A and 102B. Specifically, the greater the phase difference between adjacent cores 102A and 102B (e.g., the greater the phase difference between cores 102A and 102B), the larger the capacitance that capacitor 110 can provide. Therefore, when adjacent cores 102A and 102B are out of phase by 180°, capacitor 110 can have an increased or maximum capacitance.

[0034] Figure 6 This is a schematic diagram of portion 100 of a VCO circuit 67, 85 with two cores 102 operating in opposite phases according to an embodiment of this disclosure. Specifically, the currents 112 in the inductors 108 of the cores 102 have the same (e.g., clockwise) direction. Figure 5Similar to portion 100 of VCO circuits 67 and 85, the first terminal 104A of inductor 108A is negative, and the second terminal 104A of inductor 108A is positive. However, the first terminal 104B of inductor 108B is negative, while the second terminal 106B of inductor 108B is positive. Therefore, the energy storage circuit voltages are out of phase, and capacitor 110 provides a large (e.g., maximum) capacitance between cores 102 and appears "visible." Therefore, capacitor 110 is drawn with a solid line. Furthermore, when adjacent cores 102A and 102B are out of phase, the energy storage circuit impedance can have a lower impedance (e.g., compared to when adjacent cores 102A and 102B are in phase), such as reduced or minimal (e.g., zero or near-zero) impedance. This operation may be referred to herein as the second mode or "mode 1". However, because Mode 1 has a larger capacitance and a smaller energy storage circuit impedance, and therefore a smaller loop gain, it may be overwhelmed by Mode 0, which has a smaller capacitance and a larger energy storage circuit impedance, and therefore a larger loop gain.

[0035] To improve mode robustness, which helps ensure the exact oscillation state of the desired mode regardless of disturbances or initial conditions (e.g., not being dominated or surpassed by undesired modes), the disclosed embodiments help provide a desired mode loop gain greater than any other undesired mode during a stable oscillation phase. Thus, a correct or desired oscillation mode can be ensured even in the presence of disturbances from power supply noise, control voltage spikes, etc. Specifically, the disclosed embodiments include one or more mode boosters coupled between oscillator cores 102 to selectively enhance the desired mode gain and reduce the undesired mode gain. Specifically, mode boosters coupled to terminals (e.g., 104, 106) of core 102 associated with the desired operating mode can be enabled, while mode boosters coupled to terminals 104, 106 of core 102 associated with undesired operating modes can be disabled, as explained in more detail below.

[0036] Figure 7 This is a circuit diagram of a portion 120 of a VCO circuit 67, 85 having a mode boost converter 122 coupled between two cores 102A, 102B, according to an embodiment of this disclosure. As shown, inductors or inductive components 124A, 124B (L) are respectively connected in parallel on each energy storage circuit of each core 102. p ), capacitors or capacitor components 126A, 126B (C p ), resistors or resistor or impedance components 128A, 128B (R p), and transistors or transconductance components 130A, 130B (-gm / 2). Each terminal 104A, 106A of each core 102A is coupled to each terminal 104B, 106B of another core 102B via a mode or gain boost converter 122. Terminals 104, 106 of core 102 may be referred to herein as positive or negative terminals of core 102, but their polarity may be changed in additional or alternative embodiments. As shown, the positive terminal 104A of core 102A (with voltage V) ip The voltage is coupled to the positive terminal 104B of the core 102B via the first-mode boost converter 122A (with voltage V). jp The negative terminal 106A of core 102A (with voltage V) in The positive terminal 104B of core 102B is coupled to the positive terminal 104B of core 102B via a second-mode boost converter 122B. The positive terminal 104A of core 102A is coupled to the negative terminal 106B of core 102B via a third-mode boost converter 122C (with voltage V). jn Furthermore, the negative terminal 106A of core 102A is coupled to the negative terminal 106B of core 102B via the fourth mode boost converter 122D. It should be understood that certain components of VCO circuits 67 and 85, such as the switching circuit, have capacitors coupled in parallel with the mode boost converter 122 (e.g., such as...). Figure 5 and Figure 6 (As shown) etc. may be included in VCO circuits 67 and 85, but for convenience and ease of description, they may not be shown. Figure 7 As shown in the image.

[0037] When core 102 is in phase, the second-mode boost converter 122B and the third-mode boost converter 122C can be enabled (e.g., by setting the in-phase mode boost converter enable signal 132 (in_phase_en) to enabled or a high value), while the first-mode boost converter 122A and the fourth-mode boost converter 122D can be disabled (e.g., by setting the out-of-phase mode boost converter enable signal 134 (out-of-phase_en) to disabled or a low value). On the other hand, when core 102 is out-of-phase, the first-mode boost converter 122A and the fourth-mode boost converter 122D can be enabled (e.g., by setting the out-of-phase_en enable signal 134 to enabled or a high value), while the second-mode boost converter 122B and the third-mode boost converter 122C can be disabled (e.g., by setting the in_phase_en enable signal 132 to disabled or a low value). As shown in the figure, each mode booster 122 may include two transconductance units 136A and 136B (collectively referred to as 136) coupled end-to-end, such that the output of the first transconductance unit 136A and the input of the second transconductance unit 136B are coupled to a first terminal of a first core (e.g., the positive terminal 104A of core 102A), and the input of the first transconductance unit 136A and the output of the second transconductance unit 136B are coupled to a second terminal of a second core (e.g., the positive terminal 104A of core 102A).

[0038] Figure 8 This is a circuit diagram of a mode boost converter 122 according to an embodiment of the present disclosure. As shown, the mode boost converter 122 may include two n-channel metal-oxide-semiconductor (NMOS) transistors 150A and 150B and two p-channel metal-oxide-semiconductor (PMOS) transistors 152A and 152B coupled as shown. Specifically, the gate 154A of the first NMOS transistor 150A may be coupled to the gate 156A of the first PMOS transistor 152A, and the gate 154B of the second NMOS transistor 150B may be coupled to the gate 156B of the second PMOS transistor 152B. Furthermore, the drain 158A of the first NMOS transistor 150A may be coupled to the drain 160A of the first PMOS transistor 152A, and the drain 158B of the second NMOS transistor 150B may be coupled to the drain 160B of the second PMOS transistor 152B.

[0039] The mode boost converter 122 may also include an NMOS transistor 162 (e.g., an enable NMOS transistor) and a PMOS transistor 166 (e.g., a disable PMOS transistor). The NMOS transistor receives an enable en signal 164 to enable the mode boost converter 122, and the PMOS transistor receives an inverted enable enb signal 168 to disable the mode boost converter 122. As shown, the sources 170A and 170B of the first NMOS transistor 150A and the second NMOS transistor 150B may be coupled to the drain 172 of the enable NMOS transistor 162, and the source 174 of the enable NMOS transistor 162 may be coupled to ground 176. Additionally, the sources 178A and 178B of the first PMOS transistor 152A and the second PMOS transistor 152B may be coupled to the drain 180 of the disable PMOS transistor 166, and the source 182 of the disable PMOS transistor 166 may be coupled to a power supply 184 (e.g., a power rail). However, it should be understood that the mode booster 122 can be implemented using all NMOS transistors, all PMOS transistors, any suitable combination of transistors, a working transconductance amplifier, or any other suitable component.

[0040] While the mode booster 122 of this disclosure may be shown as being implemented using transconductance unit 136, it should be understood that the use of transconductance unit 136 is exemplary, and in additional or alternative embodiments, the mode booster 122 may include other specific implementations depending on the VCO circuit topology and / or coupling mechanism. Figures 9A to 9D It is a circuit diagram of an additional or alternative implementation of a mode booster 122 having different input / output implementations based on signal type (e.g., voltage to current).

[0041] Figure 9A This is a circuit diagram of a mode boost converter 122 in the form of a transconductance amplifier having a voltage input 190 and a current output 192, according to an embodiment of the present disclosure. As shown, the mode boost converter 122 couples a first core 102A to a second core 102B. The mode boost converter 122 is coupled to the first core 102A via the voltage input 190 and to the second core 102B via the current output 192.

[0042] Figure 9B This is a circuit diagram of a mode boost converter 122 in the form of a transimpedance amplifier, having a current input 200 and a voltage output 202, according to an embodiment of this disclosure. As shown, the mode boost converter 122 couples a first core 102A to a second core 102B. The mode boost converter 122 is coupled to the first core 102A via the current input 200 and to the second core 102B via the voltage output 202.

[0043] Figure 9CThis is a circuit diagram of a mode boost converter 122 in the form of a voltage amplifier having a voltage input 210 and a voltage output 212, according to an embodiment of the present disclosure. As shown, the mode boost converter 122 couples a first core 102A to a second core 102B. The mode boost converter 122 can be coupled to the first core 102A via the voltage input 210 and to the second core 102B via the voltage output 212.

[0044] Figure 9D This is a circuit diagram of a mode boost converter 122 in the form of a current amplifier having a current input 220 and a current output 222, according to an embodiment of the present disclosure. As shown, the mode boost converter 122 couples a first core 102A to a second core 102B. The mode boost converter 122 can be coupled to the first core 102A via the current input 220 and to the second core 102B via the current output 222.

[0045] Figure 10 This refers to portion 120 of the VCO circuits 67, 85 operating in in-phase mode according to an embodiment of this disclosure. Therefore, the in-phase boost converters 122B, 122C can be enabled, for example, by setting the in_phase_en signal 132 to a high value (e.g., 1). Conversely, the out-of-phase boost converters 122A, 122D can be disabled, for example, by setting the out-of-phase_en signal 134 to a low value (e.g., 0) (and thus drawn as dashed lines instead of solid lines). It should be understood that the in_phase_en signal 132 can be set to any suitable value (e.g., low, intermediate value) to enable the in-phase boost converters 122B, 122C, and the out-of-phase_en signal 134 can be set to any suitable value (e.g., high, intermediate value) to disable the out-of-phase boost converters 122A, 122D. For illustrative purposes, to show the waveform reversal between the positive and negative terminals, the positive waveform is represented at the positive terminal 104A of core 102A (with voltage V). ip ) and the positive terminal 104B of core 102B (with voltage V) jp The waveform is shown at point 102A, and the negative representation of the waveform is at the negative terminal 106A of core 102A (with voltage V). in ) and the negative terminal 106B of core 102B (with voltage V) jn As shown at (), this is because core j is in phase with core i.

[0046] Figure 11 This illustrates an embodiment of the present disclosure when operating in in-phase mode (e.g., as shown in the diagram). Figure 10 (See part 120 of VCO circuits 67 and 85) Equivalent half-circuit model 230 of the expected in-phase mode startup gain of the core 102 of VCO circuits 67 and 85. Figure 7 The transconductance of the oscillator core negative gm circuit of the VCO circuits 67 and 85 shown in the diagram is denoted as gm, and therefore, the transconductance component 130 of the core 102 in the equivalent half-circuit model can be -gm / 2. The transconductance of the mode boost converter 122 is denoted as gm. b Therefore, the transconductance component 232 of the mode booster 122 in the equivalent half-circuit model can be –gm b / 2. Figure 7 The shunt resistor or shunt resistor component 128 on the energy storage circuit of part 120 of the VCO circuits 67 and 85 shown is represented as R. p The desired in-phase mode startup loop gain (G) inphase This can be represented by the following equation 1: (Equation 1) Figure 12 This illustrates an embodiment of the present disclosure when operating in in-phase mode (e.g., as shown in the diagram). Figure 10 (See section 120 of VCO circuits 67 and 85) Equivalent half-circuit model 240 of the undesired out-of-phase mode startup gain of the core 102 of VCO circuits 67 and 85. (See also...) Figure 11 Similar to the equivalent half-circuit model 230 of the expected in-phase mode startup gain, the transconductance component 130 of the core 102 in the equivalent half-circuit model can be -gm / 2, and Figure 7 The shunt resistor component 128 on the energy storage circuit of portion 120 of the VCO circuits 67 and 85 shown is denoted as R. p However, the transconductance component 242 of the mode boost converter 122 in the equivalent half-circuit model can be +gm. b / 2. Therefore, when operating in in-phase mode, the startup loop gain (G) in out-of-phase mode is not expected. outphase This can be represented by the following equation 2: (Equation 2) Therefore, it is expected that the startup gain of the in-phase mode can be enhanced to (1+gm) b / gm) times, as shown in Equation 1; it is not desirable for the heterogeneous mode gain to be weakened or reduced to (1+gm) times. b R p / 2) one-third, as shown in Equation 2. Therefore, the desired in-phase mode can have a faster gain increase than the undesired out-of-phase mode, thus ensuring that the desired in-phase mode becomes dominant and remains more dominant than the undesired out-of-phase mode.

[0047] When operating VCO circuits 67 and 85 in out-of-phase mode, they can be disabled. Figure 10 The boost converters 122B and 122C are in enable mode and can be enabled. Figure 10 The disabled mode boost converters 122A and 122D are shown. As a result, Equation 1 above can be applied to the startup loop gain (G) of the desired out-of-phase mode. outphase Furthermore, Equation 2 above can be applied to the startup loop gain (G) where in-phase mode is not desired. inphase ). Figure 13 This is part 120 of the VCO circuits 67, 85 operating in out-of-phase mode according to an embodiment of this disclosure. The in-phase boost converters 122B, 122C can be disabled, for example, by setting the in_phase_en signal 132 to a low value (e.g., 0) (and therefore drawn as dashed lines instead of solid lines). Conversely, the out-of-phase boost converters 122A, 122B can be enabled, for example, by setting the out-of-phase_en signal 134 to a high value. A positive waveform is represented at the positive terminal of core i (with voltage V). ip ) and the negative terminal of core j (with voltage V) jn The waveform is shown at point ), and the negative representation of the waveform is at the negative terminal of core i (with voltage V). in ) and the positive terminal of core j (with voltage V) jn As shown at (), this is because core j is out of phase with core i. It should be understood that the in_phase_en signal 132 can be set to any suitable value (e.g., high, intermediate) to disable the in-phase boost converters 122B and 122C, and the out-of-phase_en signal 134 can be set to any suitable value (e.g., low, intermediate) to enable the out-of-phase boost converters 122A and 122D. For illustrative purposes, to show the waveform reversal between the positive and negative terminals, the positive waveform is represented at the positive terminal 104A of core 102A (with voltage V). ip ) and the positive terminal 104B of core 102B (with voltage V) jp The waveform is shown at point 102A, and the negative representation of the waveform is at the negative terminal 106A of core 102A (with voltage V). in ) and the negative terminal 106B of core 102B (with voltage V) jn (This is shown at the location.)

[0048] Figure 11 The diagram also illustrates the operation in out-of-phase mode (e.g., as shown in the diagram). Figure 13 The equivalent half-circuit model of the startup gain of the core 102 of VCO circuits 67 and 85 (shown in part 120) is as follows: That is, the transconductance component 130 of the core 102 in the equivalent half-circuit model can be -gm / 2, and the transconductance component 232 of the mode booster 122 in the equivalent half-circuit model can be -gm / 2. Figure 7The shunt resistor component 128 on the energy storage circuit of portion 120 of the VCO circuits 67 and 85 shown is denoted as R. p The desired startup loop gain for out-of-phase mode (G) outphase This can be represented by the following equation 3: (Equation 3) Figure 12 The diagram also illustrates how to demonstrate operation in out-of-phase mode (e.g., as shown in the diagram). Figure 13 (See part 120 of VCO circuits 67 and 85 in the diagram) Equivalent half-circuit model of the undesirable in-phase mode startup gain of the core 102 of VCO circuits 67 and 85.

[0049] Figure 12 This illustrates an embodiment of the present disclosure when operating in in-phase mode (e.g., as shown in the diagram). Figure 10 (See section 120 of VCO circuits 67 and 85) Equivalent half-circuit model 240 of the undesired out-of-phase mode startup gain of the core 102 of VCO circuits 67 and 85. (See also...) Figure 11 Similar to the equivalent half-circuit model 230 of the expected in-phase mode startup gain, the transconductance component 130 of the core 102 in the equivalent half-circuit model can be -gm / 2, and Figure 7 The shunt resistor component 128 on the energy storage circuit of portion 120 of the VCO circuits 67 and 85 shown is denoted as R. p However, the transconductance component 242 of the mode boost converter 122 in the equivalent half-circuit model can be +gm. b / 2. Therefore, when operating in out-of-phase mode, the startup loop gain (G) of in-phase mode is not expected. inphase This can be represented by the following equation 4: (Equation 4) Similar to VCO circuits 67 and 85 operating in in-phase mode, it is expected that the startup gain in out-of-phase mode will be enhanced to (1+gm). b / gm) times, without expecting the in-phase mode startup gain to be weakened or reduced to (1+gm) times, and without expecting it to be weakened or reduced to (1+gm) times. b R p / 2) one-third. Therefore, it is expected that the out-of-phase mode can have a faster gain increase than the unexpected in-phase mode, thus ensuring that the expected out-of-phase mode becomes dominant and remains more dominant than the unexpected in-phase mode.

[0050] Figure 14 This is a flowchart of a method 250 for increasing the gain of a desired mode and decreasing the gain of an undesired mode according to an embodiment of this disclosure. Specifically, the method involves... Figure 14Method 250 ensures that the desired operating mode of the VCO circuits 67, 85 remains more dominant than the undesired operating mode. Method 250 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10, such as processor 12. In some embodiments, method 250 can be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14 or storage device 16. For example, method 250 can be executed at least in part by one or more software components such as the operating system of the electronic device 10, one or more software applications of the electronic device 10, etc. Although method 250 is described using a specific order of steps, it should be understood that this disclosure contemplates that the steps described may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0051] In process block 252, processor 12 receives an indication to enter an operating mode of VCO circuits 67, 85. In decision block 254, processor 12 determines whether this mode corresponds to the first voltage of the first oscillator core (e.g., 102A) of VCO circuits 67, 85 being in phase with the second voltage of the second core 102B of VCO circuits 67, 85. That is, processor 12 determines whether this mode corresponds to an in-phase mode, such as... Figure 10 What is depicted.

[0052] If so, in process block 256, processor 12 disables a first-mode boost converter (e.g., 122A) that couples the positive terminal (e.g., 104A) of the first core 102A to the positive terminal (e.g., 104B) of the second core 102B. Specifically, processor 12 may set the out-of-phase boost enable signal 134 (out-of-phase_en) to disabled or a low value to indicate the disabling of out-of-phase boost converters, including the first-mode boost converter 122A, and / or send an out-of-phase_en 134 signal with a disabled value to the first-mode boost converter 122A. In process block 258, processor 12 also enables a second-mode boost converter (e.g., 122B) that couples the negative terminal (e.g., 106A) of the first core 102A to the positive terminal 104B of the second core 102B. Specifically, the processor 12 can set the in-phase mode boost enable signal 132 (in-phase_en) to enable or high to indicate the enable of the in-phase mode boost, including the second mode boost 122B, and / or send the enable value of the in-phase_en 132 signal to the second mode boost 122B.

[0053] In process block 260, processor 12 also enables a third-mode boost converter (e.g., 122C) that couples the positive terminal 104A of the first core 102A to the negative terminal (e.g., 106B) of the second core 102B. Specifically, processor 12 may set the in-phase boost converter enable signal 132 (in-phase_en) to enabled or high to indicate the activation of in-phase boost converters, including the third-mode boost converter 122C, and / or send an in-phase_en 132 signal with an enable value to the third-mode boost converter 122C. In process block 262, processor 12 disables a fourth-mode boost converter (e.g., 122D) that couples the negative terminal 106A of the first core 102A to the negative terminal 106B of the second core 102B. Specifically, the processor 12 can set the out-of-phase_en enable signal 134 to disabled or a low value to indicate that the out-of-phase boosters, including the fourth-mode booster 122D, are disabled, and / or send the out-of-phase_en 134 signal with a disabled value to the fourth-mode booster 122D.

[0054] VCO circuits 67 and 85 can now be configured to operate in in-phase mode, such that the desired in-phase mode remains more dominant than the undesired operating modes (including the undesired out-of-phase mode). Specifically, the startup gain of the desired in-phase mode can be enhanced to (1+gm) b / gm) times (for example, as shown in Equation 1 above); it is not desirable for the out-of-phase mode gain to be reduced or decreased to (1+gm) times (e.g., as shown in Equation 1 above); b R p / 2) one-third (for example, as shown in Equation 2 above). Therefore, the desired in-phase mode can have a faster gain increase than the undesired out-of-phase mode, thus ensuring that the desired in-phase mode becomes dominant and remains more dominant than the undesired out-of-phase mode.

[0055] However, in decision block 254, if processor 12 determines that the mode does not correspond to the in-phase operation mode, then in process block 264, processor 12 enables the first-mode boost converter 122A that couples the positive terminal 104A of the first core 102A to the positive terminal 104B of the second core 102A. Specifically, processor 12 may set the out-of-phase boost converter enable signal 134 (out-of-phase_en) to enabled or high to indicate the activation of out-of-phase boost converters, including the first-mode boost converter 122A, and / or send an out-of-phase_en 134 signal with an enabled value to the first-mode boost converter 122A. In process block 266, processor 12 also disables the second-mode boost converter 122B that couples the negative terminal 106A of the first core 102A to the positive terminal 104B of the second core 102B. Specifically, the processor 12 can set the in-phase mode boost enable signal 132 (in-phase_en) to disabled or low to indicate that the in-phase mode boost, including the second mode boost 122B, is disabled, and / or send the in-phase_en 132 signal with a disabled value to the second mode boost 122B.

[0056] In process block 268, processor 12 also disables the third-mode boost converter 122C that couples the positive terminal 104A of the first core 102A to the negative terminal 106B of the second core 102B. Specifically, processor 12 may set the in-phase boost converter enable signal 132 (in-phase_en) to disabled or a low value to indicate the disabling of in-phase boost converters, including the third-mode boost converter 122C, and / or send the in-phase_en 132 signal with a disabled value to the third-mode boost converter 122C. In process block 270, processor 12 enables the fourth-mode boost converter 122D that couples the negative terminal 106A of the first core 102A to the negative terminal 106B of the second core 102B. Specifically, the processor 12 can set the out-of-phase_en enable signal 134 to enable or a high value to indicate the enable of the out-of-phase boosters, including the fourth-mode booster 122D, and / or send the enable value of the out-of-phase_en 134 signal to the fourth-mode booster 122D.

[0057] VCO circuits 67 and 85 can now be configured to operate in out-of-phase mode, such that the desired out-of-phase mode remains more dominant than the undesired operating modes (including the undesired in-phase mode). Specifically, the startup gain of the desired out-of-phase mode can be enhanced to (1+gm) b / gm) times (for example, as shown in Equation 3 above); it is not desirable for the in-phase mode gain to be reduced or decreased to (1+gm) times (e.g., as shown in Equation 3 above); b R p / 2) one-third (e.g., as shown in Equation 4 above). Therefore, the desired out-of-phase mode can have a faster gain increase than the undesirable in-phase mode, thus ensuring that the desired out-of-phase mode becomes dominant and remains more dominant than the undesirable in-phase mode. In this way, method 250 can increase the gain of the desired mode and decrease or weaken the gain of the undesirable mode. Specifically, execute Figure 14 Method 250 can ensure that the desired operating mode of VCO circuits 67 and 85 remains more dominant than the undesired operating mode.

[0058] Figure 15A This is an exemplary embodiment 280 of a VCO circuit 67, 85 as described herein, operating in a first mode (e.g., mode 0) according to an embodiment of this disclosure, having four cores 102A-102D and mode boosters 122A-122H (collectively referred to as 122). Switching circuit 282 and capacitor 110 are coupled in parallel with mode booster 122 and subsequently couple the cores 102 together. Specifically, switching circuit 282 can selectively couple or decouple the cores 102 together, and thus be part of or separate from the VCO circuit 67, 85. As shown, mode 0 may include each current direction 112A-112D (collectively referred to as 112) in each inductor 108A-108D (collectively referred to as 108) of each core 102, each core having an opposite current direction compared to the current direction of its adjacent core 102. Therefore, each core 102 may be in phase with its adjacent core 102. In other words, the current direction 112A (e.g., clockwise) of the first inductor 108A in the first core 102A can be opposite to the current direction 112B, 112D (e.g., counterclockwise) of the second inductors 108B and 108D in the adjacent second core 102B and fourth core 102D. Similarly, the current direction 112B (e.g., counterclockwise) of the second inductor 108B in the second core 102B can be opposite to the current direction 112A, 112C (e.g., clockwise) of the first inductors 108A and 108C in the adjacent first core 102A and third core 102C, and so on.

[0059] Figure 15B It operates in a second mode (e.g., mode 1) according to the embodiments of this disclosure. Figure 15AAn exemplary embodiment 280 of the VCO circuits 67, 85. As shown, mode 1 may include a current direction 112 in two inductors 108 of adjacent cores 102 having a first current direction (e.g., the two adjacent cores 102 are out of phase), and a current direction 112 in two other inductors 108 of two other adjacent cores 102 having a second current direction different from the first current direction (e.g., the two other adjacent cores 102 are out of phase). In other words, the current directions 112A, 112B (e.g., clockwise) of the first inductors 108A and 108B in the first core 102A and the second core 102B are the same, and the current directions 112C, 112D (e.g., counterclockwise) of the third inductors 108C and 108D in the adjacent third core 102C and fourth core 102D are the same, but different from the current directions 112A, 112B of the first inductors 108A and 108B in the first core 102A and the second core 102B. Therefore, the first core 102A and the fourth core 102D are in phase, the second core 102B and the third core 102C are in phase, but the first core 102A and the second core 102B are out of phase, and the third core 102C and the fourth core 102D are out of phase.

[0060] Figure 15C It operates in a third mode (e.g., mode 2) according to the embodiments of this disclosure. Figure 15A An exemplary embodiment 280 of the VCO circuits 67, 85. As shown, mode 2 may include a current direction 112 in two inductors 108 of adjacent cores 102 having a first current direction (e.g., the two adjacent cores 102 are out of phase), and a current direction 112 in two other inductors 108 of two other adjacent cores 102 having a second current direction different from the first current direction (e.g., the two other adjacent cores 102 are out of phase). In other words, the current directions 112A and 112D (e.g., clockwise) of the first inductors 108A and 108D in the first core 102A and the fourth core 102D are the same, and the current directions 112B and 112C (e.g., counterclockwise) of the second inductors 108B and 108C in the adjacent second core 102B and the third inductor 108C are the same, but different from the current directions 112A and 112D of the first inductors 108A and 108D in the first core 102A and the fourth inductor 102D. Therefore, the first core 102A and the second core 102B are in phase, and the third core 102C and the fourth core 102D are in phase, but the first core 102A and the fourth core 102D are out of phase, and the second core 102B and the third core 102C are out of phase.

[0061] Figure 15D It operates in a fourth mode (e.g., mode 3) according to the embodiments of this disclosure. Figure 15A An exemplary embodiment 280 of the VCO circuits 67, 85. As shown, mode 3 may include current directions 112 in all four inductors 108 of core 102 having the same current direction (e.g., all four cores 102 are out of phase). That is, the current directions 112A-112D (e.g., clockwise) of all four inductors 108A-108D of all four cores 102A-102D are the same. Therefore, all four cores 102A-102D are out of phase with each other. As explained in detail above, mode boost 122 can promote the dominance of the desired mode over the undesired mode by enhancing the startup gain of the desired mode while reducing the startup gain of the undesired mode.

[0062] Figure 16 It shows that there is none. Figure 7 The diagram illustrates the operation of the VCO circuit of the boost converter 122. The diagram includes a horizontal or x-axis 290 representing the different modes (e.g., mode 0, mode 1, mode 2, and mode 3) in which the VCO circuits 67, 85 can operate, and a vertical or y-axis 292 representing the loop gain (e.g., in decibels). Specifically, modes 0-3 shown on the horizontal axis 290 correspond to... Figures 15A to 15D The pattern shown. In Figure 16 In the example shown, pattern 2 is the expected 294, while patterns 0, 1, and 3 are the unexpected 296. Without... Figure 7 In the case of the illustrated boost converter 122, mode 0 can supersede mode 2 and become dominant because mode 2 can have a larger capacitance 110 between its cores 102, which have the same current direction and a lower energy storage circuit quality factor, compared to mode 0. That is, the capacitance 110 between the out-of-phase cores (e.g., the first core 102A and the fourth core 102D, and the second core 102B and the third core 102C) can be larger, thus causing a lower oscillation loop quality factor in the VCO circuits 67, 85 when operating in mode 2 compared to operating in mode 0.

[0063] Figure 17 This illustrates an embodiment according to this disclosure. Figures 15A to 15DThe example implementation of VCO circuits 67, 85 is illustrated in the graph of operation of 280. As shown, the operating mode booster 122 enhances the startup gain associated with desired mode 2 294 (e.g., as indicated by the upward arrow) and reduces or weakens the startup gain associated with undesired mode 296 (e.g., as indicated by the downward arrow) (e.g., as discussed above) to ensure that desired mode 2 294 dominates (e.g., has a larger loop gain than undesired operating modes 296) and remains dominant (e.g., continues to have a larger loop gain than undesired operating modes 296).

[0064] It should be understood that Figures 15A to 15D The exemplary specific implementation 280 of the VCO circuits 67, 85 shown is purely illustrative, and any suitable number of cores (e.g., more or fewer cores), components (e.g., more or fewer components), operating modes (e.g., more or fewer operating modes), etc., can be contemplated. Specifically, the VCO circuits 67, 85 can have any suitable number (e.g., N) of cores 102 and corresponding mode (or gain) boost converters. Figure 18 This is a representative diagram of a VCO circuit 67, 85 having N cores 102A-102F (collectively referred to as 102) and a corresponding mode boost converter 122 according to an embodiment of this disclosure. Although Figure 18 The diagram shows N as six cores 102, but it should be understood that the representative diagrams of VCO circuits 67, 85 are intended to illustrate that any suitable number of cores 102 N can be implemented in VCO circuits 67, 85 (e.g., two or more, four or more, six or more, eight or more, ten or more, twelve or more, twenty or more, etc.). The inductor current 112A-112F in each inductor 108 for each core 102A-102F is also shown. Therefore, in-phase boost converters 310A-310C are shown between in-phase cores (e.g., between cores 102A and 102B, between cores 102A and 102E, and between cores 102C and 102F), and out-of-phase boost converters 312A-312G are shown between out-of-phase cores (e.g., between cores 102A and 102D, between cores 102B and 102C, between cores 102B and 102D, between cores 102C and 102E, between cores 102D and 102E, between cores 102E and 102F, and between cores 102A and 102F).

[0065] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0066] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature that significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35 USC 112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35 U.SC 112(f).

[0067] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A voltage-controlled oscillator circuit, comprising: The first core includes a first inductor, a first positive terminal, and a first negative terminal; The second core includes a second inductor, a second positive terminal, and a second negative terminal; A first-mode boost converter, wherein the first-mode boost converter couples the first positive terminal of the first core to the second positive terminal of the second core; The second-mode boost converter couples the first negative terminal of the first core to the second positive terminal of the second core. A third-mode boost converter, wherein the first positive terminal of the first core is coupled to the second negative terminal of the second core; as well as A fourth-mode boost converter, wherein the first negative terminal of the first core is coupled to the second negative terminal of the second core, wherein: Each of the first-mode boost converter, the second-mode boost converter, the third-mode boost converter, and the fourth-mode boost converter includes a first transconductance unit that is end-to-end coupled to the second transconductance unit, and each mode boost converter includes a first n-channel metal-oxide-semiconductor NMOS transistor, a second NMOS transistor, a first p-channel metal-oxide-semiconductor PMOS transistor, and a second PMOS transistor.

2. The voltage-controlled oscillator circuit of claim 1, wherein the second mode booster and the third mode booster are configured to be enabled based on the first voltage of the first core being in phase with the second voltage of the second core, and the first mode booster and the fourth mode booster are configured to be disabled.

3. The voltage-controlled oscillator circuit of claim 1, wherein the first mode booster and the fourth mode booster are configured to be enabled based on the first voltage of the first core being out of phase with the second voltage of the second core, and the second mode booster and the third mode booster are configured to be disabled.

4. The voltage-controlled oscillator circuit according to claim 1, wherein based on the first voltage of the first core and the second voltage of the second core being in phase, the second mode booster and the third mode booster are configured to increase the in-phase gain of the first core and decrease the out-of-phase gain of the first core.

5. The voltage-controlled oscillator circuit of claim 4, wherein the second-mode boost converter and the third-mode boost converter are configured to increase the in-phase gain of the first core by a multiple of the sum of the quotient of the transconductance of the second-mode boost converter or the third-mode boost converter divided by the transconductance of the first core and a constant.

6. The voltage-controlled oscillator circuit of claim 4, wherein the second-mode booster and the third-mode booster are configured to reduce the out-of-phase gain of the first core to one-tenth of the sum of the transconductance obtained by dividing the product of the transconductance and the resistance of the first core by a second constant and a first constant.

7. The voltage-controlled oscillator circuit according to claim 1, wherein, based on the first voltage of the first core and the second voltage of the second core being out of phase, the second mode booster and the third mode booster are configured to increase the out-of-phase gain of the first core and decrease the in-phase gain of the first core.

8. A method for operating a voltage-controlled oscillating circuit, comprising: The processing circuit receives an indication of either out-of-phase or in-phase operation mode for entering the voltage-controlled oscillator circuit, which includes: a first core, a second core, a third core, a fourth core, a first set of mode boosters coupled between the first core and the second core, a second set of mode boosters coupled between the second core and the third core, a third set of mode boosters coupled between the third core and the fourth core, and a fourth set of mode boosters coupled between the fourth core and the first core. Based on the in-phase or out-of-phase operating mode, a first subset of the mode boosters in the first group of mode boosters, a first subset of the mode boosters in the second group of mode boosters, a first subset of the mode boosters in the third group of mode boosters, and a first subset of the mode boosters in the fourth group of mode boosters are enabled via the processing circuit to increase the desired gain of the in-phase or out-of-phase operating mode and decrease the undesired gain of the other operating mode; and Based on the in-phase operation mode or the out-of-phase operation mode, the second subset of the mode boosters in the first group of mode boosters, the second subset of the mode boosters in the second group of mode boosters, the second subset of the mode boosters in the third group of mode boosters, and the second subset of the mode boosters in the fourth group of mode boosters are disabled via the processing circuit.

9. The method of claim 8, wherein the first subset of the mode boosters includes a first mode booster coupled between a first terminal of the first core and a first terminal of the second core, and a second mode booster coupled between a second terminal of the first core and a second terminal of the second core.

10. The method of claim 9, wherein the second subset of the mode boosters includes a third mode booster coupled between the second terminal of the first core and the first terminal of the second core, and a fourth mode booster coupled between the first terminal of the first core and the second terminal of the second core.

11. The method of claim 10, wherein the first terminal of the first core and the first terminal of the second core are positive terminals, and the second terminal of the first core and the second terminal of the second core are negative terminals.

12. The method of claim 11, wherein the out-of-phase operating mode is associated with the first core and the second core of the plurality of cores that are out of phase.

13. The method of claim 10, wherein the first terminal of the first core and the second terminal of the second core are positive terminals, and the second terminal of the first core and the first terminal of the second core are negative terminals.

14. The method of claim 13, wherein the in-phase operation mode is associated with the first core and the second core that are in phase among the plurality of cores.

15. An electronic device comprising: A transceiver having a voltage-controlled oscillator circuit, the voltage-controlled oscillator circuit comprising: The first core includes a first inductor, a first positive terminal, and a first negative terminal; The second core includes a second inductor, a second positive terminal, and a second negative terminal; A first-mode boost converter, wherein the first-mode boost converter couples the first positive terminal of the first core to the second positive terminal of the second core, and the first-mode boost converter includes a first set of transconductance units coupled end-to-end. The second-mode boost converter couples the first negative terminal of the first core to the second positive terminal of the second core, and includes a second set of transconductance units coupled end-to-end. A third-mode boost converter, wherein the first positive terminal of the first core is coupled to the second negative terminal of the second core, the third-mode boost converter including a third set of transconductance units coupled end-to-end; and A fourth-mode boost converter, which couples the first negative terminal of the first core to the second negative terminal of the second core, includes a fourth set of transconductance units coupled end-to-end. Each mode boost converter includes a first n-channel metal-oxide-semiconductor (NMOS) transistor, a second NMOS transistor, a first p-channel metal-oxide-semiconductor (PMOS) transistor, and a second PMOS transistor. The processing circuit is configured to operate the first mode boost converter, the second mode boost converter, the third mode boost converter, and the fourth mode boost converter to increase the desired gain of the desired in-phase or desired out-of-phase operating modes of the first core and the second core and to decrease the undesired gain of the undesired in-phase or undesired out-of-phase operating modes of the first core and the second core.

16. The electronic device of claim 15, wherein the voltage-controlled oscillator circuit includes pairs of capacitors coupled in parallel to the first-mode boost converter, the second-mode boost converter, the third-mode boost converter, and the fourth-mode boost converter.

17. The electronic device of claim 15, wherein the voltage-controlled oscillator circuit includes a switching circuit coupled in parallel to the first-mode boost converter, the second-mode boost converter, the third-mode boost converter, and the fourth-mode boost converter, the switching circuit being configured to couple or decouple the plurality of cores to each other.

18. The electronic device of claim 15, wherein the gate of the first NMOS transistor is coupled to the gate of the first PMOS transistor, the gate of the second NMOS transistor is coupled to the gate of the second PMOS transistor, the drain of the first NMOS transistor is coupled to the drain of the first PMOS transistor, and the drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor.

19. The electronic device of claim 18, wherein each mode booster comprises: The enabled NMOS transistor coupled to the first NMOS transistor and the second NMOS transistor, and A disabled PMOS transistor coupled to the first PMOS transistor and the second PMOS transistor.

20. The electronic device of claim 19, wherein the source of the first NMOS transistor and the source of the second NMOS transistor are coupled to the drain of the enabled NMOS transistor, and the source of the first PMOS transistor and the source of the second PMOS transistor are coupled to the drain of the disabled PMOS transistor.

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