Wideband low harmonic frequency multiplication circuit
Patent Information
- Application Number
- CN202211661977.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-21
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2042-12-21
AI Technical Summary
随着工作频带的不断拓宽，特别是倍频器输出频率覆盖两倍频程后，倍频器对低频段的谐波抑制能力会极大降低，使得其输出频率的谐波成分更高，影响其在超宽频带中的应用
[0022]第一倍频模块包括用于抑制输出频率谐波成分的第一谐振抑制单元，第二倍频模块包括用于抑制输出频率谐波成分的第二谐振抑制单元，两个倍频模块分别包括用于抑制输出频率谐波成分的谐振抑制单元，能有效抑制输出频率中的谐波成分，降低了倍频后的谐波输出；同时，第一谐振抑制单元的抑制频段范围与第二谐振抑制单元的抑制频段范围不同，结合第一倍频模块与第二倍频模块的独立倍频与谐波抑制，能有效拓展倍频输出的频率带宽。
Smart Images
Figure CN115833754B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wireless communication technology, and in particular to a broadband low-harmonic frequency multiplier circuit. Background Technology
[0002] A frequency multiplier is a circuit that multiplies the frequency of a phase-locked loop (PLL) output by a specific factor to meet the high-frequency or wideband application requirements of radio frequency transceiver systems. As the operating bandwidth continues to widen, especially when the frequency multiplier's output frequency covers two octaves, its ability to suppress harmonics in the low-frequency band decreases significantly, resulting in higher harmonic content at its output frequency and affecting its application in ultra-wideband applications.
[0003] For ultra-wideband applications, especially those covering two octaves or more, frequency multiplier circuits are required to have ultra-wideband and low-harmonic output frequency characteristics. Therefore, a wideband low-harmonic frequency multiplication technology solution is urgently needed. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a broadband low harmonic frequency multiplication technology solution to achieve ultra-wideband and low harmonic output of a 2x range frequency multiplier, so as to solve the above-mentioned technical problems.
[0005] To achieve the above and other objectives, the detailed technical solutions provided by this invention are as follows.
[0006] A broadband low-harmonic frequency multiplier circuit includes:
[0007] The first frequency multiplier module has its differential input terminal as the differential signal input terminal of the broadband low harmonic frequency multiplier circuit.
[0008] The differential input terminal of the second frequency multiplier module is connected in parallel with the differential input terminal of the first frequency multiplier module;
[0009] A differential output module, whose input terminal is connected to the output terminal of the first frequency multiplier module and the output terminal of the second frequency multiplier module, and whose output terminal serves as the differential signal output terminal of the broadband low harmonic frequency multiplier circuit;
[0010] A switching control module is connected between the output terminal of the first frequency multiplier module and the input terminal of the differential output module, and between the output terminal of the second frequency multiplier module and the input terminal of the differential output module, and is also connected to the first frequency multiplier module and the second frequency multiplier module;
[0011] The first frequency doubling module includes a first resonant suppression unit for suppressing harmonic components of the output frequency, and the second frequency doubling module includes a second resonant suppression unit for suppressing harmonic components of the output frequency. The suppression frequency range of the first resonant suppression unit is different from that of the second resonant suppression unit. Under the control of the switching control module, one of the first frequency doubling module and the second frequency doubling module is selected for frequency doubling processing and output to the outside through the differential output module.
[0012] Optionally, the first frequency multiplier module further includes a first differential pair unit, which includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor serves as the negative terminal of the differential input of the first frequency multiplier module, and the gate of the second NMOS transistor serves as the positive terminal of the differential input of the first frequency multiplier module.
[0013] Optionally, the first resonance suppression unit includes a first inductor, a second inductor, a first capacitor, and a second capacitor. One end of the first inductor is connected to the drain of the first NMOS transistor, and the other end of the first inductor is connected to the first capacitor, the second capacitor, and the second inductor connected in series and then connected to the source of the first NMOS transistor.
[0014] Optionally, the second frequency multiplier module further includes a second differential pair unit, which includes a third NMOS transistor and a fourth NMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the third NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the third NMOS transistor serves as the negative terminal of the differential input of the second frequency multiplier module, and the gate of the fourth NMOS transistor serves as the positive terminal of the differential input of the second frequency multiplier module.
[0015] Optionally, the second resonance suppression unit includes a third inductor, a fourth inductor, a third capacitor, and a fourth capacitor. One end of the third inductor is connected to the drain of the third NMOS transistor, and the other end of the third inductor is connected to the third capacitor, the fourth capacitor, and the fourth inductor connected in series and then to the source of the third NMOS transistor.
[0016] Optionally, the switching control module includes a first switching unit and a first pull-down unit; the first switching unit includes a first PMOS transistor, a fifth NMOS transistor, a fifth inductor, a sixth inductor, a first resistor, and a second resistor, wherein the gate of the first PMOS transistor is connected to a first control signal via the first resistor in series, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor via the fifth inductor in series, the gate of the fifth NMOS transistor is connected to a second control signal via the second resistor in series, and the drain of the fifth NMOS transistor is connected to the source of the first NMOS transistor via the sixth inductor in series; the first pull-down unit includes a sixth NMOS transistor and a seventh NMOS transistor, wherein the drain of the sixth NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the sixth NMOS transistor is connected to the first control signal, the source of the sixth NMOS transistor is grounded, the drain of the seventh NMOS transistor is connected to the source of the second NMOS transistor, the gate of the seventh NMOS transistor is connected to the first control signal, and the source of the seventh NMOS transistor is grounded.
[0017] Optionally, the switching control module further includes a second switching unit and a second pull-down unit; the second switching unit includes a second PMOS transistor, an eighth NMOS transistor, a seventh inductor, an eighth inductor, a third resistor, and a fourth resistor, wherein the gate of the second PMOS transistor is connected to the second control signal via the third resistor in series, the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor via the seventh inductor in series, the gate of the eighth NMOS transistor is connected to the first control signal via the fourth resistor in series, and the drain of the eighth NMOS transistor is connected to the source of the third NMOS transistor via the eighth inductor in series; the second pull-down unit includes a ninth NMOS transistor and a tenth NMOS transistor, wherein the drain of the ninth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the ninth NMOS transistor is connected to the second control signal, the source of the ninth NMOS transistor is grounded, the drain of the tenth NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the tenth NMOS transistor is connected to the second control signal, and the source of the tenth NMOS transistor is grounded.
[0018] Optionally, the first control signal and the second control signal are inverted signals.
[0019] Optionally, the differential output module includes a first transformer and a second transformer. One end of the primary coil of the first transformer is connected to the operating voltage, and the other end of the primary coil of the first transformer is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively. One end of the primary coil of the second transformer is connected to the source of the fifth NMOS transistor and the source of the eighth NMOS transistor, respectively. The other end of the primary coil of the second transformer is grounded. One end of the secondary coil of the second transformer is connected to one end of the secondary coil of the first transformer. The other end of the secondary coil of the second transformer serves as the negative output terminal of the differential output module, and the other end of the secondary coil of the first transformer serves as the positive output terminal of the differential output module.
[0020] Optionally, the broadband low harmonic frequency multiplier circuit further includes a bias module, which includes a fifth resistor and a sixth resistor. One end of the fifth resistor is connected to the gate of the second NMOS transistor and the fourth NMOS transistor, and the other end of the fifth resistor is connected to the gate of the first NMOS transistor and the third NMOS transistor after passing through the sixth resistor in series. The common terminal of the fifth resistor and the sixth resistor is connected to a bias voltage.
[0021] As described above, the broadband low harmonic frequency multiplier circuit of the present invention has at least the following beneficial effects:
[0022] The first frequency doubling module includes a first resonant suppression unit for suppressing harmonic components of the output frequency, and the second frequency doubling module includes a second resonant suppression unit for suppressing harmonic components of the output frequency. The two frequency doubling modules each include a resonant suppression unit for suppressing harmonic components of the output frequency, which can effectively suppress harmonic components in the output frequency and reduce the harmonic output after frequency doubling. At the same time, the suppression frequency range of the first resonant suppression unit is different from that of the second resonant suppression unit. By combining the independent frequency doubling and harmonic suppression of the first and second frequency doubling modules, the frequency bandwidth of the frequency doubling output can be effectively extended. Attached Figure Description
[0023] Figure 1 The diagram shown is a circuit diagram of the broadband low harmonic frequency multiplier circuit in this invention.
[0024] Figure 2 The diagram shown is a circuit diagram of the control signal generation circuit for the broadband low harmonic frequency multiplier circuit in this invention.
[0025] Figure 3 The image shown is a low-frequency multiplication output spectrum diagram when the first multiplication module is selected in an optional embodiment of the present invention.
[0026] Figure 4 The image shown is a high-frequency multiplication output spectrum diagram when the first multiplication module is selected in an optional embodiment of the present invention.
[0027] Figure 5 The image shown is a low-frequency multiplication output spectrum diagram when the second multiplication module is selected in an optional embodiment of the present invention.
[0028] Figure 6 The image shown is a high-frequency multiplication output spectrum diagram when the second multiplication module is selected in an optional embodiment of the present invention. Detailed Implementation
[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0030] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.
[0031] As described in the background section, the inventors discovered that as the operating bandwidth continues to widen, especially when the frequency multiplier output frequency covers twice the octave, the frequency multiplier's ability to suppress harmonics in the low-frequency band decreases significantly, resulting in higher harmonic components at its output frequency and affecting its application in ultra-wideband applications. For ultra-wideband applications, especially those covering twice the octave or more, frequency multiplier circuits are required to have high bandwidth and low harmonic output frequency characteristics.
[0032] Based on this, the inventors of this invention propose a broadband low-harmonic frequency doubling technology: a resonant suppression unit is added to the frequency doubling structure to suppress harmonic components of the output frequency; at the same time, two parallel frequency doubling structures with different suppression frequency ranges of the resonant suppression units are designed, and the frequency bandwidth of the frequency doubling output is expanded through the independent frequency doubling and harmonic suppression of the two frequency doubling structures.
[0033] In detail, such as Figure 1As shown, the present invention provides a broadband low harmonic frequency multiplier circuit, which includes:
[0034] The first frequency multiplier module has its differential input terminal as the differential signal input terminal of the broadband low harmonic frequency multiplier circuit;
[0035] The differential input terminal of the second frequency multiplier module is connected in parallel with the differential input terminal of the first frequency multiplier module;
[0036] The differential output module has its input terminal connected to the output terminal of the first frequency multiplier module and the output terminal of the second frequency multiplier module, and its output terminal serves as the differential signal output terminal of the broadband low harmonic frequency multiplier circuit.
[0037] The switching control module is connected between the output terminal of the first frequency multiplier module and the input terminal of the differential output module, and between the output terminal of the second frequency multiplier module and the input terminal of the differential output module, and is also connected to the first frequency multiplier module and the second frequency multiplier module.
[0038] The first frequency doubling module includes a first resonant suppression unit for suppressing harmonic components of the output frequency, and the second frequency doubling module includes a second resonant suppression unit for suppressing harmonic components of the output frequency. The suppression frequency range of the first resonant suppression unit is different from that of the second resonant suppression unit. Under the control of the switching control module, one of the first frequency doubling module and the second frequency doubling module is selected for frequency doubling processing and output to the outside through the differential output module.
[0039] More in detail, such as Figure 1 As shown, the first frequency multiplier module further includes a first differential pair unit, which includes a first NMOS transistor N1 and a second NMOS transistor N2. The source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2, and the drain of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2. The gate of the first NMOS transistor N1 serves as the negative terminal of the differential input of the first frequency multiplier module and is connected to the negative terminal RFINN of the differential signal input of the broadband low harmonic frequency multiplier circuit. The gate of the second NMOS transistor N2 serves as the positive terminal of the differential input of the first frequency multiplier module and is connected to the positive terminal RFINP of the differential signal input of the broadband low harmonic frequency multiplier circuit.
[0040] More in detail, such as Figure 1 As shown, the first resonance suppression unit includes a first inductor L1, a second inductor L2, a first capacitor C1 and a second capacitor C2. One end of the first inductor L1 is connected to the drain of the first NMOS transistor N1, and the other end of the first inductor L1 is connected to the first capacitor C1, the second capacitor C2 and the second inductor L2 connected in series and then connected to the source of the first NMOS transistor N1.
[0041] More in detail, such as Figure 1As shown, the second frequency multiplier module also includes a second differential pair unit, which includes a third NMOS transistor N3 and a fourth NMOS transistor N4. The source of the third NMOS transistor N3 is connected to the source of the fourth NMOS transistor N4, and the drain of the third NMOS transistor N3 is connected to the drain of the fourth NMOS transistor N4. The gate of the third NMOS transistor N3 serves as the negative terminal of the differential input of the second frequency multiplier module, and the gate of the third NMOS transistor N3 is connected to the gate of the first NMOS transistor N1. The gate of the fourth NMOS transistor N4 serves as the positive terminal of the differential input of the second frequency multiplier module, and the gate of the fourth NMOS transistor N4 is connected to the gate of the second NMOS transistor N2.
[0042] More in detail, such as Figure 1 As shown, the second resonance suppression unit includes a third inductor L3, a fourth inductor L4, a third capacitor C3, and a fourth capacitor C4. One end of the third inductor L3 is connected to the drain of the third NMOS transistor N3, and the other end of the third inductor L3 is connected to the third capacitor C3, the fourth capacitor C4, and the fourth inductor L4 connected in series and then connected to the source of the third NMOS transistor N3.
[0043] More in detail, such as Figure 1 As shown, the switching control module includes a first switching unit and a first pull-down unit; the first switching unit includes a first PMOS transistor P1, a fifth NMOS transistor N5, a fifth inductor L5, a sixth inductor L6, a first resistor R1, and a second resistor R2. The gate of the first PMOS transistor P1 is connected to the first control signal selp via the first resistor R1 in series, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 via the fifth inductor L5 in series. The gate of the fifth NMOS transistor N5 is connected to the second control signal seln via the second resistor R2 in series. The drain of N5 is connected to the source of the first NMOS transistor N1 via the sixth inductor L6 connected in series. The first pull-down unit includes a sixth NMOS transistor N6 and a seventh NMOS transistor N7. The drain of the sixth NMOS transistor N6 is connected to the drain of the second NMOS transistor N2. The gate of the sixth NMOS transistor N6 is connected to the first control signal selp. The source of the sixth NMOS transistor N6 is grounded to VSS. The drain of the seventh NMOS transistor N7 is connected to the source of the second NMOS transistor N2. The gate of the seventh NMOS transistor N7 is connected to the first control signal selp. The source of the seventh NMOS transistor N7 is grounded to VSS.
[0044] More in detail, such as Figure 1As shown, the switching control module also includes a second switching unit and a second pull-down unit; the second switching unit includes a second PMOS transistor P2, an eighth NMOS transistor N8, a seventh inductor L7, an eighth inductor L8, a third resistor R3, and a fourth resistor R4. The gate of the second PMOS transistor P2 is connected to the second control signal seln via the third resistor R3 in series, and the drain of the second PMOS transistor P2 is connected to the drain of the third NMOS transistor N3 via the seventh inductor L7 in series. The gate of the eighth NMOS transistor N8 is connected to the first control signal selp via the fourth resistor R4 in series. The drain of transistor 8 is connected to the source of transistor 3 via the eighth inductor L8 connected in series; the second pull-down unit includes transistors 9 and 10. The drain of transistor 9 is connected to the drain of transistor 4. The gate of transistor 9 is connected to the second control signal seln. The source of transistor 9 is grounded to VSS. The drain of transistor 10 is connected to the source of transistor 4. The gate of transistor 10 is connected to the second control signal seln. The source of transistor 10 is grounded to VSS.
[0045] Wherein, the first control signal selp and the second control signal seln are inverted signals; in detail, as follows Figure 2 As shown, inverters inv1 and inv2 constitute a control signal generation circuit. The input terminal of inverter inv1 is connected to the initial control signal band_sel, and the output terminal of inverter inv1 outputs the second control signal seln. The output terminal of inverter inv1 is also connected to the input terminal of inverter inv2, and the output terminal of inverter inv2 outputs the first control signal selp.
[0046] More in detail, such as Figure 1 As shown, the differential output module includes a first transformer T1 and a second transformer T2. One end of the primary coil of the first transformer T1 is connected to the operating voltage VCC, and the other end of the primary coil of the first transformer T1 is connected to the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2, respectively. One end of the primary coil of the second transformer T2 is connected to the source of the fifth NMOS transistor N5 and the source of the eighth NMOS transistor N8, respectively. The other end of the primary coil of the second transformer T2 is grounded to VSS. One end of the secondary coil of the second transformer T2 is connected to one end of the secondary coil of the first transformer T1. The other end of the secondary coil of the second transformer T2 serves as the negative output terminal OUTN of the differential output module, and the other end of the secondary coil of the first transformer T1 serves as the positive output terminal OUTP of the differential output module.
[0047] More in detail, such as Figure 1As shown, the broadband low harmonic frequency multiplier circuit also includes a bias module, which includes a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is connected to the gates of the second NMOS transistor N2 and the fourth NMOS transistor N4. The other end of the fifth resistor R5 is connected to the gates of the first NMOS transistor N1 and the third NMOS transistor N3 via the sixth resistor R6 connected in series. The common terminal of the fifth resistor R5 and the sixth resistor R6 is connected to the bias voltage vb. The common-mode level of the input signal is clamped near the bias voltage vb.
[0048] In detail, such as Figure 1 As shown, the frequency multiplier circuit proposed in this invention consists of two frequency multiplier units: a first frequency multiplier module and a second frequency multiplier module. The first resonant suppression unit in the first frequency multiplier module has a lower suppression frequency range, while the second resonant suppression unit in the second frequency multiplier module has a higher suppression frequency range. The first frequency multiplier module can be used to achieve low-frequency multiplier frequency output, and the second frequency multiplier module can be used to achieve high-frequency multiplier frequency output. Adding a resonant suppression unit to the frequency multiplier structure to suppress harmonic components of the output frequency effectively suppresses these components. Furthermore, the first and second frequency multiplier modules are arranged in parallel, and the suppression frequency ranges of their resonant suppression units are different. Through the independent frequency multiplication and harmonic suppression of the first and second frequency multiplier modules, the frequency bandwidth of the multiplied output can be effectively expanded.
[0049] More in detail, such as Figure 1 As shown, in the first frequency multiplier module, the first inductor L1, the second inductor L2, the first capacitor C1, and the second capacitor C2 are connected in series to form a low-impedance resonant path, which suppresses the harmonic components of the output frequency; in the second frequency multiplier module, the third inductor L3, the fourth inductor L3, the third capacitor C3, and the fourth capacitor C4 are connected in series to form a low-impedance resonant path, which also suppresses the harmonic components of the output frequency.
[0050] More in detail, such as Figure 1 As shown, the output of the first frequency multiplier module is connected to the fifth inductor L5 and the sixth inductor L6, and the output of the second frequency multiplier module is connected to the seventh inductor L7 and the eighth inductor L8, which effectively improves the load capacity.
[0051] In detail, in an optional embodiment of the present invention, simulation experiments were conducted to demonstrate the beneficial effects of the broadband low-harmonic output frequency multiplier circuit of the present invention, and the frequency multiplier output spectrum diagram was obtained as follows. Figures 3-6 As shown. Figure 3 To select the low-frequency multiplication output spectrum when selecting the first multiplication module, the 2nd multiplication output frequency is 12GHz, the output power is -14.5dBm, the corresponding second harmonic frequency is 24GHz, the output power is -44.7dBm, and the harmonic suppression is 30.2dBc. Figure 4To select the high-frequency multiplication output spectrum when selecting the first multiplication module, the second multiplication output frequency is 18GHz, the output power is -15.8dBm, the corresponding second harmonic frequency is 36GHz, the output power is -43.1dBm, and the harmonic suppression is 27.3dBc; Figure 5 To select the low-frequency multiplication output spectrum when using the second multiplication module, the 2nd multiplication output frequency is 18GHz, the output power is -13.6dBm, the corresponding second harmonic frequency is 36GHz, the output power is -46.6dBm, and the harmonic suppression is 33dBc. Figure 6 To select the high-frequency output spectrum for the second harmonic generation module, the second harmonic output frequency is 24 GHz with an output power of -16.8 dBm. The corresponding second harmonic frequency is 48 GHz with an output power of -50.4 dBm, and the harmonic suppression is 33.6 dBc. This means that within the input frequency range of 6 GHz to 12 GHz, and with a harmonic output frequency range of 12 GHz to 24 GHz, the harmonic suppression capability of this invention is better than 27.3 dBc, achieving both wideband second harmonic output and superior harmonic suppression.
[0052] The above implementation results show that the broadband low harmonic output frequency multiplier circuit proposed in this invention has excellent harmonic suppression performance when achieving broadband frequency multiplication of 2 octaves, and can be applied to the local oscillator system of ultra-wideband wireless communication.
[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A broadband low-harmonic frequency multiplier circuit, characterized in that, include: The first frequency multiplier module has its differential input terminal as the differential signal input terminal of the broadband low harmonic frequency multiplier circuit. The differential input terminal of the second frequency multiplier module is connected in parallel with the differential input terminal of the first frequency multiplier module; A differential output module, whose input terminal is connected to the output terminal of the first frequency multiplier module and the output terminal of the second frequency multiplier module, and whose output terminal serves as the differential signal output terminal of the broadband low harmonic frequency multiplier circuit; A switching control module is connected between the output terminal of the first frequency multiplier module and the input terminal of the differential output module, and between the output terminal of the second frequency multiplier module and the input terminal of the differential output module, and is also connected to the first frequency multiplier module and the second frequency multiplier module; The first frequency doubling module includes a first resonant suppression unit for suppressing harmonic components of the output frequency, and the second frequency doubling module includes a second resonant suppression unit for suppressing harmonic components of the output frequency. The suppression frequency range of the first resonant suppression unit is different from that of the second resonant suppression unit. Under the control of the switching control module, one of the first and second frequency doubling modules is selected for frequency doubling processing and output through the differential output module. The first frequency multiplier module further includes a first differential pair unit, which includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor serves as the negative terminal of the differential input of the first frequency multiplier module, and the gate of the second NMOS transistor serves as the positive terminal of the differential input of the first frequency multiplier module. The first resonance suppression unit includes a first inductor, a second inductor, a first capacitor, and a second capacitor. One end of the first inductor is connected to the drain of the first NMOS transistor, and the other end of the first inductor is connected to the first capacitor, the second capacitor, and the second inductor connected in series and then connected to the source of the first NMOS transistor. The switching control module includes a first switching unit and a first pull-down unit. The first switching unit includes a first PMOS transistor, a fifth NMOS transistor, a fifth inductor, a sixth inductor, a first resistor, and a second resistor. The gate of the first PMOS transistor is connected to a first control signal via the first resistor in series. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor via the fifth inductor in series. The gate of the fifth NMOS transistor is connected to a second control signal via the second resistor in series. The drain of the fifth NMOS transistor is connected to the source of the first NMOS transistor via the sixth inductor in series. The first pull-down unit includes a sixth NMOS transistor and a seventh NMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the sixth NMOS transistor is connected to the first control signal. The source of the sixth NMOS transistor is grounded. The drain of the seventh NMOS transistor is connected to the source of the second NMOS transistor. The gate of the seventh NMOS transistor is connected to the first control signal. The source of the seventh NMOS transistor is grounded.
2. The broadband low harmonic frequency multiplier circuit according to claim 1, characterized in that, The second frequency multiplier module further includes a second differential pair unit, which includes a third NMOS transistor and a fourth NMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the third NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the third NMOS transistor serves as the negative terminal of the differential input of the second frequency multiplier module, and the gate of the fourth NMOS transistor serves as the positive terminal of the differential input of the second frequency multiplier module.
3. The broadband low harmonic frequency multiplier circuit according to claim 2, characterized in that, The second resonance suppression unit includes a third inductor, a fourth inductor, a third capacitor, and a fourth capacitor. One end of the third inductor is connected to the drain of the third NMOS transistor, and the other end of the third inductor is connected to the third capacitor, the fourth capacitor, and the fourth inductor connected in series and then to the source of the third NMOS transistor.
4. The broadband low harmonic frequency multiplier circuit according to claim 2, characterized in that, The switching control module further includes a second switching unit and a second pull-down unit. The second switching unit includes a second PMOS transistor, an eighth NMOS transistor, a seventh inductor, an eighth inductor, a third resistor, and a fourth resistor. The gate of the second PMOS transistor is connected to the second control signal via the third resistor in series. The drain of the second PMOS transistor is connected to the drain of the third NMOS transistor via the seventh inductor in series. The gate of the eighth NMOS transistor is connected to the first control signal via the fourth resistor in series. The drain of the eighth NMOS transistor is connected to the source of the third NMOS transistor via the eighth inductor in series. The second pull-down unit includes a ninth NMOS transistor and a tenth NMOS transistor. The drain of the ninth NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the ninth NMOS transistor is connected to the second control signal. The source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the tenth NMOS transistor is connected to the second control signal. The source of the tenth NMOS transistor is grounded.
5. The broadband low harmonic frequency multiplier circuit according to claim 4, characterized in that, The first control signal and the second control signal are inverse signals.
6. The broadband low harmonic frequency multiplier circuit according to claim 5, characterized in that, The differential output module includes a first transformer and a second transformer. One end of the primary coil of the first transformer is connected to the operating voltage, and the other end of the primary coil of the first transformer is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively. One end of the primary coil of the second transformer is connected to the source of the fifth NMOS transistor and the source of the eighth NMOS transistor, respectively. The other end of the primary coil of the second transformer is grounded. One end of the secondary coil of the second transformer is connected to one end of the secondary coil of the first transformer. The other end of the secondary coil of the second transformer serves as the negative output terminal of the differential output module, and the other end of the secondary coil of the first transformer serves as the positive output terminal of the differential output module.
7. The broadband low harmonic frequency multiplier circuit according to claim 6, characterized in that, The broadband low harmonic frequency multiplier circuit also includes a bias module, which includes a fifth resistor and a sixth resistor. One end of the fifth resistor is connected to the gate of the second NMOS transistor and the fourth NMOS transistor, and the other end of the fifth resistor is connected to the gate of the first NMOS transistor and the third NMOS transistor after passing through the sixth resistor in series. The common terminal of the fifth resistor and the sixth resistor is connected to the bias voltage.
Citation Information
Patent Citations
Millimeter-wave frequency multiplier and cascaded frequency multipliers
CN102104362A
The reconfigurable injection locking multi-mode single-ended output frequency multiplier is used for ultra-wideband millimeter wave reconfigurable injection locking multi-mode single-ended output frequency multiplier
CN112350669A