A low noise amplifier, a receiver and a wireless communication system

Abstract

The application discloses a low-noise amplifier, a receiver and a wireless communication system, which realizes protection of a low-noise amplifier from a large input signal in a case where the low-noise amplifier is closed, and minimizes negative influence on normal operation of the low-noise amplifier. The low-noise amplifier comprises a low-noise amplification circuit and a limiting circuit; wherein the limiting circuit is used for being closed in a case where the low-noise amplification circuit is normally operated and being opened in a case where the low-noise amplification circuit is closed under control of an external control signal, and the limiting circuit limits an input signal of the low-noise amplification circuit after being opened.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically, to a low-noise amplifier, a receiver, and a wireless communication system. Background Technology

[0002] An LNA (Low Noise Amplifier) ​​is a small-signal amplifier with excellent noise characteristics and high gain. It is generally located at the front end of the receiver in a wireless communication system and is a key component that determines the noise characteristics of the entire receiver.

[0003] LNAs are susceptible to damage when subjected to large input signals. Currently, there are mechanisms in place to protect LNAs from damage by large input signals during normal operation, but there are no corresponding protection mechanisms for when the LNA is turned off. Summary of the Invention

[0004] In view of this, the present invention provides a low-noise amplifier, a receiver, and a wireless communication system to protect the low-noise amplifier from damage by large input signals when the low-noise amplifier is turned off, and to minimize the negative impact on the normal operation of the low-noise amplifier.

[0005] A low-noise amplifier, characterized in that it comprises: a low-noise amplification circuit and a limiting circuit;

[0006] The limiting circuit is used to be turned off when the low-noise amplifier circuit is working normally under the control of an external control signal, and turned on when the low-noise amplifier circuit is turned off. After being turned on, the limiting circuit limits the input signal of the low-noise amplifier circuit.

[0007] Optionally, the differential input terminal of the low-noise amplifier circuit is connected to the control terminal of the differential amplifier tube in the high-gain channel through a differential coupling capacitor; the differential amplifier tube includes amplifier tube M11 and amplifier tube M12;

[0008] The limiting circuit includes a pull-down capacitor module, which includes: pull-down capacitor C3, pull-down capacitor C4, switching transistor M1, and switching transistor M2.

[0009] Among them, the first end of the pull-down capacitor C3 is connected to the control terminal of the amplifier tube M11;

[0010] The second terminal of the pull-down capacitor C3 is connected to the first terminal of the switching transistor M1;

[0011] The first terminal of the pull-down capacitor C4 is connected to the control terminal of the amplifier transistor M12;

[0012] The second terminal of the pull-down capacitor C4 is connected to the first terminal of the switching transistor M2;

[0013] The second terminals of both switching transistors M1 and M2 are grounded.

[0014] Optionally, the limiting circuit further includes a differential short-circuit switch, which comprises one or more switching transistors connected in series.

[0015] Optionally, the differential short-circuit switch includes two switching transistors connected in series.

[0016] Optionally, the low-noise amplifier circuit includes: a balun B1, a tuning capacitor C5, a coupling capacitor C1, a coupling capacitor C2, a high-gain channel HG, and a low-gain channel LG;

[0017] Among them, the tuning capacitor C5 is connected in parallel to the differential output terminal of the balun B1;

[0018] The first terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C1, and the second terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C2.

[0019] The low-gain channel LG includes switching transistors M7 and M8;

[0020] The second terminal of coupling capacitor C1 is connected to the control terminal of amplifier transistor M11 and the second terminal of switching transistor M7.

[0021] The second terminal of the coupling capacitor C2 is connected to the control terminal of the amplifier transistor M12 and the second terminal of the switching transistor M8.

[0022] Optionally, the parasitic capacitances of pull-down capacitor C3 and C4, along with coupling capacitors C1 and C2, resonate with balun B1 to achieve impedance matching.

[0023] Optionally, the differential input terminal of the low-noise amplifier circuit is connected to the second terminal of the differential switch in the low-gain channel through a differential coupling capacitor; the differential switch includes switch M7 and switch M8;

[0024] The limiting circuit includes a charge discharge module; the charge discharge module includes: switching transistors M5, M6, M9, and M10, as well as resistors R1 and R2;

[0025] Among them, the first end of the switching transistor M9 is connected to the first end of the switching transistor M7;

[0026] The first terminal of switching transistor M10 is connected to the first terminal of switching transistor M8;

[0027] The second terminal of switching transistor M9 is connected to the second terminal of switching transistor M10;

[0028] The second terminal of switching transistor M6 is connected to the second terminal of switching transistor M7;

[0029] The control terminal of switching transistor M6 is connected to the control terminal of switching transistor M7.

[0030] The second terminal of switching transistor M5 is connected to the second terminal of switching transistor M8;

[0031] The control terminal of switching transistor M5 is connected to the control terminal of switching transistor M8.

[0032] The first terminal of switch M5 is grounded through resistor R1, and the first terminal of switch M6 is grounded through resistor R2.

[0033] Optionally, the low-noise amplifier circuit includes: a balun B1, a tuning capacitor C5, a coupling capacitor C1, a coupling capacitor C2, a high-gain channel HG, and a low-gain channel LG;

[0034] Among them, the tuning capacitor C5 is connected in parallel to the differential output terminal of the balun B1;

[0035] The first terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C1, and the second terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C2.

[0036] The high-gain channel HG includes amplifier tubes M11 and M12;

[0037] The second terminal of coupling capacitor C1 is connected to the control terminal of amplifier transistor M11 and the second terminal of switching transistor M7.

[0038] The second terminal of the coupling capacitor C2 is connected to the control terminal of the amplifier transistor M12 and the second terminal of the switching transistor M8.

[0039] Optionally, the switching transistors in the limiting circuit are all MOS transistors, with the first terminal of the switching transistor being the drain of the MOS transistor, the second terminal of the switching transistor being the source of the MOS transistor, and the control terminal of the switching transistor being the gate of the MOS transistor.

[0040] A receiver comprising: any of the low-noise amplifiers disclosed above.

[0041] A wireless communication system includes: a transmitter and any of the receivers disclosed above.

[0042] As can be seen from the above technical solution, the present invention adds a limiting circuit to the traditional LNA. The limiting circuit is turned on when the LNA is off, and after it is turned on, it limits the amplitude of the input signal of the LNA, thereby limiting the amplitude of the leaked signal to the safe input strength range of the LNA. This achieves the protection of the LNA from damage by large input signals when the LNA is off. Moreover, the limiting circuit is turned off when the LNA is working normally and is only turned on when the LNA is off, so as to minimize the negative impact on the normal operation of the LNA. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram of a wireless communication system structure disclosed in the prior art;

[0045] Figure 2 A schematic diagram of a low-noise amplifier circuit disclosed in the prior art;

[0046] Figure 3 This is a schematic diagram of a low-noise amplifier circuit disclosed in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of another low-noise amplifier circuit disclosed in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of another low-noise amplifier circuit disclosed in an embodiment of the present invention. Detailed Implementation

[0049] For the sake of clarity and reference, the technical terms, abbreviations, or acronyms used below are summarized as follows:

[0050] LNA: Low Noise Amplifier;

[0051] RX: Receiver;

[0052] TX: Transmitter;

[0053] TDD: Time Division Duplexing;

[0054] WI-FI: Wireless-Fidelity.

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] This invention discloses an LNA, comprising: a low-noise amplifier circuit (i.e., the core circuit for the LNA to perform basic functions, the on / off state of the low-noise amplifier circuit represents the on / off state of the LNA, and the input signal of the low-noise amplifier circuit is the input signal of the LNA) and a limiting circuit (i.e., a protection circuit added to a traditional LNA in this invention embodiment); wherein, the limiting circuit is used to be turned off when the low-noise amplifier circuit is working normally under the control of an external control signal, and turned on when the low-noise amplifier circuit is turned off, and the limiting circuit limits the input signal of the low-noise amplifier circuit after being turned on.

[0057] The working principle of the embodiments of the present invention will be described in detail below:

[0058] LNAs are typically located at the front end of the RX in a wireless communication system. For example... Figure 1 As shown, the RX in the wireless communication system includes an LNA1, a down-mixer 2, and a low-pass filter 3. The TX in the wireless communication system includes a power amplifier 4, an up-mixer 5, and another low-pass filter 6. Since the LNA is located in front of the RX, it is easily damaged when the TX emits a high-power signal (especially when the TX and RX share an antenna 7, in which case the TX is closest to the RX, and the high-power signal emitted by the TX has the greatest destructive effect on the LNA). Currently, there are mechanisms to protect the LNA from damage by large input signals under normal operating conditions, but there is no corresponding protection mechanism for the LNA when it is off. In this embodiment of the invention, a limiting circuit is specifically designed for the LNA when it is off. The limiting circuit is turned on when the LNA is off, and after it is turned on, it limits the amplitude of the input signal of the LNA, thereby limiting the amplitude of the leaked signal to within the safe input strength range of the LNA, thus protecting the LNA from damage by large input signals when it is off. Moreover, the limiting circuit is turned off when the LNA is working normally and is only turned on when the LNA is off, so as to minimize the negative impact on the normal operation of the LNA.

[0059] The wireless communication system is, for example, a TDD-based wireless communication system, which may be a Wi-Fi system or a Bluetooth system, and is not limited thereto.

[0060] The LNA operates normally in two modes: high gain and low gain. The differential input terminal of the low-noise amplifier circuit is connected to the control terminal of the differential amplifier transistor in the high-gain channel via a differential coupling capacitor. At the same time, the differential input terminal is also connected to the second terminal of the differential switch transistor in the low-gain channel via the differential coupling capacitor.

[0061] Optional, see Figure 2 ( Figure 2 Taking the example of TX and RX sharing a single antenna, the low-noise amplifier circuit includes: a balun B1, a tuning capacitor C5, a coupling capacitor C1, a coupling capacitor C2 (coupling capacitor C1 and coupling capacitor C2 constitute the differential coupling capacitor), a high-gain channel HG, and a low-gain channel LG.

[0062] Among them, the balun B1 is a broadband radio frequency transmission line transformer that enables the connection between balanced and unbalanced transmission line circuits by converting single-ended inputs to differential outputs.

[0063] The tuning capacitor C5 is connected in parallel to the differential output terminal of the balun B1; the differential output terminal of the balun B1 is the differential input terminal of the low-noise amplifier circuit.

[0064] The first terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C1, and the second terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C2.

[0065] The high-gain channel HG includes amplifier tubes M11, M12, M13, and M14, as well as other devices (not listed in the original text). Figure 2 (shown in full), the second ends of amplifier tubes M11 and M12 are both grounded to VSS, the first end of amplifier tube M11 is connected to the second end of amplifier tube M13; the first end of amplifier tube M12 is connected to the second end of amplifier tube M14; amplifier tubes M11 and M12 constitute the differential amplifier tube;

[0066] The low-gain channel LG includes switching transistors M7 and M8, and other devices (not listed in the original text). Figure 2 (All shown in the image); Switch M7 and switch M8 constitute the differential switch;

[0067] The second terminal A of the coupling capacitor C1 is connected to the control terminal of the amplifier transistor M11 and the second terminal of the switching transistor M7.

[0068] The second terminal B of the coupling capacitor C2 is connected to the control terminal of the amplifier transistor M12 and the second terminal of the switching transistor M8.

[0069] The amplifying transistor / switching transistor mentioned in the embodiments of the present invention is preferably a MOS transistor (the same below), but is not limited thereto; the amplifying transistor / switching transistor is a three-terminal device. When the amplifying transistor / switching transistor is a MOS transistor, the first terminal of the amplifying transistor / switching transistor is the drain of the MOS transistor, the second terminal of the amplifying transistor / switching transistor is the source of the MOS transistor, and the control terminal of the amplifying transistor / switching transistor, i.e., the third terminal, is the gate of the MOS transistor.

[0070] exist Figure 2 In a fully functional LNA, there are two modes: high gain and low gain. In high gain mode, the high-gain channel HG is on (amplifier transistors M11, M12, M13, and M14 are all turned on), while the low-gain channel LG is off (switches M7 and M8 are both off). The LNA first converts the externally input single-ended signal into a differential signal via balun B1 and tuning capacitor C5, then sends it to the control terminals of amplifier transistors M11 and M12 via coupling capacitors C1 and C2, and finally amplifies it via amplifier transistors M13 and M14. In low gain mode, the high-gain channel HG is off (amplifier transistors M11, M12, M13, and M14 are all off), while the low-gain channel LG is on (switches M7 and M8 are both turned on). The LNA first converts the externally input single-ended signal into a differential signal via balun B1 and tuning capacitor C5, then sends it to the attenuation array via coupling capacitors C1 and C2 and switches M7 and M8 for attenuation, before further amplification.

[0071] LNAs are prone to damage when subjected to large input signals, mainly referring to the impact of large input signals on the differential amplifier transistors in high-gain channels (see...). Figure 2 Damage to the control terminals of M11 and M12 in the circuit. To address this, embodiments of the present invention introduce a limiting circuit, such as... Figure 3 As shown ( Figure 3 Limited circuits are only used in Figure 2 The low-noise amplifier circuit shown is used as an example, but it is not limited to applications in this area. Figure 2 The low-noise amplifier circuit shown includes a limiting circuit comprising a pull-down capacitor module, which includes pull-down capacitor C3, pull-down capacitor C4, switching transistor M1, and switching transistor M2.

[0072] The first terminal of the pull-down capacitor C3 is connected to the control terminal A of the amplifier transistor M11;

[0073] The second terminal of the pull-down capacitor C3 is connected to the first terminal of the switching transistor M1;

[0074] The first terminal of the pull-down capacitor C4 is connected to the control terminal B of the amplifier transistor M12;

[0075] The second terminal of the pull-down capacitor C4 is connected to the first terminal of the switching transistor M2;

[0076] The second terminals of both switching transistors M1 and M2 are grounded to VSS.

[0077] exist Figure 3 In this circuit, the limiting circuit is off when switching transistors M1 and M2 are off, and on when switching transistors M1 and M2 are on. After the limiting circuit is on (at this time, switching transistors M1 and M2 are on, while amplifier transistors M11, M12, M13, M14, and switching transistors M7 and M8 are all off), coupling capacitor C1 and pull-down capacitor C3 are connected in series to divide the voltage, and coupling capacitor C2 and pull-down capacitor C4 are connected in series to divide the voltage. By selecting appropriate values ​​for C1, C2, C3, and C4, the control terminal voltage V of amplifier transistor M11 can be controlled. A The control terminal voltage V of M12 B Limited to the withstand voltage value V specified in the process. max Within this range, the large input signal is amplified, preventing damage to amplifier transistors M11 and M12. Voltage V A and V B The expression is as follows:

[0078]

[0079]

[0080] Among them, V P V is the voltage at the first terminal of the differential output of balun B1. N This is the voltage at the second terminal of the differential output of balun B1.

[0081] Furthermore, considering that after the limiting circuit is activated, the higher the impedance to ground at point A, the greater the signal amplitude at point A; similarly, the higher the impedance to ground at point B, the greater the signal amplitude at point B. Therefore, to further reduce the signal amplitudes at points A and B, this embodiment of the invention adds a differential short-circuit switch to the aforementioned pull-down capacitor module. The differential short-circuit switch includes one or more switching transistors connected in series. Figure 4 The example uses only two switching transistors, M3 and M4, connected in series. The principle analysis is as follows:

[0082] Before the introduction of differential short-circuit switches, see Figure 3 After the limiting circuit is turned on, the impedance Z of point A to ground is... AC = Capacitor C3 Impedance Z C3 + On-resistance Z of switch M1 M1 The impedance Z of point B to ground BC = Capacitor C4 Impedance Z C4 + On-resistance Z of switch M2 M2 ;

[0083] After the introduction of a differential short-circuit switch, see... Figure 4After the limiting circuit is turned on (at this time, switches M1, M2, M3, and M4 are turned on, while amplifiers M11, M12, M13, and M14, and switches M7 and M8 are all turned off), the differential signals leaking from points A and B into this branch of the differential short-circuit switch cancel each other out at the intermediate node of the differential short-circuit switch. Therefore, this intermediate node is equivalent to a virtual ground VSS. Taking the differential short-circuit switch as an example of switches M3 and M4 connected in series, this intermediate node is the connection point of M3 and M4. At this time, the on-resistance Z of switch M3 is... M3 The on-resistance Z of the switching transistor M1 M1 In parallel connection, the on-resistance Z of switching transistor M4 M4 The on-resistance Z of the switching transistor M2 M2 The parallel connection has the following expressions for the impedance of points A and B to ground:

[0084] Z AC =Z C3 +Z M1 / / Z M3 (Equation 3)

[0085] Z BD =Z C4 +Z M2 / / Z M4 (Equation 4)

[0086] In the formula, the symbol " / / " indicates parallel connection. Z M1 / / Z M3 Z represents M1 With Z M3 The impedance after parallel connection, Z M2 / / Z M4 Z represents M2 With Z M2 The impedance after parallel connection.

[0087] Clearly, after introducing the differential short-circuit switch and activating the limiting circuit, the impedance to ground at points A and B decreases, thus further reducing the signal amplitude at points A and B. When the number of series-connected switching transistors within the differential short-circuit switch changes, it affects the signal amplitude at points Z. M1 The magnitude of the impedance after parallel connection and its relationship with Z M2 The impedance changes after parallel connection. The fewer the number of switching transistors connected in series inside the differential short-circuit switch, the smaller the impedance to ground at points A and B, and the lower the signal amplitude at points A and B.

[0088] Additionally, see also Figure 4Parasitic capacitance exists between the first and second terminals of the switching transistor. For a differential short-circuit switch composed of multiple switching transistors connected in series, the parasitic capacitances of each internal switching transistor are connected in series to form the total parasitic capacitance of the differential short-circuit switch. When the LNA is working normally, the differential signal leaking from points A and B into this branch of the differential short-circuit switch will flow through the total parasitic capacitance of the differential short-circuit switch and cancel each other out, reducing the gain of the LNA. The more switching transistors connected in series inside the differential short-circuit switch, the smaller the total parasitic capacitance of the differential short-circuit switch, the larger the total impedance of the differential short-circuit switch, and the less differential signal leaks from points A and B into this branch of the differential short-circuit switch, thus having a smaller impact on the gain of the LNA. To achieve a compromise between "maximizing the impact of the differential short-circuit switch on the signal amplitude at points A and B after the limiting circuit is turned on" and "minimizing the impact of the differential short-circuit switch on the gain of the LNA when it is working normally," this embodiment of the invention recommends setting the number of switching transistors connected in series inside the differential short-circuit switch to two.

[0089] Furthermore, based on Figure 3 and Figure 4 In the illustrated embodiment, the first terminals of pull-down capacitors C3 and C4 have large parasitic capacitances. These parasitic capacitances negatively impact the gain of the LNA during normal operation. Therefore, in parameter design, this embodiment recommends that the parasitic capacitances of pull-down capacitors C3 and C4, along with coupling capacitors C1 and C2, resonate with the balun B1 to achieve impedance matching, thereby reducing the impact of these parasitic capacitances on the LNA's gain during normal operation.

[0090] In another embodiment, still taking the differential switches in the low-gain channel, including switches M7 and M8, as an example, the limiting circuit includes a charge discharge module, such as... Figure 5 As shown ( Figure 5 Limited circuits are only used in Figure 2 The low-noise amplifier circuit shown is used as an example, but it is not limited to applications in this area. Figure 2 The low-noise amplifier circuit shown includes a charge discharge module comprising switching transistors M5, M6, M9, and M10, as well as resistors R1 and R2. The first terminal E of switching transistor M9 is connected to the first terminal of switching transistor M7; the first terminal F of switching transistor M10 is connected to the first terminal of switching transistor M8; the second terminal of switching transistor M9 is connected to the second terminal of switching transistor M10; the second terminal of switching transistor M6 is connected to the second terminal of switching transistor M7; the control terminal of switching transistor M6 is connected to the control terminal of switching transistor M7; the second terminal of switching transistor M5 is connected to the second terminal of switching transistor M8; the control terminal of switching transistor M5 is connected to the control terminal of switching transistor M8; the first terminal of switching transistor M5 is grounded to VSS via resistor R1; and the first terminal of switching transistor M6 is grounded to VSS via resistor R2.

[0091] exist Figure 5 In this circuit, switching transistors M5 and M8 are simultaneously on and off, and switching transistors M6 and M7 are simultaneously on and off. The limiting circuit is off when switching transistors M9 and M10 are off, and on when it is on, switching transistors M9 and M10 are on. After the limiting circuit is on (at this time, switching transistors M9 and M10 are on, and amplifier transistors M11, M12, M13, M14, and switching transistors M5, M6, M7, and M8 are all off), the charge leaking from point A is discharged to ground through the parasitic capacitance of switching transistor M7 and switching transistor M9, and the charge leaking from point B is discharged to ground through the parasitic capacitance of switching transistor M8 and switching transistor M10. However, because the parasitic capacitances of switching transistors M7 and M8 are very small, their charge discharge capability is insufficient. Therefore, this embodiment of the invention further introduces switching transistors M6 and M5 to increase the parasitic capacitance between points A and E, and between points B and F. The principle analysis is as follows:

[0092] After introducing switching transistors M6 and M5, the impedance Z between points A and E is... AE The impedance Z between points B and F BF Satisfy the following expression:

[0093]

[0094]

[0095] In the formula, C gs_M7 The value C represents the parasitic capacitance between the control terminal and the third terminal of the switching transistor M7. gs_M6 The parasitic capacitance C between the control terminal and the third terminal of the switching transistor M6 is indicated. gd_M7 The parasitic capacitance C between the control terminal and the first terminal of the switching transistor M7 is indicated. gs_M8 The parasitic capacitance C between the control terminal and the third terminal of the switching transistor M8 is indicated. gs_M5 The parasitic capacitance C between the control terminal and the third terminal of the switching transistor M5 is indicated. gd_M8 This represents the parasitic capacitance between the control terminal and the first terminal of the switching transistor M8. Impedance Z AE Z BF Compared to before the introduction of switching transistors M6 and M7, the parasitic capacitance between points A and E, and between points B and F, is smaller. Therefore, the limiting circuit has a stronger ability to reduce the amplitude of leaked signals after it is turned on.

[0096] Resistors R1 and R2 are used to prevent the input differential signal from being discharged to ground through switches M6 and M5 when the LNA is working normally in low gain mode, thus ensuring the signal quality and energy of the input low gain channel LG.

[0097] The charge discharge module disclosed in the above embodiments can be used alone, or in combination with a pull-down capacitor module, or in combination with a pull-down capacitor module and a differential short-circuit switch, and is not limited thereto.

[0098] Furthermore, embodiments of the present invention also disclose a receiver, including any of the low-noise amplifiers disclosed above.

[0099] This invention also discloses a wireless communication system, including a transmitter and any of the receivers disclosed above.

[0100] Optionally, the wireless communication system is a time-division multiplexing-based wireless communication system.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0102] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the invention. Therefore, the embodiments of the invention are not to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-noise amplifier, characterized in that, include: Low-noise amplifier circuits and limiting circuits; The limiting circuit is used to be turned off when the low-noise amplifier circuit is working normally under the control of an external control signal, and turned on when the low-noise amplifier circuit is turned off. After being turned on, the limiting circuit limits the input signal of the low-noise amplifier circuit. The differential input terminal of the low-noise amplifier circuit is connected to the control terminal of the differential amplifier tube in the high-gain channel through a differential coupling capacitor; the differential amplifier tube includes amplifier tube M11 and amplifier tube M12; The limiting circuit includes a pull-down capacitor module, which includes: pull-down capacitor C3, pull-down capacitor C4, switching transistor M1, and switching transistor M2. Among them, the first end of the pull-down capacitor C3 is connected to the control terminal of the amplifier tube M11; The second terminal of the pull-down capacitor C3 is connected to the first terminal of the switching transistor M1; The first terminal of the pull-down capacitor C4 is connected to the control terminal of the amplifier transistor M12; The second terminal of the pull-down capacitor C4 is connected to the first terminal of the switching transistor M2; The second terminals of both switching transistors M1 and M2 are grounded; The limiting circuit also includes a differential short-circuit switch, which includes one or more switching transistors connected in series. The differential short-circuit switch includes switching transistor M3 and switching transistor M4. One end of switching transistor M3 is connected to the second end of the pull-down capacitor C3, and the other end of switching transistor M3 is connected to one end of switching transistor M4. The other end of switching transistor M4 is connected to the second end of the pull-down capacitor C4. The connection point between switching transistor M3 and switching transistor M4 forms a virtual grounding node.

2. The low-noise amplifier according to claim 1, characterized in that, The differential short-circuit switch includes two switching transistors connected in series.

3. The low-noise amplifier according to any one of claims 1 or 2, characterized in that, The low-noise amplifier circuit includes: balun B1, tuning capacitor C5, coupling capacitor C1, coupling capacitor C2, high-gain channel HG, and low-gain channel LG. Among them, the tuning capacitor C5 is connected in parallel to the differential output terminal of the balun B1; The first terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C1, and the second terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C2. The low-gain channel LG includes switching transistors M7 and M8; The second terminal of coupling capacitor C1 is connected to the control terminal of amplifier transistor M11 and the second terminal of switching transistor M7. The second terminal of the coupling capacitor C2 is connected to the control terminal of the amplifier transistor M12 and the second terminal of the switching transistor M8.

4. The low-noise amplifier according to claim 3, characterized in that, The parasitic capacitances of pull-down capacitor C3 and C4, along with coupling capacitors C1 and C2, resonate with balun B1 to achieve impedance matching.

5. The low-noise amplifier according to claim 1, characterized in that, The differential input terminal of the low-noise amplifier circuit is connected to the second terminal of the differential switch transistor in the low-gain channel through a differential coupling capacitor; the differential switch transistor includes switch transistor M7 and switch transistor M8; The limiting circuit includes a charge discharge module; the charge discharge module includes: switching transistors M5, M6, M9, and M10, as well as resistors R1 and R2; Among them, the first end of the switching transistor M9 is connected to the first end of the switching transistor M7; The first terminal of switching transistor M10 is connected to the first terminal of switching transistor M8; The second terminal of switching transistor M9 is connected to the second terminal of switching transistor M10; The second terminal of switching transistor M6 is connected to the second terminal of switching transistor M7; The control terminal of switching transistor M6 is connected to the control terminal of switching transistor M7. The second terminal of switching transistor M5 is connected to the second terminal of switching transistor M8; The control terminal of switching transistor M5 is connected to the control terminal of switching transistor M8. The first terminal of switch M5 is grounded through resistor R1, and the first terminal of switch M6 is grounded through resistor R2.

6. The low-noise amplifier according to claim 5, characterized in that, The low-noise amplifier circuit includes: balun B1, tuning capacitor C5, coupling capacitor C1, coupling capacitor C2, high-gain channel HG, and low-gain channel LG. Among them, the tuning capacitor C5 is connected in parallel to the differential output terminal of the balun B1; The first terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C1, and the second terminal of the differential output of balun B1 is connected to the first terminal of coupling capacitor C2. The high-gain channel HG includes amplifier tubes M11 and M12; The second terminal of coupling capacitor C1 is connected to the control terminal of amplifier transistor M11 and the second terminal of switching transistor M7. The second terminal of the coupling capacitor C2 is connected to the control terminal of the amplifier transistor M12 and the second terminal of the switching transistor M8.

7. The low-noise amplifier according to claim 1 or 5, characterized in that, The switching transistors in the limiting circuit are all MOSFETs. Correspondingly, the first terminal of the switching transistor is the drain of the MOSFET, the second terminal of the switching transistor is the source of the MOSFET, and the control terminal of the switching transistor is the gate of the MOSFET.

8. A receiver, characterized in that, include: The low-noise amplifier as described in any one of claims 1 to 7.

9. A wireless communication system, characterized in that, include: The transmitter and the receiver as described in claim 8.

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