Photoelectric conversion device, driving method thereof, imaging system, mobile body, and apparatus

Abstract

The present application provides a photoelectric conversion device and a driving method thereof, an imaging system, a mobile body, and an apparatus. The disclosed photoelectric conversion device includes: a pixel including a photoelectric conversion unit; an AD conversion unit configured to AD-convert an analog signal generated in the pixel; and a control unit configured to control the AD conversion unit. The control unit is configured to control the AD conversion unit to perform a plurality of AD conversions on the same analog signal. A length of a first AD conversion period in the plurality of AD conversions is shorter than a length of a second AD conversion period in the plurality of AD conversions. A rate of change of a reference signal in the second AD conversion period is smaller than a rate of change of the reference signal in the first AD conversion period. In each of the first AD conversion period and the second AD conversion period, a potential of the reference signal changes by a first level.

Description

Technical Field

[0001] This disclosure relates to a photoelectric conversion device and a method for driving the photoelectric conversion device. Background Technology

[0002] In photoelectric conversion devices such as solid-state cameras, improving the signal-to-noise ratio (S / N ratio) requires reduced noise levels, expanded dynamic range, and high-speed readout. In response to this demand, Japanese Patent Application Publication No. 2015-128253 discloses a technique for expanding the dynamic range by setting multiple amplifiers that amplify the output signal from the imaging element with different amplification factors, and selecting / combining the signal outputs of these multiple amplifiers according to the brightness of the subject. Japanese Patent Application Publication No. 2016-054424 discloses a technique for increasing speed by changing the length of the time period for analog-to-digital conversion of the amplifier's output signal according to the amplifier's amplification factor.

[0003] However, in the technology described in Japanese Patent Application Publication No. 2015-128253, when an image is obtained by synthesizing multiple output signals, the image quality may degrade due to the offset and / or gain error between the output signals caused by the characteristic variations between the signal processing circuits, which include multiple amplifiers. As a measure to this, a configuration in which the same signal processing circuit processes signals sequentially with different amplification factors can be considered; however, this configuration cannot be said to be suitable for accelerating readout because it increases the readout time. Furthermore, the technology described in Japanese Patent Application Publication No. 2016-054424 has a configuration that can increase the speed of analog-to-digital conversion when the amplifier's output amplitude is small, but research from the viewpoint of S / N ratio and dynamic range is still insufficient. Summary of the Invention

[0004] The purpose of this invention is to provide an advantageous technique for improving the performance of photoelectric conversion devices.

[0005] According to embodiments of this disclosure, a photoelectric conversion device is provided, comprising: a pixel including a photoelectric conversion unit; an AD conversion unit configured to perform AD conversion on the analog signal by comparing the level of an analog signal generated in the pixel with the level of a reference signal whose level changes over time; and a control unit configured to control the AD conversion unit, wherein the control unit is configured to control the AD conversion unit to perform multiple AD conversions on the same analog signal generated in the pixel, wherein the length of a first AD conversion period in the multiple AD conversions is shorter than the length of a second AD conversion period in the multiple AD conversions, wherein the rate of change of the reference signal relative to time used in the second AD conversion period is less than the rate of change of the reference signal relative to time used in the first AD conversion period, wherein the potential change of the reference signal is a first level in the second AD conversion period, and wherein the potential change of the reference signal is the first level in the first AD conversion period.

[0006] According to another embodiment of this specification, a driving method for a photoelectric conversion device is provided. The photoelectric conversion device includes a pixel and an AD conversion unit. The pixel includes the photoelectric conversion unit, and the AD conversion unit is configured to perform AD conversion on the analog signal by comparing the level of an analog signal generated in the pixel with the level of a reference signal whose level changes over time. The driving method includes: performing multiple AD conversions on the same analog signal generated in the pixel for AD conversion periods of different lengths to obtain multiple digital signals corresponding to the multiple AD conversions; and generating an image signal by synthesizing the multiple digital signals. The length of a first AD conversion period in the multiple AD conversions is shorter than the length of a second AD conversion period in the multiple AD conversions. The rate of change of the reference signal relative to time used in the second AD conversion period is less than the rate of change of the reference signal relative to time used in the first AD conversion period. In the second AD conversion period, the potential change of the reference signal is a first level, and in the first AD conversion period, the potential change of the reference signal is the first level.

[0007] Other features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating an example configuration of a photoelectric conversion device according to a first embodiment of the present invention.

[0009] Figure 2 This is an equivalent circuit diagram illustrating an example of pixel configuration in a photoelectric conversion device according to a first embodiment of the present invention.

[0010] Figure 3 This is an equivalent circuit diagram illustrating an example configuration of the amplifier in a photoelectric conversion device according to a first embodiment of the present invention.

[0011] Figure 4 and Figure 5 This is a timing diagram illustrating the driving method of the photoelectric conversion device.

[0012] Figure 6 , Figure 7 and Figure 8 This is a diagram illustrating an example of digital signal processing in a digital signal processing unit.

[0013] Figure 9 This is a graph showing the relationship between incident light quantity, pixel output signal, and optical shot noise.

[0014] Figure 10 and Figure 14 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a first embodiment of the present invention.

[0015] Figure 11 , Figure 12 and Figure 13 This is a diagram illustrating an example of digital signal processing in a driving method for a photoelectric conversion device according to a first embodiment of the present invention.

[0016] Figure 15 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a second embodiment of the present invention.

[0017] Figure 16 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a third embodiment of the present invention.

[0018] Figure 17 and Figure 18 This is a diagram illustrating an example of digital signal processing in a driving method for a photoelectric conversion device according to a third embodiment of the present invention.

[0019] Figure 19 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a fourth embodiment of the present invention.

[0020] Figure 20 and Figure 21 This is a diagram illustrating an example of digital signal processing in a driving method for a photoelectric conversion device according to a fourth embodiment of the present invention.

[0021] Figure 22 This is a diagram illustrating the signal processing content in a photoelectric conversion device according to a fifth embodiment of the present invention.

[0022] Figure 23 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a fifth embodiment of the present invention.

[0023] Figure 24 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a sixth embodiment of the present invention.

[0024] Figure 25 This is a timing diagram illustrating a driving method for a photoelectric conversion device according to a sixth embodiment of the present invention.

[0025] Figure 26 This is a diagram illustrating the signal processing content in a photoelectric conversion device according to a sixth embodiment of the present invention.

[0026] Figure 27 This is a block diagram illustrating a schematic configuration of a camera system according to a seventh embodiment of the present invention.

[0027] Figure 28A This is a diagram illustrating a configuration example of a camera system according to an eighth embodiment of the present invention.

[0028] Figure 28B This is a diagram illustrating an example configuration of a mobile body according to an eighth embodiment of the present invention.

[0029] Figure 29 This is a block diagram illustrating a schematic configuration of a device according to a ninth embodiment of the present invention. Detailed Implementation

[0030] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] [First Embodiment]

[0032] Reference Figures 1 to 3 The structure of the photoelectric conversion device according to the first embodiment of the present invention is described. Figure 1 This is a schematic diagram illustrating an example configuration of the photoelectric conversion device according to this embodiment. Figure 2 This is an equivalent circuit diagram illustrating an example of pixel configuration in a photoelectric conversion device according to this embodiment. Figure 3 This is an equivalent circuit diagram showing an example configuration of the amplifier in the photoelectric conversion device according to this embodiment.

[0033] like Figure 1 As shown, the photoelectric conversion device 100 according to this embodiment includes a pixel unit 10, a pixel driving unit 20, an amplification unit 30, a comparison unit 40, a memory unit 50, a horizontal scanning unit 60, a digital signal processing unit 70, an output unit 80, and a timing generation unit 90. The photoelectric conversion device 100 also includes a reference signal generation unit 46 and a counter unit 54.

[0034] Pixel unit 10 includes a plurality of pixels 12 arranged in a matrix on multiple rows and columns. Each pixel 12 includes a photoelectric conversion unit and outputs a pixel signal corresponding to the amount of incident light, wherein the photoelectric conversion unit includes a photoelectric conversion element such as a photodiode. Each pixel 12 may include a color filter having predetermined spectral sensitivity characteristics. The number of rows and columns of the pixel array arranged in pixel unit 10 is not particularly limited. In addition to the effective pixels that output pixel signals corresponding to the amount of incident light, the pixel unit 10 may also include optical black pixels that block the photoelectric conversion units from light and dummy pixels that do not output signals.

[0035] In each row of pixel units 10, pixel driving signal lines 14 are arranged in a first direction ( Figure 1 The pixel driving signal lines 14 extend in the horizontal direction (as shown in the image). Each row of pixel driving signal lines 14 is connected to a pixel 12 arranged in the first direction and serves as a common signal line for these pixels 12. The first direction in which the pixel driving signal lines 14 extend can be referred to as the row direction or the horizontal direction. The pixel driving signal lines 14 are connected to the pixel driving unit 20.

[0036] In each column of pixel unit 10, pixel output lines 16 are arranged in a second direction intersecting the first direction. Figure 1 The pixel output lines 16 extend in the vertical direction. Each column of pixel output lines 16 is connected to pixels 12 arranged in the second direction and serves as a common signal line for these pixels 12. The second direction in which the pixel output lines 16 extend can be referred to as the column direction or the vertical direction. Current sources 18 are connected to each pixel output line 16. The pixel output lines 16 are connected to the amplification unit 30.

[0037] The pixel driving unit 20 is a control circuit unit that receives control signals supplied from the timing generation unit 90, generates control signals for driving the pixels 12, and supplies the control signals to the pixels 12 via the pixel driving signal lines 14. Logic circuitry such as shift registers or address decoders can be used in the pixel driving unit 20. The pixel driving unit 20 can be configured to sequentially supply control signals to the pixel driving signal lines 14 of each row, and sequentially drive the pixels 12 of the pixel unit 10 row by row. Signals read from the pixels 12 row by row are input to the amplification unit 30 via pixel output lines 16 provided in each column of the pixel unit 10.

[0038] The amplification unit 30 includes a plurality of amplifiers 32 arranged corresponding to each column of the pixel unit 10. Each amplifier in the amplifier 32 has an output node and an input node connected to a pixel output line 16 in the corresponding column. The output node of each amplifier in the plurality of amplifiers 32 is connected to an amplified signal output line 36 of a plurality of amplified signal output lines 36 arranged corresponding to each column of the pixel unit 10. The plurality of amplified signal output lines 36 are connected to the comparator unit 40.

[0039] The reference signal generation unit 46 is a circuit unit that receives a control signal supplied from the timing generation unit 90, generates a reference signal to be used for analog-to-digital conversion (AD conversion), and outputs the generated reference signal to the comparison unit 40 via the reference signal output line 48. The reference signal is a signal whose signal level changes with time, such as a ramp signal. A ramp signal is a signal whose signal level gradually changes (increases or decreases) from a predetermined value with a constant rate of change over time. In the following description, the rate of change of the reference signal (ramp signal) with respect to time can be expressed as the slope of the reference signal (ramp signal). The reference signal can be any signal with a predetermined amplitude suitable for AD conversion, and is not necessarily limited to a ramp signal.

[0040] The comparison unit 40 includes a plurality of buffer circuits 42 and a plurality of comparators 44 arranged corresponding to each column of the pixel unit 10. Each comparator 44 has a first input node connected to an amplified signal output line 36 of the corresponding column, a second input node connected to a reference signal output line 48 via the buffer circuit 42 of the corresponding column, and an output node. The output node of the comparator 44 is connected to the memory unit 50.

[0041] The counter unit 54 is a circuit unit that receives a control signal supplied from the timing generation unit 90, generates a counting signal whose count value changes at a constant frequency, and outputs the generated counting signal to the memory unit 50 via the counting signal line 56. The counting signal includes multiple bits, and the counting signal line 56 includes multiple signal lines corresponding to the number of bits of the counting signal.

[0042] Memory unit 50 includes a plurality of memories 52 arranged corresponding to each column of pixel unit 10. Each memory in the plurality of memories 52 is composed of multiple bits. Each memory in the plurality of memories 52 includes a first input node connected to the output node of comparator 44 of the corresponding column, a second input node connected to the counting signal line 56, a third input node connected to the horizontal scan unit 60, and an output node connected to the horizontal transmission line 58. The memory 52 is configured to hold a count value indicated by a count signal received at a timing from a latch signal output from comparator 44, wherein the magnitude relationship between the level of the output signal of indicator amplifier 32 and the level of a reference signal is reversed. The count value held in the memory 52 in this way becomes digital data of the pixel signal.

[0043] The horizontal scanning unit 60 is a control circuit unit that receives control signals supplied from the timing generation unit 90, generates control signals for reading digital data of pixel signals from the memory unit 50, and supplies control signals to the memory unit 50. Control lines of the horizontal scanning units 60, which are arranged corresponding to each column of the pixel units 10, are connected to the memory 52 of the corresponding column. Horizontal transmission lines 58 are connected to the digital signal processing unit 70.

[0044] The digital signal processing unit 70 has the function of performing digital signal processing on the digital data transferred from the memory unit 50, such as data addition / subtraction, digital gain processing, offset addition / subtraction, decoding, and data scrambling. The digital signal processing unit 70 is connected to the output unit 80.

[0045] The output unit 80 has the function of outputting the data processed by the digital signal processing unit 70 to the outside of the photoelectric conversion device 100. For example, the output unit 80 may include a system that outputs voltage from a single terminal, such as a buffer circuit, or a system that outputs LVDS (Low Voltage Differential Signal) with two differential terminals. The output unit 80 may have a parallel / serial conversion (P / S conversion) function.

[0046] The timing generation unit 90 is a circuit that supplies control signals for the operation and timing of the pixel driving unit 20, amplification unit 30, comparison unit 40, reference signal generation unit 46, memory unit 50, counter unit 54, horizontal scanning unit 60, and output unit 80. In other words, the timing generation unit 90 functions as a control unit for controlling the pixel driving unit 20, amplification unit 30, comparison unit 40, reference signal generation unit 46, memory unit 50, counter unit 54, horizontal scanning unit 60, and output unit 80. At least a portion of these control signals can be supplied from outside the photoelectric conversion device 100.

[0047] Next, we will refer to Figure 1 An overview describing the operation of the photoelectric conversion device 100 according to this embodiment.

[0048] Under the control of the timing generation unit 90, the pixel driving unit 20 drives the plurality of pixels 12 constituting the pixel unit 10 in rows (i.e., so-called vertical scanning) via control signals supplied through the pixel driving signal line 14. As a result, pixel signals of the plurality of pixels 12 are sequentially output to the pixel output lines 16 in rows. The pixel signals output from each pixel of the plurality of pixels 12 may include a signal (optical signal or photoelectric conversion signal) corresponding to the amount of incident light to the photoelectric conversion unit and a signal (reference signal or reset signal) corresponding to the amount of noise. The pixel signals output from the pixels 12 to the pixel output lines 16 are input to the amplification unit 30.

[0049] The pixel signal output from pixel 12 via pixel output line 16 is amplified by a predetermined amplification factor in the amplifier 32 of the corresponding column, and then input to the comparator 44 of the corresponding column. The comparator 44 compares the signal level of the pixel signal with the signal level of the reference signal input from the reference signal generation unit 46 via the buffer circuit 42, and outputs a latch signal at a timing point where the magnitude relationship between the signal level of the pixel signal and the signal level of the ramp signal is reversed. The counting signal supplied from the counter unit 54 and the output signal of the comparator 44 are input to the memory 52. ​​The memory 52 stores the count value indicated by the timing when the count signal receives the latch signal from the comparator 44 as digital data of the pixel signal. In this way, the pixel signal, which is an analog signal output from pixel 12, is converted into digital data (digital pixel signal). The comparator unit 40, the reference signal generation unit 46, the memory unit 50, and the counter unit 54 constitute an AD conversion unit for converting the pixel signal, which is an analog signal output from pixel 12, into a digital signal.

[0050] Under the control of the timing generation unit 90, the horizontal scanning unit 60 sequentially outputs the control signals of each column to the memory 52 of the memory unit 50. The memory 52, having received the control signals from the horizontal scanning unit 60, outputs the stored digital pixel signals to the horizontal transmission line 58.

[0051] The digital pixel signal output to the horizontal transmission line 58 undergoes predetermined digital signal processing in the digital signal processing unit 70, and is then output to the outside of the photoelectric conversion device 100 via the output unit 80.

[0052] Next, we will refer to Figure 2 An example of the configuration of pixel 12 in the photoelectric conversion device 100 according to this embodiment is described.

[0053] like Figure 2 As shown, for example, each pixel in pixel 12 may include a photoelectric conversion element PD, a transmission transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. Each pixel 12 may include a microlens and a color filter arranged in the optical path until the incident light is guided to the photoelectric conversion element PD. The microlens has the function of focusing the incident light onto the photoelectric conversion element PD. The color filter selectively transmits light of a predetermined color.

[0054] The photoelectric conversion element PD is, for example, a photodiode, whose anode is connected to the reference voltage line GND and whose cathode is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node connecting the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 is called a floating diffusion FD. The floating diffusion FD includes a capacitor assembly (floating diffusion capacitor) and serves as a charge holding part. The floating diffusion capacitor may include pn junction capacitance and interconnect capacitance. The drains of the reset transistor M2 and the amplification transistor M3 are connected to the power supply voltage line VDD (voltage VDD). The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the pixel output line 16.

[0055] exist Figure 2 In the case of a pixel configuration, the pixel driving signal lines 14 of each row include signal lines connected to the gate of the transfer transistor M1, signal lines connected to the gate of the reset transistor M2, and signal lines connected to the gate of the select transistor M4. The control signal PTX is supplied from the pixel driving unit 20 to the gate of the transfer transistor M1 via the signal lines. The control signal PRES is supplied from the pixel driving unit 20 to the gate of the reset transistor M2 via the signal lines. The control signal PSEL is supplied from the pixel driving unit 20 to the gate of the select transistor M4 via the signal lines. When each transistor is formed by an n-channel MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the pixel driving unit 20. The corresponding transistor is turned off when a low-level control signal is supplied from the pixel driving unit 20.

[0056] In this embodiment, a description is given assuming that electrons in the electron-hole pairs generated in the photoelectric conversion element PD by incident light are used as signal charges. When electrons are used as signal charges, the individual transistors included in pixel 12 can be formed by n-channel MOS transistors. However, signal charges are not limited to electrons, and holes can also be used as signal charges. When holes are used as signal charges, the conductivity type of the individual transistors is opposite to the conductivity type described in this embodiment. Furthermore, the terms "source" or "drain" for MOS transistors can vary depending on the conductivity type or target function of the transistor. Some or all of the names for source and drain used in this embodiment are sometimes referred to as opposite names.

[0057] The photoelectric conversion element PD converts incident light (photoelectric conversion) into a charge corresponding to the amount of incident light and accumulates the generated charge. When the transfer transistor M1 is turned on, the charge held in the photoelectric conversion element PD is transferred to the floating diffuser FD. The charge transferred from the photoelectric conversion element PD is held in the capacitor component (floating diffuser capacitor) of the floating diffuser FD. As a result, the floating diffuser FD becomes a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD by utilizing the charge-voltage conversion of the floating diffuser capacitor.

[0058] When the select transistor M4 is turned on, the source of the amplifying transistor M3 is connected to the pixel output line 16. The amplifying transistor M3 is configured such that a voltage VDD is supplied to its drain and a bias current is supplied from the current source 18 to its source via the select transistor M4, thus forming an amplifier unit (source follower circuit) with its gate as the input node. Therefore, the amplifying transistor M3 outputs a signal based on the potential of the floating diffusion FD to the pixel output line 16 via the select transistor M4. In this sense, the amplifying transistor M3 and the select transistor M4 form an output unit for outputting a pixel signal corresponding to the amount of charge held in the floating diffusion FD.

[0059] The reset transistor M2 has the function of controlling the supply of voltage (VDD) to the floating diffuser FD to reset the floating diffuser FD, which is a charge holding part. When the reset transistor M2 is turned on, the floating diffuser FD is reset to the potential corresponding to the voltage VDD.

[0060] Next, we will refer to Figure 3 An example of the configuration of amplifier 32 in the photoelectric conversion device 100 according to this embodiment is described.

[0061] like Figure 3As shown, for example, each amplifier in amplifier 32 may include amplifier circuit 34, input capacitor C0, feedback capacitors C1, C2 and C3, and switches S0, S1, S2 and S3. Amplifier circuit 34 may be, for example, a differential amplifier circuit. The input node of amplifier circuit 34 is connected to pixel output line 16 via input capacitor C0. The output node of amplifier circuit 34 is connected to amplified signal output line 36. Switch S0, the series connection of feedback capacitor C1 and switch S1, the series connection of feedback capacitor C2 and switch S2, and the series connection of feedback capacitor C3 and switch S3 are connected in parallel between the input node and the output node of amplifier circuit 34.

[0062] When amplifier circuit 34 is an inverting amplifier circuit, the voltage amplification factor of amplifier 32 is expressed as -(input capacitor (C0) / feedback capacitors (C1 to C3)). The voltage amplification factor of amplifier 32 can be switched by changing which of the feedback capacitors C1 to C3 is selected by switches S1 to S3 to change the feedback coefficient determined by the voltage division ratio between the feedback capacitors C1 to C3 and the input capacitor C0. That is, amplifier 32 is an amplifier configured to change its voltage amplification factor. Control signals for switches S0, S1, S2, and S3 are supplied from timing generation unit 90.

[0063] Next, we will refer to Figure 4 A standard driving example of the photoelectric conversion device according to this embodiment is described. Figure 4 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 4 The diagram illustrates the time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX, and PSEL, control signals of switches S0, S1, S2, and S3, the output signal of amplifier 32, the ramp signal, the output signal of comparator 44, and the counting signal. It is assumed that switches S0, S1, S2, and S3 are on when the corresponding control signal is high, and off when the corresponding control signal is low.

[0064] Before the readout operation, the photoelectric conversion element PD is exposed during a set time period (exposure period). In the photoelectric conversion element PD, a charge corresponding to the amount of incident light during the exposure period accumulates. During this period, the control signal PRES is high, the reset transistor M2 is turned on, and the gate and floating diffuser FD of the amplification transistor M3 are in a reset state. Furthermore, switches S0 to S3 are on, the amplifier circuit 34 is in voltage follower mode, and the amplified signal output line 36 is at potential V0. At this time, both terminals of each of the feedback capacitors C1 to C3 are short-circuited, and these terminals are also at potential V0.

[0065] First, by switching the control signals of switches S2 and S3 from high level to low level to disconnect switches S2 and S3, the feedback capacitors C2 and C3 are disconnected from the feedback path of amplifier circuit 34.

[0066] Next, the reset state of amplifier circuit 34 is released by switching the control signal of switch S0 from high to low to disconnect switch S0. The reset state of the gate of amplifier transistor M3 and floating diffusion FD is released by switching the control signal PRES from high to low to turn off reset transistor M2. The floating diffusion FD maintains a potential corresponding to the release of the reset state. At this time, the control signal PSEL is high and selection transistor M4 is turned on, and a signal with a potential corresponding to the reset potential of floating diffusion FD is output to pixel output line 16 through the source follower circuit configured by amplifier transistor M3 and current source 18.

[0067] Next, by switching the control signal PTX to a high level for a predetermined time period to turn on the transfer transistor M1, the charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion FD. Here, when the absolute value of the amount of charge transferred to the floating diffusion FD is represented by Q and the capacitance of the floating diffusion FD is represented by CFD, the gate potential of the amplification transistor M3 connected to the floating diffusion FD decreases by Q / CFD. The potential of the pixel output line 16 also changes in response to the change in the gate potential of the amplification transistor M3. When the gain of the source follower circuit is represented by Gsf, the potential change (amplitude) ΔV1 of the pixel output line 16 due to the transfer of charge from the photoelectric conversion element PD to the floating diffusion FD is represented by the following expression (1).

[0068] ΔV1=-Q×Gsf / CFD…(1)

[0069] The potential change ΔV1 is amplified by amplifier 32, which includes amplifier circuit 34, input capacitor C0, and feedback capacitor C1. The potential change (amplitude) ΔV2 of the output potential of amplifier 32 is represented by the following expression (2). The output potential V2 of amplifier 32 is represented by the following expression (3). The voltage amplification factor C0 / C1 set in amplifier 32 is called Gain1.

[0070] ΔV2=Q×(Gsf / CFD)×(C0 / C1)…(2)

[0071] V2=V0+Q×(Gsf / CFD)×(C0 / C1)…(3)

[0072] In the following description, the period from the transition of the control signal PRES and the control signal S0 from high to low to the transition of the control signal PTX to high is called the pixel noise level readout period. The period after the control signal PTX becomes high is called the pixel signal level readout period. The period during which the comparison unit 40 compares the pixel signal with the reference signal is called the comparison period or AD conversion period. The AD conversion period during the pixel noise level readout period is called the NAD period TN1. The AD conversion period during the pixel signal level readout period is called the SAD period TS1. The period from the beginning of the NAD period to the end of the SAD period is called the AD conversion period T1 of one pixel.

[0073] Comparator 44 performs a comparison operation, comparing the potential level of the output signal of amplifier 32 with the potential level of a reference signal. When the magnitude relationship between the potential level of the output signal of amplifier 32 and the potential level of the reference signal is reversed, comparator 44 outputs a pulse signal (latch signal) indicating the comparison result.

[0074] Counter unit 54 begins counting the clock signal (clock pulse) in response to a change in the potential level of the reference signal initiated by reference signal generation unit 46. The start of the change in the potential level of the reference signal and the start of counting by counter unit 54 do not necessarily coincide perfectly. For example, counting by counter unit 54 may begin after a predetermined time period has elapsed since the change in the potential level of the reference signal. When a latch signal is received from comparator 44 during NAD period TN1, memory 52 holds the count value a indicated by the count signal supplied from count signal line 56 at that time. Similarly, when a latch signal is received from comparator 44 during SAD period TS1, memory 52 holds the count value b indicated by the count signal supplied from count signal line 56 at that time. The count values ​​a and b held in memory 52 in this manner are the AD conversion values ​​(digital data) of the pixel signal. It is assumed that memory 52 has multiple memories corresponding to pixel noise level readout and pixel signal level readout.

[0075] The count value held in memory 52 is transmitted to digital signal processing unit 70 in response to a control signal from horizontal scanning unit 60, and output to the outside via output unit 80 after digital signal processing in digital signal processing unit 70. An example of digital signal processing in digital signal processing unit 70 is the subtraction of AD conversion value a from AD conversion value b. By performing the subtraction, reset noise of pixel 12, offset differences generated in the plurality of amplifiers 32 and the plurality of comparators 44 including pixel 12, and fixed-pattern noise can be removed, thereby improving image quality.

[0076] Next, we will refer to Figure 5 Another example of driving a photoelectric conversion device according to this embodiment is described. Figure 5 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 5 The diagram illustrates the time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX, and PSEL, control signals of switches S0, S1, S2, and S3, the output signal of amplifier 32, the ramp signal, the output signal of comparator 44, and the counting signal. It is assumed that switches S0, S1, S2, and S3 are on when the corresponding control signal is high, and off when the corresponding control signal is low.

[0077] Figure 5 The driver example is a standard driver example used to extend dynamic range. That is to say, Figure 5 The driving example can be applied to situations where an image with expanded dynamic range is generated by using signals obtained by amplification with different voltage amplification factors. Specifically, the pixel signal is amplified by two amplification factors (i.e., voltage amplification factor Gain1 and voltage amplification factor Gain2), and each amplified pixel signal in the amplified pixel signal undergoes AD conversion.

[0078] First, with Figure 4 The driving example follows the same procedure, performing processing up to the SAD period TS1 to obtain the AD conversion values ​​a and b. The voltage amplification factor at this point is Gain1.

[0079] Next, the control signals of switches S2 and S3 change from low level to high level, and switches S2 and S3 are turned on. As a result, the feedback capacitor of amplifier circuit 34 becomes (C1+C2+C3), and the voltage amplification factor of amplifier 32 becomes C0 / (C1+C2+C3). The voltage amplification factor at this time is Gain2. The output potential V3 of amplifier 32 at this time is represented by the following expression (4).

[0080] V3=V0+Q×(Gsf / CFD)×(C0 / (C1+C2+C3))…(4)

[0081] Similar to the SAD period TS1, the comparator unit 40 and the memory unit 50 perform AD conversion on the pixel signal amplified by the voltage amplification factor Gain2, and store the acquired AD conversion value in the memory 52. ​​This period is called the SAD period TS2. It is assumed that the numerical value c is held in the memory 52 as the AD conversion value.

[0082] Next, the control signal PRES is switched to a high level for a predetermined time period to turn on the reset transistor M2, thereby resetting the floating diffuser FD. Furthermore, the control signal for switch S0 is switched to a high level for a predetermined time period to turn on switch S0, thereby resetting amplifier 32. As a result, a pixel signal at the pixel noise level is output to pixel output line 16, and a signal obtained by amplifying the pixel signal with a voltage amplification factor Gain2 is output to amplified signal output line 36.

[0083] Similar to NAD period TN1, comparator unit 40 and memory unit 50 perform AD conversion on the pixel signal with pixel noise level amplified by voltage amplification factor Gain2, and store the acquired AD conversion value in memory 52. ​​This period is called NAD period TN2. It is assumed that the numerical value d is stored in memory 52 as the AD conversion value.

[0084] Note that the AD conversion value obtained during NAD period TN2 includes noise when reset transistor M2 and switch S0 are turned off, but this noise may differ from the noise included in the AD conversion value obtained during NAD period TN1. The data obtained during NAD period TN2 can be effectively used to remove offset or fixed-mode noise during digital signal processing in digital signal processing unit 70.

[0085] Furthermore, in this driving example, each memory in memory 52 may have multiple memories corresponding to NAD periods TN1 and TN2 and SAD periods TS1 and TS2. Alternatively, the AD conversion values ​​held in AD conversion periods TN1 and TS1 can be transferred to other memories and held in other memories, and a portion of the memory after the AD conversion values ​​are transferred can be used as memory for holding AD conversion values ​​in AD conversion periods TN2 and TS2. The data held in other memories during AD conversion periods TN1 and TS1 can be horizontally transferred during AD conversion periods TN2 and TS2.

[0086] In this driving example, the time period from the beginning of NAD time period TN1 to the end of NAD time period TN2 is referred to as the AD conversion time period T2 of one pixel. In this driving example, the order of AD conversion is AD conversion time periods TN1, TS1, TS2, and TN2, but the configuration of amplifier 32 can be changed to AD conversion time periods TN1, TN2, TS2, and TS1 or AD conversion time periods TN1, TN2, TS1, and TS2. In this embodiment, the AD conversion time period is the time period from the start of the potential change of the reference signal to the end of the potential change. On the other hand, the AD conversion time period is the time period from the start of the counting operation of the counting unit 54 to the end of the counting operation. In the figure, the start of the potential change of the reference signal and the start of the counting operation of the counter unit 54 are performed simultaneously. Therefore, the time period from the start of the potential change of the reference signal to the end of the potential change coincides with the time period from the start of the counting operation of the counting unit 54 to the end of the counting operation. However, the present invention is not limited to this example, and as described above, the start to the end of the potential change of the reference signal or the start to the end of the counting operation of the counter unit 54 can be used as the AD conversion time period. Although an analog-to-digital (ADC) conversion using a reference signal has been described as an example in this embodiment, the invention is not limited to this example. For example, in the case of successive approximation ADC conversion, the ADC conversion period can be the period from the beginning to the end of the potential change of the reference signal compared to the analog signal.

[0087] The count values ​​a, b, c, and d held in memory 52 are transmitted to digital signal processing unit 70 in response to control signals from horizontal scanning unit 60, and are output to the outside via output unit 80 after digital signal processing by digital signal processing unit 70.

[0088] Figures 6 to 8 It is used to explain the situation in Figure 5 The diagram shows an example of digital signal processing using the AD conversion values ​​obtained from the driving example shown.

[0089] Figure 6 The result after subtraction processing in the digital signal processing unit 70 is shown. Figure 6In the diagram, the horizontal axis represents the signal amplitude (potential change ΔV1) of pixel output line 16, and the vertical axis represents the result of subtracting the AD conversion value obtained in the NAD period from the AD conversion value obtained in the SAD period. Here, it is assumed that the maximum value of the potential change ΔV1 of pixel output line 16 based on expression (1) is 1.0V, and the maximum value of the difference between the AD conversion values ​​obtained in AD conversion periods TN1 and TS1 (hereinafter referred to as the AD conversion result) is 4096 LSB. That is, the resolution of the AD conversion is set to 12 bits. It is also assumed that the voltage amplification factor Gain1 is C0 / C1 = 2, and the voltage amplification factor Gain2 is C0 / (C1+C2+C3) = 1.

[0090] The slope of the reference signal and the frequency of the counter are set such that when the voltage amplification factor is Gain2 (=1), the potential change ΔV1 of pixel output line 16 is 1.0V, and the potential change ΔV2 of amplifier 32 is 1.0V, the AD conversion result (cd) becomes 4096 LSB. This is in Figure 6 This is shown in dashed lines. On the other hand, when the voltage amplification factor is Gain1 (=2) and the potential change ΔV1 of the pixel output line 16 is 0.5V, the potential change ΔV2 of the amplifier 32 is 1.0V, and the AD conversion result (ba) is 4096 LSB. This is in Figure 6 It is shown in solid line.

[0091] Figure 6 The diagram illustrates how the change in the AD conversion result relative to the potential change of pixel output line 16 varies depending on the voltage amplification factor of amplifier 32. Specifically, when the voltage amplification factor is Gain1 (=2), the change in the AD conversion result is twice the change in the AD conversion result when the voltage amplification factor is Gain2 (=1).

[0092] Figure 7 This graph shows the result when a digital gain (=(cd)×2) twice the value of the AD conversion result (cd) is applied. When the voltage amplification factor is Gain2 (=1) and the potential change ΔV1 of the pixel output line 16 is 0.5V, the value obtained by multiplying the AD conversion result (cd) by the digital gain (=(cd)×2) is 4096 LSB. That is, the change in the AD conversion result relative to the potential change ΔV1 of the pixel output line 16 at this time is the same as the change in the AD conversion result (ba) relative to the potential change ΔV1 of the pixel output line 16 when the voltage amplification factor is Gain1. At this time, the maximum value of the AD conversion is 8192 LSB.

[0093] Figure 8This diagram illustrates a method for synthesizing an image using the results of AD conversion (ba) and AD conversion (cd). For example... Figure 8 As shown, the AD conversion result (ba) of the pixel signal amplified by the voltage amplification factor Gain1 is used as image data in the range where the potential change ΔV1 of the pixel output line 16 is equal to or greater than 0V and less than 0.5V (low brightness region). In the range where the potential change ΔV1 of the pixel output line 16 is 0.5V or greater (high brightness region), the AD conversion result (cd) × 2 of the pixel signal amplified by the voltage amplification factor Gain2 is used as image data.

[0094] Since the voltage amplification factor Gain1 is higher than the voltage amplification factor Gain2, the AD conversion result (ba) is more advantageous than the AD conversion result (cd) in terms of noise at the output stage of amplifier 32. On the other hand, since the AD conversion result (cd) becomes 4096 LSB when the potential change ΔV1 of the pixel output line 16 is 1.0V (the potential change ΔV1 becomes maximum), the AD conversion result (cd) is more advantageous than the AD conversion result (ba) in terms of input dynamic range. Therefore, as... Figure 8 The synthesized image shown becomes an image with an increased dynamic range while improving the S / N ratio.

[0095] On the other hand, since NAD time periods TN1 and TN2, as well as SAD time periods TS1 and TS2, require the same processing time, the processing time of the AD conversion time period T2 for one pixel is a reference. Figure 4 The processing time for the AD conversion period T1 of a single pixel is twice that of the described pixel. Therefore, in Figure 5 In the driver example, the read time is long and the frame rate is reduced.

[0096] As another method for obtaining an image with expanded dynamic range by using two AD conversion results obtained with different voltage amplification factors, it can be considered that two or more signal processing circuits are provided at the stage following amplifier 32, and the same pixel signal is processed simultaneously in these signal processing circuits. According to this configuration example, although the readout time can be shortened, the image quality may be degraded due to offsets caused by errors in the two or more signal processing circuits (e.g., errors in the voltage amplification factor of amplifier 32 or errors in the operating point). Furthermore, the circuit size increases, which may be disadvantageous from the viewpoint of chip size and the allowable current of the power supply.

[0097] Figure 9 This is for illustrative reference. Figures 6 to 8 A graph depicting the S / N ratio of pixel signals in digital signal processing. Figure 9In the diagram, the horizontal axis represents the amount of incident light to pixel 12, and the vertical axis, on a logarithmic scale, represents the signal level (pixel output signal) and optical shot noise resulting from the photoelectric conversion based on the incident light. Figure 9 In the diagram, solid lines indicate the relationship between incident light intensity and pixel output signal. Dashed lines indicate the relationship between incident light intensity and optical shot noise. Dotted lines indicate pixel noise (this includes noise caused by amplifier 32, but excludes noise due to AD conversion).

[0098] Assuming pixel noise is 0.2mV, the S / N ratio between a signal level represented as 1.0V and pixel-based noise of 0.2mV is 74dB. Considering quantization bit errors, an A / D conversion resolution higher than 12 bits is required to cover this S / N ratio when performing A / D conversion on the pixel signal.

[0099] Next, the relationship between pixel signal and optical shot noise will be described. Here, it is assumed that the number of photocharges N at a signal level of 1.0V is 10,000. The amount of optical shot noise is typically expressed as... (The square root of N). When the large amplitude signal level of the pixel signal is 1.0V, for 10,000 photocharges, the number of optical shot noise is 100, and the S / N ratio is 40dB. When the small amplitude signal level is 10mV, the S / N ratio is 20dB. In other words, it can be understood that the resolution used to ensure an S / N ratio of over 40dB is sufficient at any point in the signal level.

[0100] exist Figure 9 In this context, the resolution in 8-bit to 12-bit AD conversion is indicated by a one-dot-chain line. For example... Figure 9 As shown, depending on the amount of light, the resolution of the AD conversion can be set low while taking into account optical shot noise and quantization error. (Referencing...) Figures 6 to 8 In the described digital signal processing, by applying twice the digital gain to the AD conversion value of the pixel signal amplified by a voltage amplification factor Gain2 (=1), the resolution is halved, equivalent to 11 bits. See reference... Figure 9 As stated above, when the potential change ΔV1 of the pixel output line 16 is 0.5V or greater, there is no impact on image quality even if the resolution becomes 11 bits.

[0101] Figure 10 It is shown that... Figure 5 The timing diagram of the driving method in the case of increased read speed is shown in the example driver. Figure 10The time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, output signal of amplifier 32, ramp signal, output signal of comparator 44 and count signal are shown.

[0102] In this driving example, during the SAD period TS3 and NAD period TN3, the rate of change of the reference signal generated by the reference signal generation unit 46 with respect to time is doubled. Therefore, it is possible to... Figure 5 The maximum value (1.0V) of the potential change ΔV1 of pixel output line 16 is compared during half of the SAD period TS2.

[0103] exist Figure 10 In this context, the period when the SAD period TS2 is shortened to half is defined as the SAD period TS3, and the period when the NAD period TN2 is shortened to half is defined as the NAD period TN3. By shortening the SAD period TS3 and the NAD period TN3 in this way, the AD conversion period T3 of one pixel can be shortened to [a shorter timeframe]. Figure 5 The AD conversion time T2 of one pixel is 3 / 4. Figure 10 In the driving example, the count value e is held in memory 52 during the SAD period TS3, and the count value f is held in memory 52 during the NAD period TN3.

[0104] Figures 11 to 13 It is used to explain the situation in Figure 10 The diagram shows an example of digital signal processing using the AD conversion values ​​obtained from the driving example shown.

[0105] Figure 11 The result after the subtraction process in the digital signal processing unit 70 is shown. Figure 11 In the diagram, the horizontal axis represents the signal amplitude (potential change ΔV1) of pixel output line 16, and the vertical axis represents the result of subtracting the AD conversion value obtained in the NAD period from the AD conversion value obtained in the SAD period. Here, as... Figure 6 Assuming the voltage amplification factor Gain1 is C0 / C1 = 2 and the voltage amplification factor Gain2 is C0 / (C1+C2+C3) = 1.

[0106] exist Figure 11In the diagram, the solid line indicates the signal corresponding to the voltage amplification factor Gain1, and when the potential change ΔV1 of the pixel output line 16 is 0.5V, the potential change ΔV2 of the amplifier 32 is 1.0V, and the AD conversion result (ba) is 4096 LSB. The dashed line indicates the signal corresponding to the voltage amplification factor Gain2. As mentioned above, when the voltage amplification factor of the amplifier 32 is Gain2 (=1), since the reference signal changes by twice the amount of time, the time required for AD conversion is 1 / 2. That is, when the potential change ΔV1 of the pixel output line 16 is 1.0V, the AD conversion result (ef) becomes 2048 LSB. In other words, the change in the AD conversion result when the voltage amplification factor is Gain1 (=2) is four times the change in the AD conversion result when the voltage amplification factor is Gain2 (=1).

[0107] Figure 12 This graph shows the result when a digital gain (=(ef)×4) four times the AD conversion result (ef) is applied. When the voltage amplification factor is Gain2 (=1) and the potential change ΔV1 of pixel output line 16 is 0.5V, the value obtained by multiplying the AD conversion result (ef) by 4 times the digital gain (=(ef)×4) is 4096 LSB. That is, the change in the AD conversion result relative to the potential change ΔV1 of pixel output line 16 at this time is the same as the change in the AD conversion result (ba) relative to the potential change ΔV1 of pixel output line 16 when the voltage amplification factor is Gain1. At this time, the maximum value of the AD conversion is 8192 LSB.

[0108] Figure 13 This diagram illustrates a method for synthesizing an image using the results of AD conversion (ba) and AD conversion (ef). For example... Figure 13 As shown, in the range where the potential change ΔV1 of the pixel output line 16 is equal to or greater than 0V and less than 0.5V (low brightness region), the AD conversion result (ba) with the voltage amplification factor of Gain1 will be used as image data. In the range where the potential change ΔV1 of the pixel output line 16 is 0.5V or greater (high brightness region), the AD conversion result (ef) × 4 with the voltage amplification factor of Gain2 will be used as image data.

[0109] exist Figure 10 In the driving example, during the comparison operation in the SAD period TS3 and NAD period TN3, the resolution becomes 1 / 2 because the change in the level of the reference signal relative to time is set to twice. Furthermore, by setting the digital gain to four times, the resolution becomes 1 / 4. Therefore, although... Figure 13The resolution in the high-brightness areas becomes 1 / 8, but as referenced... Figure 9 Even when the resolution is reduced to 1 / 8, the image quality remains unaffected because optical shot noise is high in high-brightness areas where the potential change on the pixel output line 16 is 0.5V or greater. In other words, in Figure 10 In the driving example, an image with expanded dynamic range can also be obtained while improving the S / N ratio. Furthermore, since the lengths of the SAD period TS3 (with a voltage amplification factor of Gain2 = 1) and the NAD period TN3 can be reduced to half, the readout time becomes significantly shorter than... Figure 5 The readout time in the driver example is short, and it can suppress the reduction of frame rate.

[0110] exist Figure 10 In the driving example, although from the viewpoint of obtaining an image with expanded dynamic range, signals amplified by voltage amplification factor Gain1 and signals amplified by voltage amplification factor Gain2 are obtained for the same pixel signal, multiple signals amplified by the same voltage amplification factor can be obtained.

[0111] Figure 14 It is shown in relation to Figure 5 The timing diagram of the driving example compared to another driving method with increased read speed. Figure 14 The diagram illustrates the time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX, and PSEL, control signals for switches S0, S1, S2, and S3, the output signal of amplifier 32, the ramp signal, the output signal of comparator 44, and the counting signal. In this driving example, [details omitted]. Figure 10 The NAD period TN3 in the driving example.

[0112] Subtract the AD conversion value e obtained during the SAD period TS3 from the value obtained during the SAD period TS3. Figure 10 In the driving example, the AD conversion value f is obtained during the NAD period TN3, and this AD conversion value f is used to subtract offset and fixed-mode noise. On the other hand, in this driving example, since the NAD period TN3 is omitted, the AD conversion value f is not obtained. Here, apart from some noise components, in Figure 10 The AD conversion value f obtained in the NAD period TN3 is approximated as Gain2 / Gain1 relative to the AD conversion value a obtained in the NAD period TN1.

[0113] For reference Figure 13Specifically, within a range where the potential change of the pixel output line 16 is 0.5V or greater, the data of the AD conversion value (ef) × 4 at a voltage amplification factor of Gain2 is used as the image. Within this range, the level of optical shot noise is high, and even if the AD conversion value a × Gain2 / Gain1 is used instead of... Figure 10 The image quality will not be affected by the AD conversion value f obtained during the NAD period TN3. Therefore, in Figure 14 In the driving example, the digital signal processing unit 70 calculates the AD conversion value a × Gain2 / Gain1 and performs the process of subtracting the AD conversion value a × Gain2 / Gain1 from the AD conversion value e. Figure 14 In the driver example, with Figure 10 Compared to the AD conversion time T3 for one pixel in the driving example, the AD conversion time T4 for one pixel can be further shortened.

[0114] For reference Figure 8 and Figure 13 As stated above, when using AD conversion results with different voltage amplification factors as boundaries based on a specific brightness (the amount of potential change in pixel output line 16), errors in the voltage amplification factor may occur even within the same signal processing path. This is due to offsets at the boundary between low-brightness and high-brightness regions, or linearity errors between low-brightness and high-brightness regions, and may affect image quality. In this case, the image can be corrected by obtaining AD conversion values ​​with different voltage amplification factors within a range where the potential change in pixel output line 16 is less than 0.5V, and by processing these signals to calculate correction values ​​for offset and linearity.

[0115] For example, the offset can be calculated by subtracting AD conversion values ​​obtained with different voltage amplification factors, and then a correction process can be performed. Alternatively, image data can be obtained by averaging AD conversion values ​​obtained with different voltage amplification factors. Furthermore, in a photoelectric conversion device configured to process signals generated by multiple photoelectric conversion elements to detect phase difference, AD conversion values ​​obtained with different voltage amplification factors within a range where the potential change at the pixel output line 16 is less than 0.5V can be used. For example, a suitable processing result (phase difference detection signal) can be obtained by selecting and processing any one of the AD conversion values ​​obtained with different voltage amplification factors or by averaging them for the signals generated by the multiple photoelectric conversion elements.

[0116] Furthermore, as in the driving example of this embodiment, when selecting an AD conversion result based on the level of the pixel signal in a plurality of AD conversion results and using it as an image signal, the amount of data horizontally transmitted from the memory unit 50 or the amount of signal processing data from the digital signal processing unit 70 can be adjusted.

[0117] For example, data smaller than 2048 LSBs should not be used as... Figure 5 The AD conversion result (cd) is obtained in the SAD period TS2 and NAD period TN2 in the driving example. Therefore, depending on the required resolution, several bits on the lower side may not be transferred horizontally from the memory cell 50. Alternatively, several bits on the lower side may be invalidated during signal processing in the digital signal processing unit 70.

[0118] On the other hand, for in Figure 10 In the driving example, the AD conversion results (ef) obtained in the SAD period TS3 and NAD period TN3 do not use 2048 LSB or larger of data, so the most significant bit does not need to be horizontally transferred from memory cell 50. Alternatively, it can be invalid during signal processing in digital signal processing unit 70. In the driving example of this embodiment, power consumption can be reduced by decreasing the amount of data horizontally transferred and processed according to the resolution and the required range of AD conversion values.

[0119] In addition, as referenced Figure 7 and Figure 12 As stated above, when digital gain processing is performed by the digital signal processing unit 70, the bit width of the AD conversion value increases. In this case, the decrease in readout speed can be suppressed by increasing the operating frequency of the output unit 80. Alternatively, the digital signal processing unit 70 can be configured to compress data after various signal processing steps and output it to the output unit 80.

[0120] The voltage amplification factor settings, voltage amplification factor ratios, AD conversion operation resolution, pixel charge-to-voltage conversion ratio, optical shot noise, and pixel noise values ​​described in this embodiment are examples and can be referenced. Figure 9 The concept of the S / N ratio described is appropriately modified.

[0121] As described above, in this embodiment, in the configuration of performing AD conversion processing on pixel signals amplified with multiple different voltage amplification factors, the AD conversion period of pixel signals amplified with some voltage amplification factors is shortened. Therefore, according to this embodiment, an image with a high signal-to-noise ratio and expanded dynamic range can be obtained while suppressing the reduction in frame rate.

[0122] [Second Embodiment]

[0123] Reference Figure 15 A driving method for a photoelectric conversion device according to a second embodiment of the present invention is described. Components similar to those in the photoelectric conversion device according to the first embodiment are indicated by the same reference numerals, and their description will be omitted or simplified.

[0124] In this embodiment, another driving method for the photoelectric conversion device described in the first embodiment will be described. Figure 15 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 15 The time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, output signal of amplifier 32, ramp signal, output signal of comparator 44 and count signal are shown.

[0125] In the driving method of this embodiment, the frequency of the counting signal generated by the counter unit 54 during the AD conversion period for the pixel signal amplified by the voltage amplification factor Gain2 is set to be higher than that of the counter unit 54. Figure 10 The frequency is shown in the case of the driving method of the photoelectric conversion device according to the first embodiment. Specifically, in this embodiment, the frequency of the counting signal in the SAD period TS2 and the NAD period TN2 is set to... Figure 10 The frequency is twice that of the drive example in this case. In this specification, the frequency of the counter and the frequency of the counting signal are the frequencies at which the count value indicated by the counting signal changes.

[0126] In the driving method of this embodiment, such as Figure 10 As in the driving method shown, the change in the reference signal relative to time during SAD period TS2 and NAD period TN2 is set to twice the change in the reference signal relative to time during NAD period TN1 and SAD period TS1. When the change in the reference signal relative to time is set to twice, the AD conversion period can be shortened, but the resolution of the AD conversion is reduced to half. However, since the counter frequency is set to twice in this embodiment, even when the change in the reference signal relative to time is set to twice, the potential change of the pixel output line 16 can still be obtained. Figure 5 The driving example shows the same AD conversion result.

[0127] Examples of configurations for counter unit 54 include a PLL (Phase Locked Loop) circuit and a counter circuit driven by a clock output from the PLL circuit. In this configuration, the frequency of the counter can be changed by switching the multiplier of the output clock of the PLL circuit. Alternatively, the clock input to the counter circuit can be switched by providing multiple PLL circuits with different frequencies to be generated. With this configuration, it is not necessary to ensure the settling time associated with the switching of the multiplier, and the processing time can be reduced.

[0128] In this embodiment, a configuration is used where the count value g is acquired and stored in memory 52 during the SAD period TS2, and the count value h is acquired and stored in memory 52 during the NAD period TN2. If there is no noise, the count values ​​g and h acquired in this way are equivalent to those acquired during the NAD period TN2. Figure 5 The count values ​​c and d obtained in the driving example.

[0129] exist Figure 10 In the driving example, the resolution of the AD conversion result in the high-brightness region decreases as the amount of change of the reference signal relative to time increases. For example, assume a large ratio of voltage amplification factors such as Gain1 (=4) to Gain2 (=1). In this case, the range for using the AD conversion value of the pixel signal amplified by voltage amplification factor Gain2 as the image is a range where the potential change of pixel output line 16 is 0.25V or greater, and it is shifted towards the low-brightness side. That is, due to the reference... Figure 9 The described optical shot noise is shifted to small areas, making it necessary to suppress the reduction in resolution during AD conversion. On the other hand, when the counting signal becomes high-frequency, for example, the effects of power supply noise or clock jitter during comparison operations can affect image quality. Therefore, it is desirable to set the frequency of the counting signal lower in low-brightness areas with low optical shot noise and increase the frequency of the counting signal in high-brightness areas with high optical shot noise.

[0130] As described above, according to this embodiment, an image with a high S / N ratio and expanded dynamic range can be obtained while suppressing the reduction in resolution and frame rate during AD conversion.

[0131] [Third Embodiment]

[0132] Reference Figures 16 to 18 A driving method for a photoelectric conversion device according to a third embodiment of the present invention is described. Figure 16 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 17 and Figure 18 This is a diagram illustrating an example of digital signal processing for the AD conversion value. Components similar to those in the photoelectric conversion device according to the first and second embodiments are indicated by the same reference numerals, and their description will be omitted or simplified.

[0133] In this embodiment, another driving method for the photoelectric conversion device described in the first embodiment will be described. Figure 16 The time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, output signal of amplifier 32, ramp signal, output signal of comparator 44 and count signal are shown.

[0134] In the driving method of this embodiment, to Figure 14 In the driving example, a time period (SAD time period TS3) is added for performing AD conversion on the pixel signal amplified by voltage amplification factor Gain3. In this embodiment, the case where voltage amplification factor Gain1 is C0 / C1 = 4, voltage amplification factor Gain2 is C0 / (C1+C2) = 2, and voltage amplification factor Gain3 is C0 / (C1+C2+C3) = 1 is described as an example.

[0135] Corresponding to each voltage amplification factor, the AD conversion period of the pixel signal amplified by voltage amplification factor Gain1 is defined as NAD period TN1 and SAD period TS1. Furthermore, the AD conversion period of the pixel signal amplified by voltage amplification factor Gain2 is SAD period TS2, and the AD conversion period of the pixel signal amplified by voltage amplification factor Gain3 is SAD period TS3. The change in level of the reference signal relative to time in SAD period TS2 and SAD period TS3 is set to twice the change in level of the reference signal relative to time in SAD period TS1. In each AD conversion period, as... Figure 16 As shown, the count values ​​i, j, k, and l are stored in memory 52.

[0136] exist Figure 17 In the diagram, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain1 is indicated by a solid line, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain2 is indicated by a single-dot dashed line, and the AD conversion result of the pixel signal amplified by voltage amplification factor Gain3 is indicated by a dashed line.

[0137] Figure 18 This diagram illustrates a method for multiplying the AD conversion results of pixel signals amplified by various voltage amplification factors by a predetermined digital gain and then synthesizing the results into an image. The AD conversion result of a pixel signal amplified by voltage amplification factor Gain2 becomes the same as the slope in the case of voltage amplification factor Gain1 by applying a digital gain of 4. The AD conversion result of a pixel signal amplified by voltage amplification factor Gain3 becomes the same as the slope in the case of voltage amplification factor Gain1 by applying a digital gain of 8.

[0138] In regions where the potential change on pixel output line 16 is less than 0.25V, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain1 is set as the image signal. In regions where the potential change on pixel output line 16 is 0.25V or greater but less than 0.5V, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain2 is used as the image signal. In regions where the potential change on pixel output line 16 is 0.5V or greater, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain3 is used as the image signal. The AD conversion results of the pixel signals amplified by voltage amplification factors Gain2 and Gain3 can be obtained by multiplying the AD conversion value i obtained in NAD period TN1 by the ratio of each voltage amplification factor and subtracting it from the AD conversion values ​​k and l.

[0139] To improve the signal-to-noise ratio (S / N), increasing the voltage amplification factor on the low-brightness side and increasing the ratio between different voltage amplification factors will not reduce the resolution of the AD conversion value on the high-brightness side. Therefore, in this embodiment, three voltage amplification factors, Gain1, Gain2, and Gain3, are set, and the optimal voltage amplification factor and resolution can be set for each brightness level. In this embodiment, three types of voltage amplification factors, Gain1, Gain2, and Gain3, are set; however, the voltage amplification factor settings are not limited to three types and can include four or more types.

[0140] During SAD transition periods TS2 and TS3, the change in the reference signal level relative to time or the frequency of the counter can be adjusted. For example, during SAD transition period TS2, the counter frequency is doubled, and during SAD transition period TS3, the change in the reference signal level relative to time is further doubled, and the counter frequency is doubled again. By setting it in this way, the resolution and AD conversion period can be optimized.

[0141] As described above, according to this embodiment, the S / N ratio can be further improved while suppressing the reduction of frame rate.

[0142] [Fourth Embodiment]

[0143] Reference Figures 19 to 21 A driving method for a photoelectric conversion device according to a fourth embodiment of the present invention is described. Figure 19 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 20 and Figure 21 This is a diagram illustrating an example of digital signal processing for the AD conversion value. Components similar to those in the photoelectric conversion apparatus according to the first to third embodiments are indicated by the same reference numerals, and their description will be omitted or simplified.

[0144] In this embodiment, another driving method for the photoelectric conversion device described in the first embodiment will be described. Figure 19 The time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, output signal of amplifier 32, ramp signal, output signal of comparator 44 and count signal are shown.

[0145] The driving method in this embodiment differs from the driving example in the configuration for further improving the speed of the AD conversion. Specifically, the SAD period TS4 is executed instead of... Figure 14 The driving example includes the SAD period TS1. A judgment period TJ is added before the SAD period TS4. As for the voltage amplification factor of amplifier 32, the case where the voltage amplification factor Gain1 is 2 and the voltage amplification factor Gain2 is 1, as in the first embodiment, will be described as an example.

[0146] During the SAD period TS4, two slope reference signals are used for AD conversion. Here, it is assumed that these two reference signals are ramp signal H and ramp signal L, and the slope of ramp signal H is twice the slope of ramp signal L. The slope of ramp signal L is... Figure 14 The slope of the reference signal in the SAD period TS1 of the driving example is the same.

[0147] During the judgment period TJ, the output level of amplifier 32 is compared with the maximum value level VL of ramp signal L. When the output level of amplifier 32 is lower than level VL, the comparison operation for SAD period TS4 is performed using ramp signal L. On the other hand, when the output level of amplifier 32 is higher than level VL, the comparison operation for SAD period TS4 is performed using ramp signal H. That is, when the potential change of pixel output line 16 is less than 0.25V, AD conversion is performed using ramp signal L with a resolution of 12 bits, and when the potential change of pixel output line 16 is 0.25V or greater, AD conversion is performed using ramp signal H with a resolution of 11 bits.

[0148] By applying a digital gain twice that of the digital gain in the digital signal processing unit 70, the AD conversion value converted using the ramp signal H is synthesized with the AD conversion result converted using the ramp signal L. (See reference...) Figure 9 As stated above, when the potential change of pixel output line 16 is 0.25V or greater, the impact on image quality is minimal, even at a resolution of 10 bits, when considering optical shot noise. Therefore, Figure 14 In the driving example, the SAD period TS1 can be changed to a half-time SAD period TS4. On the other hand, in the SAD period TS2, as in Figure 14 As in the driving example case, an AD conversion is performed using a reference signal with the same slope as the ramp signal H.

[0149] The pixel signal amplified by the voltage amplification factor Gain1 is compared using either ramp signal L or ramp signal H. Specifically, ramp signal L is used for comparison when the potential change of pixel output line 16 is less than 0.25V. When the potential change of pixel output line 16 is 0.25V or greater, ramp signal H is used for comparison, and a digital gain of twice is applied to the AD conversion value obtained through the comparison operation. Thus, the AD conversion result for the pixel signal amplified by the voltage amplification factor Gain1 is obtained.

[0150] exist Figure 20 In the diagram, the AD conversion result of the pixel signal amplified by voltage amplification factor Gain1 using ramp signal L is shown by a solid line, and the AD conversion result of the pixel signal amplified by voltage amplification factor Gain1 using ramp signal H is shown by a dashed line. The AD conversion result of the pixel signal amplified by voltage amplification factor Gain2 is indicated by a dashed line.

[0151] Figure 21 This diagram illustrates a method for multiplying the AD conversion results of pixel signals amplified by various voltage amplification factors by a digital gain and then synthesizing the results into an image. The AD conversion results of the pixel signals amplified by the voltage amplification factor Gain2 are processed as follows: Figure 11 In the case of applying a 4x digital gain, the slope becomes the same as that of the voltage amplification factor Gain1.

[0152] During the comparison operation of a pixel signal amplified by voltage amplification factor Gain2, the slope of the reference signal can be changed in the same manner as in the comparison operation of a pixel signal amplified by voltage amplification factor Gain1. Furthermore, the voltage amplification factor and the slope of the ramp signal can be optimally set according to the noise level and the desired resolution.

[0153] As described above, in this embodiment, the tilt of the reference signal is switched based on the output levels of the pixel output line 16 and the amplifier 32. Therefore, according to this embodiment, the frame rate reduction can be further suppressed by shortening the readout time while improving the S / N ratio.

[0154] [Fifth Embodiment]

[0155] Reference Figure 22 and Figure 23 A photoelectric conversion device and its driving method according to a fifth embodiment of the present invention are described. Figure 22 This is a diagram illustrating the signal processing content in the photoelectric conversion device according to this embodiment. Figure 23This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Components similar to those in the photoelectric conversion devices according to the first to fourth embodiments are indicated by the same reference numerals, and their descriptions will be omitted or simplified.

[0156] The photoelectric conversion device according to this embodiment is configured to adjust the timing of signal processing and each signal processing step. That is, the photoelectric conversion device according to this embodiment is configured, for example, as... Figure 22 The diagram shows the ability to selectively perform signal processing (A) to signal processing (D).

[0157] Signal processing (A) refers to the use of signal processing in the first embodiment. Figure 10 The described signal processing. In Figure 10 In the driving example, regardless of the result of the AD conversion in the SAD period TS1 of the pixel signal amplified by the voltage amplification factor Gain1, the comparison operation is performed in the SAD period TS2 of the pixel signal amplified by the voltage amplification factor Gain2. (See reference...) Figures 11 to 13 As stated above, when the potential change of the pixel output line 16 is less than 0.5V, since the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain1 is used for the image, it is not always necessary to perform the comparison operation of the voltage amplification factor Gain2.

[0158] Signal processing (B) is an example of signal processing performed when the AD conversion result of the pixel signal amplified by voltage amplification factor Gain1 does not exceed 4096 LSB, the comparison operation of the pixel signal amplified by voltage amplification factor Gain2 is not performed, and amplifier 32 and comparator 44 are controlled in a power-saving state. The power-saving state is a state in which the drive current of amplifier 32 or comparator 44 is cut off or reduced.

[0159] Signal processing (C) is an example of signal processing where the comparison operation of the pixel signal amplified by the voltage amplification factor Gain1 is not performed, the pixel signal is held or in a power-saving state, and only the comparison operation of the pixel signal amplified by the voltage amplification factor Gain2 is performed. For example... Figure 23 As shown, for example, signal processing (C) can be implemented by comparing the output level of amplifier 32 with the maximum value level VH of ramp signal H during the judgment period TJ described in the fourth embodiment. That is, when it is determined, as a result of the comparison between the output level of amplifier 32 and level VH, that the potential change of pixel output line 16 is equal to or greater than 0.5V, the comparison operation can be performed only on the pixel signal amplified by voltage amplification factor Gain2.

[0160] Signal processing (D) is another example of signal processing. For example, when the voltage amplification factor Gain1 is less than the voltage amplification factor Gain2, the AD conversion result of the voltage amplification factor Gain2 can be predicted by multiplying the AD conversion result of the SAD period TS1 by Gain2 / Gain1. For example, a shortened SAD period TS3 is executed based on the AD conversion result of the SAD period TS1, and thereafter, as in signal processing (B), the individual blocks are controlled to a power-saving state. Since the AD conversion result is obtained through a count value, the amplitude of the pixel output line 16 can be detected from the data stored in specific high bits of the multiple memories 52.

[0161] As described above, in this embodiment, the amplitude of the pixel signal is detected based on the results of the AD conversion periods with different voltage amplification factors and the judgment unit, and the signal processing time and each process are controlled. Therefore, according to this embodiment, power consumption and the impact of crosstalk such as noise caused by AD conversion on other pixel signals can be reduced.

[0162] [Sixth Embodiment]

[0163] Reference Figures 24 to 26 A photoelectric conversion device and its driving method according to a sixth embodiment of the present invention are described. Figure 24 and Figure 25 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 26 This is a diagram illustrating the signal processing in the photoelectric conversion device according to an embodiment. Components similar to those in the photoelectric conversion devices according to the first to fifth embodiments are indicated by the same reference numerals, and their descriptions will be omitted or simplified.

[0164] In this embodiment, another driving method for the photoelectric conversion device described in the first embodiment will be described. Figure 24 The diagram shows the time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, the output signal of amplifier 32, the ramp signal, and the output signal of comparator 44. In the driving method of this embodiment, the voltage amplification factor can be switched during the comparison operation of the SAD period TS2.

[0165] Reference in the first embodiment Figure 10 and Figure 14In the described driving example, when the potential change of pixel output line 16 exceeds 0.5V with a voltage amplification factor Gain1 of 2, the potential change of pixel output line 16 exceeds the input dynamic range of the AD conversion during the SAD period TS1. In this case, the AD conversion result during the comparison operation of the pixel signal amplified by a voltage amplification factor Gain2 (=1) in the SAD period TS2 is valid as the image signal.

[0166] On the other hand, when the potential change of pixel output line 16 is less than 0.5V in SAD period TS1, as described in the fifth embodiment, the AD conversion result in SAD period TS1, where the pixel signal is amplified by a voltage amplification factor Gain1 (=2), is valid as an image signal. Therefore, the comparison operation in SAD period TS2 becomes unnecessary.

[0167] Assuming the AD conversion value in NAD period TN1 is 100 LSB, in SAD period TS1, the full scale of the AD conversion result is set to 4096 LSB, thus being configured to be limited to 100 LSB + 4096 LSB. This configuration can be achieved, for example, by adjusting the tilt of the counting signal and the reference signal.

[0168] In this embodiment, when the AD conversion result in the SAD period TS1 does not exceed the full-scale 4096LSB+100LSB, the voltage amplification factor Gain2 in the SAD period TS2 is made variable.

[0169] exist Figure 24 In the driving example, when the AD conversion result in SAD period TS1 does not exceed the full-scale 4096LSB+100LSB, driving is performed in SAD period TS2 using the voltage amplification factor Gain1. Figure 24 In the SAD period TS2, the amplifier output and comparator output are indicated by dashed lines when the voltage amplification factor is Gain1, and by solid lines when the voltage amplification factor is Gain2.

[0170] During the SAD periods TS1 and TS2, the results of AD conversion with the same voltage amplification factor Gain1 become two correlated signals, and noise components in the AD conversion results can be reduced by performing root mean square signal processing. For example, if AD conversion results with the same resolution are obtained by adjusting the counter frequency as described in the second embodiment, the noise component can be reduced to 1 / √2.

[0171] Figure 25 Shown in reference Figure 24The described driver example performs multiple comparison operations during the SAD period TS2. Figure 25 The diagram shows the time variations of the voltage amplification factor of amplifier 32, control signals PRES, PTX and PSEL, control signals of switches S0, S1, S2 and S3, the output signal of amplifier 32, the ramp signal, and the output signal of comparator 44. Figure 25 In the process, two comparison operations are performed during the SAD period TS2, but the number of comparison operations is not limited to two.

[0172] The comparison operations in SAD period TS2 can be determined based on the AD conversion result of SAD period TS1. For example, when the AD conversion result of SAD period TS1 is equal to or less than half of the full scale, in SAD period TS2, comparison operations can be performed only in half of the time required for the full-scale AD conversion, and the number of comparisons can be increased. By increasing the number of comparisons, the noise reduction can be increased through RMS signal processing. Specifically, since the number of comparisons can increase as brightness decreases, the noise reduction can be increased and the S / N ratio can be improved.

[0173] As the number of comparisons increases, the required amount of memory 52 may increase. In this case, for example, if memory 52 uses 13 bits at full scale, then some of those 13 bits can be used for individual comparison operations. By configuring memory 52 in this way, the increase in memory 52 can be suppressed.

[0174] As described in the fifth embodiment Figure 22 Similarly, Figure 26 An example of signal processing that can be performed in the photoelectric conversion device according to this embodiment is illustrated schematically.

[0175] Signal processing (E) is a driving example that performs four comparison operations during the SAD period TS2. Signal processing (F) is an example of a case where the brightness is lower than that in signal processing (E) (i.e., the comparison operation period is shorter than that in signal processing (E)), and is a driving example that performs four comparison operations during the SAD period TS2 and then sets a power-saving state.

[0176] As described in the first embodiment, the voltage amplification factor and the slope of the reference signal can be appropriately set. Furthermore, as a configuration including an adjustment mechanism for adjusting the capacitor value of the floating diffusion FD of pixel 12, a configuration that switches the capacitor value based on the AD conversion result can be adopted. Additionally, the AD conversion period of the SAD period TS1 can be reduced by combining it with the second and fourth embodiments.

[0177] As described above, in this embodiment, the voltage amplification factor and the number of comparison operations in other AD conversion periods are set based on the AD conversion result. Therefore, according to this embodiment, the S / N ratio can be further improved.

[0178] [Seventh Embodiment]

[0179] Reference Figure 27 A camera system according to a seventh embodiment of the present invention is described. Figure 27 This is a block diagram illustrating a schematic configuration of the camera system according to this embodiment.

[0180] The photoelectric conversion device 100 described in the first to sixth embodiments can be applied to various camera systems. Examples of applicable camera systems include digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules that include optical systems such as lenses and camera devices are also included in the camera system. Figure 27 This is a block diagram of a digital still camera, which serves as an example of these.

[0181] Figure 27 The illustrated camera system 200 includes a camera device 201, a lens 202 for forming an optical image of a subject on the camera device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and aperture 204 form an optical system on the camera device 201 for collecting light. The camera device 201 is a photoelectric conversion device 100 as described in any of the first to sixth embodiments, and converts the optical image formed by the lens 202 into image data.

[0182] The camera system 200 also includes a signal processing unit 208 for processing the output signal from the camera device 201. The signal processing unit 208 generates image data based on the digital signal output from the camera device 201. The signal processing unit 208 performs various corrections and compressions as needed and outputs the processed image data. The camera device 201 may include an AD conversion unit for generating the digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the camera device 201 is formed, or it may be formed in a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the camera device 201 is formed. The signal processing unit 208 may be formed on the same semiconductor substrate as the camera device 201.

[0183] The camera system 200 also includes a memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the camera system 200 includes a storage medium 214, such as a semiconductor memory, for storing or retrieving camera data, and a storage medium control interface unit (storage medium control I / F unit) 216 for storing or retrieving camera data from the storage medium 214. The storage medium 214 may be built into the camera system 200 or may be removable.

[0184] The camera system 200 also includes an overall control / computation unit 218 for controlling various calculations and the operation of the entire digital still camera, and a timing generation unit 220 for outputting various timing signals to the camera device 201 and the signal processing unit 208. Here, timing signals, etc., can be input from the outside, and the camera system 200 may include at least the camera device 201 and the signal processing unit 208 for processing the output signals output from the camera device 201.

[0185] The camera device 201 outputs a camera signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the camera signal output from the camera device 201 and outputs image data. The signal processing unit 208 uses the camera signal to generate an image.

[0186] As described above, according to this embodiment, a camera system applying the photoelectric conversion device 100 according to the first to sixth embodiments can be realized.

[0187] [Eighth Embodiment]

[0188] Reference Figure 28A and Figure 28B A camera system and a moving body according to an eighth embodiment of the present invention are described. Figure 28A This is a diagram illustrating the configuration of the camera system according to this embodiment. Figure 28B This is a diagram illustrating the configuration of the moving body according to this embodiment.

[0189] Figure 28AAn example of a camera system related to a vehicle-mounted camera is shown. The camera system 300 includes a camera device 310. The camera device 310 is the photoelectric conversion device 100 described in any of the first to sixth embodiments. The camera system 300 includes an image processing unit 312 and a parallax acquisition unit 314. The image processing unit 312 performs image processing on multiple image data acquired by the camera device 310, and the parallax acquisition unit 314 calculates the parallax (phase difference of the parallax image) based on the multiple image data acquired by the camera device 310. The camera system 300 includes a distance acquisition unit 316 and a collision determination unit 318. The distance acquisition unit 316 calculates the distance to an object based on the calculated parallax, and the collision determination unit 318 determines the possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition units used to acquire distance information to an object. That is, the distance information can be information related to parallax, defocus, distance to an object, etc. The collision determination unit 318 can use any of the distance information from this distance information to determine the probability of a collision. The distance information acquisition unit can be implemented by dedicated hardware or software modules. Alternatively, it can be implemented using an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit), or a combination thereof.

[0190] The camera system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Furthermore, the camera system 300 is connected to a control ECU 330, which is a control device for outputting control signals to the vehicle to generate braking force based on the judgment result of the collision judgment unit 318. The camera system 300 is also connected to an alarm device 340 for issuing warnings to the driver based on the judgment result of the collision judgment unit 318. For example, when the collision probability is high according to the judgment result of the collision judgment unit 318, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by braking, returning the accelerator to its original position, or suppressing engine output. The alarm device 340 alerts the user by emitting alarms such as sounds, displaying alarm information on a screen such as a car navigation system, or applying vibrations to the seat belt or steering wheel.

[0191] In this embodiment, the camera system 300 captures images of the area around the vehicle (e.g., the front or rear). Figure 28B The image capture system is shown in a configuration where it captures images in front of the vehicle (within a camera range of 350). The vehicle information acquisition device 320 sends commands to the image capture system 300 or the image capture device 310. This configuration can further improve the accuracy of distance measurement.

[0192] The above description has described examples of controlling the vehicle to avoid collisions with other vehicles; however, the invention is also applicable to autonomous driving control that follows other vehicles and autonomous driving control that prevents the vehicle from leaving its lane. Furthermore, the camera system is not limited to vehicles such as the host vehicle, but can be applied to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. In addition, the invention is applicable not only to mobile bodies but also to a wide variety of devices such as Intelligent Transportation Systems (ITS).

[0193] [Ninth Embodiment]

[0194] Reference Figure 29 A device according to a ninth embodiment of the present invention is described. Figure 29 This is a block diagram illustrating a schematic configuration of the device according to this embodiment.

[0195] Figure 29 This is a schematic diagram illustrating a device EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functionality of the photoelectric conversion device 100 of any of the first to sixth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this embodiment can be used, for example, as an image sensor, an AF (autofocus) sensor, a metering sensor, or a distance measurement sensor. The semiconductor device IC includes a pixel region PX, in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC may include a peripheral region PR around the pixel region PX. Circuitry other than the pixel circuits may be arranged in the peripheral region PR.

[0196] The photoelectric conversion device APR can have a structure in which a first semiconductor chip having multiple photoelectric conversion units is stacked and a second semiconductor chip having peripheral circuits is stacked (a chip stack structure). Each peripheral circuit in the second semiconductor chip can be a column circuit corresponding to a pixel column of the first semiconductor chip. The peripheral circuits in the second semiconductor chip can also be matrix circuits corresponding to pixels or pixel blocks of the first semiconductor chip. The connection between the first and second semiconductor chips can be achieved through-electrode (TSV), chip-to-chip interconnection via direct bonding through a conductor such as copper, connection via micro-bumps between chips, or connection via wiring.

[0197] In addition to semiconductor device ICs, photoelectric conversion devices (APRs) may include a package PKG that houses the semiconductor device IC. The package PKG may include a substrate to which the semiconductor device IC is fixed, a cover made of glass or the like facing the semiconductor device IC, and connecting members (such as bonding wires or bumps) that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0198] The device EQP may also include at least one of the following: an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR, which is a photoelectric conversion device, and is, for example, a lens, shutter, or mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC (Application-Specific Integrated Circuit). The processing device PRCS processes the signal output from the photoelectric conversion device APR and constitutes an AFE (Analog Front End) or DFE (Digital Front End). The processing unit PRCS is a semiconductor device such as a central processing unit (CPU) or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays the information (images) obtained by the photoelectric conversion device APR. The storage device MMRY may be a magnetic device or a semiconductor device that stores the information (images) obtained by the photoelectric conversion device APR. The storage device MMR may be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN includes a movable or propulsion part such as a motor or engine. In the device EQP, the signal output from the photoelectric conversion device APR can be displayed on the display device DSPL and transmitted to the outside via a communication device (not shown) included in the device EQP. Therefore, the device EQP preferably also includes a storage device MMRY and a processing device PRCS, which are separate from the storage circuit unit and the arithmetic circuit unit included in the photoelectric conversion device APR.

[0199] Figure 29 The illustrated device EQP can be an electronic device such as an information terminal with shooting capabilities (e.g., a smartphone or wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, and a surveillance camera). The mechanical device MCHN in the camera can drive the components of the optical device OPT to perform zoom, focus, and shutter operations. The device EQP can be a transportation device (mobile body) such as a vehicle, ship, or aircraft. The device EQP can be a medical device such as an endoscope or a CT scanner.

[0200] The mechanical device MCHN in the transport device can be used as a mobile device. The equipment EQP as a transport device is suitable for transporting the photoelectric conversion device APR, or suitable for assisting and / or automating operation (manipulation) through camera functionality. The processing device PRCS for assisting and / or automating operation (manipulation) can perform processing for operating the mechanical device MCHN as a mobile device based on information obtained from the photoelectric conversion device APR.

[0201] The photoelectric conversion device APR according to this embodiment can provide high value to designers, manufacturers, sellers, buyers, and / or users. Therefore, when the photoelectric conversion device APR is installed on the device EQP, the value of the device EQP can be increased. Therefore, in order to increase the value of the device EQP, it is advantageous to determine that the installation of the photoelectric conversion device APR of this embodiment on the device EQP is beneficial when manufacturing and selling the device EQP.

[0202] [Modified Embodiments]

[0203] The present invention is not limited to the above embodiments, and various modifications are possible.

[0204] For example, adding a portion of the configuration of any embodiment to an example of another embodiment, or replacing a portion of the configuration of any embodiment with a portion of the configuration of another embodiment, are also examples of embodiments of the present invention.

[0205] Figure 2 The circuit configuration of pixel 12 shown is an example and can be changed appropriately. For example, each pixel 12 may include two or more photoelectric conversion elements. Furthermore, multiple photoelectric conversion elements of a pixel 12 can constitute a pupil-segmented pixel sharing a single microlens. Pixel 12 does not necessarily need to include a selection transistor M4. The capacitance value of the floating diffusion FD can be switchable. In this case, the voltage amplification factor of the pixel signal can be set by a combination of the amplification factor (gain Gsf) of the source follower circuit and the amplification factor of amplifier 32, which can be switched by the capacitance value of the floating diffusion FD.

[0206] Although one pixel output line 16 is arranged in each column in the above embodiment, two or more pixel output lines 16 can be arranged in each column. In this case, each pixel 12 can be connected to one of the pixel output lines 16 in each column, or can include multiple selection transistors corresponding to the number of pixel output lines 16 in each column.

[0207] Figure 3 The circuit configuration of amplifier 32 shown is an example and can be changed appropriately. For example, in Figure 3In the configuration example, the three feedback capacitors C1, C2, and C3 can be connected in parallel to amplifier circuit 34, but the number of feedback capacitors is not limited to this. Although in Figure 3 The configuration example sets the input capacitor C0, but the value of the input capacitor can be switched. The circuit configuration of amplifier 32 can be appropriately changed according to the type of voltage amplification factor required, etc.

[0208] The camera systems described in the seventh and eighth embodiments are examples of camera systems to which the photoelectric conversion device of the present invention can be applied, and the camera systems to which the photoelectric conversion device of the present invention can be applied are not limited to those described in the seventh and eighth embodiments. Figure 27 and Figure 28A The configuration shown.

[0209] The device described in the ninth embodiment is an example of a device to which the photoelectric conversion device of the present invention can be applied, and the device to which the photoelectric conversion device of the present invention can be applied is not limited to. Figure 14 The configuration shown.

[0210] Other embodiments

[0211] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads out and executes the program.

[0212] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: A pixel, which includes a photoelectric conversion unit; An amplification unit is configured to amplify the analog signal generated in the pixel using an amplification factor, the amplification factor being configured to be changeable; The AD conversion unit is used to perform AD conversion on the analog signal by comparing the level of the analog signal amplified by the amplification unit with the level of a reference signal whose level changes with time. as well as The control unit is configured to control the AD conversion unit. The control unit is configured to control the AD conversion unit to perform multiple AD conversions on the same analog signal generated in the pixel and amplified by the amplification unit. Wherein, the length of the first AD conversion period in the multiple AD conversions is shorter than the length of the second AD conversion period in the multiple AD conversions. In the second AD conversion period, the rate of change of the reference signal relative to time is less than the rate of change of the reference signal relative to time used in the first AD conversion period. During the second AD conversion period, the potential of the reference signal changes from a second level to a first level. During the first AD conversion period, the potential of the reference signal changes from the second level to the first level, and The AD conversion unit performs AD conversion on the analog signal amplified by a first amplification factor during the first AD conversion period, and performs AD conversion on the analog signal amplified by a second amplification factor during the second AD conversion period.

2. The photoelectric conversion device according to claim 1, in, The AD conversion unit includes a comparator configured to perform a comparison operation between the level of the analog signal and the level of the reference signal.

3. The photoelectric conversion device according to claim 1, in, The AD conversion unit includes: A comparator configured to perform a comparison operation between the level of the analog signal and the level of the reference signal; and A counter, configured to begin counting the clock signal in response to the start of the comparison operation, and The frequency of the counter in the first AD conversion period is different from the frequency of the counter in the second AD conversion period.

4. The photoelectric conversion device according to any one of claims 1 to 3, wherein, The control unit sets the rate of change of the reference signal relative to time based on the level of the analog signal in at least one of the multiple AD conversions.

5. The photoelectric conversion device according to claim 1, in, The amplification unit is configured to change the amplification factor, and The control unit sets the length of the AD conversion period in at least one of the multiple AD conversions based on the amplification factor of the amplification unit.

6. The photoelectric conversion device according to claim 1, wherein, The AD conversion unit is configured to perform AD conversion on each signal obtained by amplifying the analog signal by at least three amplification factors.

7. The photoelectric conversion device according to claim 1, wherein, The control unit sets the amplification factor of the analog signal to be converted in one of the multiple AD conversions based on the AD conversion results of other AD conversions in the multiple AD conversions.

8. The photoelectric conversion device according to any one of claims 1 to 3, wherein, The control unit sets the length of the AD conversion period in one of the multiple AD conversions based on the AD conversion results of other AD conversions in the multiple AD conversions.

9. The photoelectric conversion device according to any one of claims 1 to 3, wherein, The control unit controls the drive current of the AD conversion unit in one of the multiple AD conversions based on the AD conversion results of other AD conversions in the multiple AD conversions.

10. The photoelectric conversion device according to any one of claims 1 to 3, wherein, The control unit sets the number of AD conversions based on the result of one AD conversion.

11. The photoelectric conversion device according to any one of claims 1 to 3, further comprising a digital signal processing unit, the digital signal processing unit being configured to perform digital signal processing on the digital signal transmitted from the AD conversion unit. in, The AD conversion unit is configured to reduce the number of bits in at least a portion of the digital signals obtained through the multiple AD conversions, and to transmit the digital signals with reduced bits to the digital signal processing unit.

12. The photoelectric conversion device according to any one of claims 1 to 3, further comprising a digital signal processing unit, the digital signal processing unit being configured to perform digital signal processing on the digital signal transmitted from the AD conversion unit. in, The digital signal processing unit is configured to reduce the number of bits in at least a portion of the digital signals obtained through the multiple A / D conversions, and to perform the digital signal processing on the digital signals with the reduced number of bits.

13. The photoelectric conversion device according to any one of claims 1 to 3, further comprising a digital signal processing unit, the digital signal processing unit being configured to perform digital signal processing on the digital signal transmitted from the AD conversion unit. in, The digital signal processing unit performs digital gain processing on the digital signal based on the rate of change of the reference signal relative to time.

14. The photoelectric conversion device according to claim 1, further comprising a digital signal processing unit configured to perform digital signal processing on the digital signal transmitted from the AD conversion unit. in, The digital signal processing unit performs digital gain processing on the digital signal based on the amplification factor of the analog signal.

15. The photoelectric conversion device according to claim 3, further comprising a digital signal processing unit configured to perform digital signal processing on the digital signal transmitted from the AD conversion unit. in, The digital signal processing unit performs digital gain processing on the digital signal according to the frequency of the counter.

16. The photoelectric conversion device according to claim 11, wherein, The digital signal processing unit generates an image signal by synthesizing multiple digital signals obtained through the multiple A / D conversions.

17. The photoelectric conversion device according to claim 11, wherein, The digital signal processing unit generates a phase difference detection signal based on multiple digital signals obtained through the multiple A / D conversions.

18. The photoelectric conversion device according to claim 11, wherein, The digital signal processing unit generates an image signal by averaging multiple digital signals obtained through the multiple A / D conversions.

19. A driving method for a photoelectric conversion device, the photoelectric conversion device comprising a pixel, an amplification unit, and an analog-to-digital (AD) conversion unit, the pixel comprising the photoelectric conversion unit, the amplification unit configured to amplify an analog signal generated in the pixel using an amplification factor, the amplification factor being configured to be changeable, the AD conversion unit configured to perform AD conversion on the analog signal by comparing the level of the analog signal amplified by the amplification unit with the level of the reference signal whose level changes over time, the driving method comprising: The same analog signal generated in the pixel and amplified by the amplification unit is subjected to multiple AD conversions with different lengths to obtain multiple digital signals corresponding to the multiple AD conversions; as well as An image signal is generated by synthesizing the multiple digital signals. Wherein, the length of the first AD conversion period in the multiple AD conversions is shorter than the length of the second AD conversion period in the multiple AD conversions; the rate of change of the reference signal relative to time used in the second AD conversion period is less than the rate of change of the reference signal relative to time used in the first AD conversion period; in the second AD conversion period, the potential of the reference signal changes from a second level to a first level; and in the first AD conversion period, the potential of the reference signal changes from a second level to the first level. Specifically, during the first AD conversion period, an AD conversion is performed on the analog signal amplified by a first amplification factor, and during the second AD conversion period, an AD conversion is performed on the analog signal amplified by a second amplification factor.

20. A camera system, comprising: The photoelectric conversion device according to any one of claims 1 to 18; as well as A signal processing unit is configured to process the signal output from the photoelectric conversion device.

21. A mobile body, comprising: The photoelectric conversion device according to any one of claims 1 to 18; A distance information acquisition unit is configured to acquire distance information to an object from a parallax image based on a signal from the photoelectric conversion device; as well as A control unit is configured to control the moving body based on the distance information.

22. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 18, further comprising at least one of the following devices: An optical device, corresponding to the photoelectric conversion device, A control device configured to control the photoelectric conversion device. A processing device configured to process the signal output from the photoelectric conversion device. A mechanical device that is controlled based on information obtained from the photoelectric conversion device. A display device configured to display information obtained by the photoelectric conversion device, and A storage device configured to store information obtained by the photoelectric conversion device.

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