A masterless distributed high-speed data acquisition device and method

Abstract

This invention discloses a masterless distributed high-speed data acquisition device and method, belonging to the field of space microwave remote sensing technology. The device includes an ADC high-speed acquisition module, a low-frequency connector, and an optical module. The ADC high-speed acquisition module is used to acquire and preprocess dual-channel data, while the optical module is used to download the preprocessed data. The low-frequency connector provides one power supply and transmits a configuration signal to the ADC high-speed acquisition module, and also provides one power supply to the optical module. This device significantly reduces its size while achieving high-speed acquisition, making it suitable for application in various circuits.

Description

Technical Field

[0001] This invention belongs to the field of space microwave remote sensing technology, and specifically relates to a masterless distributed high-speed acquisition device and method. Background Technology

[0002] Various application scenarios, such as marine oil and gas exploration, sonar exploration, satellite launch, navigation, missile control, submarine positioning, integrated observation, and real-time communication, have put forward requirements for high performance, low power consumption, high flexibility, and even distributed form for signal acquisition.

[0003] Currently, distributed data acquisition technology is combined with a main control chip (CPU, FPGA, etc.). The main control chip configures the ADC chip. The ADC chip is configured first, and the power supply for both the main control chip and the ADC chip is provided by the power distribution section. After configuration, the ADC chip converts the signal to be acquired into high-speed data, which is then sent by the main control chip to the optical module for conversion into optical signals and transmitted out, completing the data acquisition function of the entire acquisition device. This data acquisition method results in high power consumption. The demand for high-speed, multi-channel synchronous acquisition without a main control is increasingly strong, but a good solution still lacks. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art. This invention proposes a masterless distributed acquisition device and method. The device includes an ADC high-speed acquisition module, a low-frequency connector, and an optical module to realize high-speed data acquisition and data transmission of dual channels.

[0005] The present invention is achieved through the following technical solutions:

[0006] A masterless distributed high-speed acquisition device includes an ADC high-speed acquisition module, a low-frequency connector, and an optical module;

[0007] The ADC high-speed acquisition module is used to acquire and preprocess dual-channel data to be acquired, and the optical module is used to transmit the preprocessed data down. The low-frequency connector is used to input one power supply to the ADC high-speed acquisition module and transmit a configuration signal, and to input one power supply to the optical module.

[0008] Preferably, the low-frequency connector is externally connected to a central control and signal processing unit. The central control and signal processing unit supplies power to the low-frequency connector and sends clock, enable, and data three-wire configuration signals to the ADC high-speed acquisition module for configuration through the low-frequency connector. The data output by the optical module is sent to the central control and signal processing unit through optical fiber.

[0009] Preferably, the dual-channel signals to be sampled are connected to the input port of the ADC high-speed acquisition module. After sampling, the ADC high-speed acquisition module converts the analog signals into digital signals. The DDC control register in the module is configured by the configuration signal to realize DDC preprocessing of the digital signals. The preprocessed data is then output through the output pin of the module.

[0010] Preferably, an external frequency source inputs a sampling clock signal to the ADC high-speed acquisition module to control the ADC high-speed acquisition module to acquire dual-channel high-speed data, with a maximum sampling rate greater than 1 GSPS.

[0011] Preferably, the central control and signal processing unit sends synchronization reference signals and synchronization control signals to the corresponding ADC high-speed acquisition modules through multiple low-frequency connectors to achieve synchronous acquisition by multiple masterless distributed high-speed acquisition devices.

[0012] Preferably, it also includes a linear voltage regulator module for regulating the power supply signal transmitted through the low-frequency connector to generate the power required by the ADC high-speed acquisition module and the optical module.

[0013] Preferably, the performance of the ADC high-speed acquisition module meets the following requirements:

[0014] It has two or more acquisition channels, a sampling rate greater than 1Gbps, and a sampling bit depth greater than 12 bits;

[0015] The packaged module is less than 1cm*1cm in size, and the single-channel sampling power consumption is less than 0.8W.

[0016] The configuration has no more than 3 signal lines, and the digital signal output supports high-speed serial interface protocols.

[0017] Preferably, the performance of the optical module needs to meet the following requirements:

[0018] It has more than 8 transmission channels, with a single channel transmission rate greater than 8Gbps;

[0019] With a single power supply, the power consumption of a single transmitter is less than 0.3W;

[0020] It can directly forward and download data.

[0021] Preferably, the parameters of the ADC high-speed acquisition module are changed according to the acquisition rate or effective bit requirements, and the parameters of the optical module are changed according to different data output rates, so as to realize the application of masterless distributed high-speed acquisition equipment in different application scenarios.

[0022] A masterless distributed high-speed data acquisition method, comprising:

[0023] The ADC high-speed acquisition module is powered by an external central control and signal processing unit via a low-frequency connector.

[0024] The low-frequency connector sends the clock, enable, and data three-wire configuration signals to the ADC high-speed acquisition module.

[0025] An externally provided sampling clock is used for dual-channel high-speed data acquisition, with a maximum sampling rate greater than 1 GSPS;

[0026] The high-speed acquisition data output from the ADC high-speed acquisition module is input into the optical module, and the power transmission section of the optical module is less than 0.3W per channel.

[0027] The data output from the optical module is transmitted to the central control and signal processing unit via optical fiber.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1) The masterless distributed high-speed data acquisition device of this invention achieves a masterless design through the design of power supply and control signals. The ADC chip is powered by an external central control and signal processing unit via a low-frequency connector. The selected ADC chip has a maximum sampling rate greater than 1 GSPS, a single-channel power consumption of only 800mW, and a serial data transmission line rate of 16Gbps after acquisition. Data is output to the next-level processing unit through an optical module with a transmission power consumption of less than 2W. The ADC is configured by control signals from the central control and signal processing unit input through the connector. The configuration includes functions such as chip acquisition and DDC preprocessing. Finally, the data is transmitted down via optical fiber. The printed circuit board size of the device is only 7cm*8cm, far smaller than that of commercially available distributed data acquisition devices.

[0030] 2) The masterless distributed high-speed acquisition device proposed in this invention has strong versatility and can be directly applied as a general-purpose product in various fields. Furthermore, the hardware selection and design concepts provided by this invention can also be applied to scenarios with different requirements, requiring only adaptive modifications. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the architecture of a high-speed data acquisition device in the existing technology;

[0032] Figure 2 This is a schematic diagram of a masterless distributed high-speed acquisition device architecture according to an embodiment of the present invention. Detailed Implementation

[0033] To facilitate understanding of the embodiments of the present invention, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of the present invention.

[0034] This invention proposes a masterless distributed high-speed data acquisition device, changing the design concept of existing high-speed data acquisition devices that include a master control chip, and realizing masterless distributed high-speed data acquisition. Existing high-speed data acquisition devices, such as... Figure 1 As shown, the ADC chip is configured by the main control chip, and the acquired data is buffered before being transmitted to the subsequent signal processing unit, which results in high power consumption. Furthermore, there is no good solution for the requirement of high-speed, multi-channel synchronous acquisition without a main control chip.

[0035] The device proposed in this invention, such as Figure 2 As shown, it includes an ADC high-speed acquisition module, a low-frequency connector, an optical module, and a linear voltage regulator module. The ADC high-speed acquisition module is used for dual-channel high-speed data acquisition. The low-frequency connector enables the transmission of power supply and configuration signals to the optical module. The optical module completes the downlink of the acquired data.

[0036] An external central control and signal processing unit supplies power to the low-frequency connector, which then outputs power to the linear regulator module. The linear regulator module processes the power and outputs it to the ADC high-speed acquisition module and the optical module. Simultaneously, the central control and signal processing unit sends clock, enable, and data three-wire signals to the ADC high-speed acquisition module for configuration via the low-frequency connector. An external frequency source is input via an RF interface to a transformer, where it is converted into a differential signal, serving as the sampling clock signal for the ADC high-speed acquisition module.

[0037] The external analog signal to be acquired is input through a high-frequency interface at one end. After input, it is converted into a differential signal by a transformer and output as a differential analog signal to the input port of the ADC high-speed acquisition module. After sampling, the ADC high-speed acquisition module converts the analog signal into a digital signal, performs DDC preprocessing on the digital signal, and outputs the preprocessed data to the optical module through a high-speed serial interface. Then, the optical module converts the input signal into an optical signal and outputs it to the central control and signal processing unit.

[0038] This device is used in scenarios requiring distributed data acquisition, and has strict requirements on device size and power consumption. Its ADC chip features: multi-channel high-speed, multi-bit acquisition (acquisition channels ≥ 2, sampling rate > 1Gbps, sampling bit depth > 12bit), small package (package < 1cm * 1cm), low power consumption (single-channel sampling power consumption < 0.8W), easy configuration (configuration signal lines ≤ 3), and support for high-speed serial interface protocols such as JESD204B for data output. Multiple chips can be synchronized and pre-processed. The device also requires a high degree of simplicity in signal connection and transmission configuration. Its optical module features: multi-channel high-speed transmission (number of channels > 8, single-channel transmission rate > 8Gbps), simple power supply (single-channel power supply), low power consumption (single-channel transmit power consumption < 0.3W), and direct data forwarding and downloading. Strict requirements are placed on device size; the device's external dimensions should be < 10cm * 10cm.

[0039] Through extensive physical comparison and experimental verification, a prototype engineering device was successfully manufactured. The printed circuit board (PCB) size is 7cm x 8cm, and the overall device dimensions are 8cm x 9cm. The ADC chip selected is the AD9695, with a package size of 9mm x 9mm, two channels, a sampling rate of 1.3Gbps, a sampling bit depth of 14 bits, and support for multi-channel high-speed serial output via the JESD204B protocol. It also supports multi-chip synchronization and preprocessing functions. The optical module selected is the TLD850M10GT parallel optical transmitter module. This module has 12 independent channels, each supporting 10Gbps high-speed transmission, powered by a 3.3V power supply, and supports multi-channel high-speed serial output via the JESD204B protocol. The total power consumption for all 12 channels is 1.5W.

[0040] The masterless distributed high-speed data acquisition method is as follows:

[0041] (1) The ADC chip AD9695 is powered by an external central control and signal processing unit via the low-frequency connector J30J-9ZKW.

[0042] (2) Configure AD9695 using the same connector J30J-9ZKW as in step (1). The configuration includes the acquisition register and the DDC configuration register.

[0043] (3) An external sampling clock is provided for dual-channel high-speed data acquisition, with a maximum sampling rate greater than 1GSPS.

[0044] (4) Input the high-speed acquisition data output by AD9695 into the optical module TLD850M10GT. The power transmission section of the optical module is 0.3W per channel.

[0045] (5) Data is output to the central control and signal processing unit via optical fiber.

[0046] This device can be used in parallel. The central control and signal processing unit sends synchronous reference signals and synchronous control signals to multiple devices with the same design as this device, so as to realize synchronous acquisition of multiple devices.

[0047] For other different application scenarios, this device can be adapted, including but not limited to: changing the low-frequency connector model according to the input signal requirements, changing the ADC high-speed acquisition module according to the acquisition rate or effective bit requirements, and changing the optical module according to different data output rates.

[0048] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0049] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A masterless distributed high-speed data acquisition device, characterized in that, Includes ADC high-speed acquisition module, low-frequency connector, and optical module; The ADC high-speed acquisition module is used to acquire and preprocess dual-channel data to be acquired; the optical module is used to transmit the preprocessed data; the low-frequency connector is used to input one power supply to the ADC high-speed acquisition module and transmit a configuration signal, and to input one power supply to the optical module. The low-frequency connector is externally connected to the central control and signal processing unit. The central control and signal processing unit supplies power to the low-frequency connector and sends the clock, enable, and data three-wire configuration signals to the ADC high-speed acquisition module for configuration through the low-frequency connector. The data output by the optical module is sent to the central control and signal processing unit through optical fiber.

2. The masterless distributed high-speed data acquisition device according to claim 1, characterized in that, The dual-channel signals to be sampled are connected to the input port of the ADC high-speed acquisition module. After sampling, the ADC high-speed acquisition module converts the analog signals into digital signals. The DDC control register in the module is configured by the configuration signal to realize DDC preprocessing of the digital signals. The preprocessed data is output through the output pin of the module.

3. The masterless distributed high-speed data acquisition device according to claim 2, characterized in that, An external frequency source inputs a sampling clock signal to the ADC high-speed acquisition module to control the ADC high-speed acquisition module to acquire dual-channel high-speed data, with a maximum sampling rate greater than 1 GSPS.

4. A masterless distributed high-speed data acquisition device according to claim 1, characterized in that, The central control and signal processing unit sends synchronization reference signals and synchronization control signals to the corresponding ADC high-speed acquisition modules through multiple low-frequency connectors, enabling synchronous acquisition by multiple masterless distributed high-speed acquisition devices.

5. A masterless distributed high-speed data acquisition device according to claim 1, characterized in that, It also includes a linear voltage regulator module, which is used to regulate the power supply signal transmitted through the low-frequency connector to generate the power required by the ADC high-speed acquisition module and the optical module.

6. A masterless distributed high-speed data acquisition device according to claim 1, characterized in that, The performance of the ADC high-speed acquisition module meets the following requirements: It has two or more acquisition channels, a sampling rate greater than 1Gbps, and a sampling bit depth greater than 12 bits; The packaged module is less than 1cm in size. 1cm, single-channel sampling power consumption is less than 0.8W; The configuration has no more than 3 signal lines, and the digital signal output supports high-speed serial interface protocols.

7. A masterless distributed high-speed data acquisition device according to claim 1, characterized in that, The optical module must meet the following performance requirements: It has more than 8 transmission channels, with a single channel transmission rate greater than 8Gbps; With a single power supply, the power consumption of a single transmitter is less than 0.3W; It can directly forward and download data.

8. A masterless distributed high-speed data acquisition device according to claim 1, characterized in that, By adjusting the parameters of the ADC high-speed acquisition module according to the acquisition rate or effective bit requirements, and by adjusting the parameters of the optical module according to different data output rates, the masterless distributed high-speed acquisition device can be applied in different application scenarios.

9. A masterless distributed high-speed data acquisition method, employing the masterless distributed high-speed data acquisition device as described in claim 1, characterized in that... include: The ADC high-speed acquisition module is powered by an external central control and signal processing unit via a low-frequency connector. The low-frequency connector sends the clock, enable, and data three-wire configuration signals to the ADC high-speed acquisition module. An externally provided sampling clock is used for dual-channel high-speed data acquisition, with a maximum sampling rate greater than 1 GSPS; The high-speed acquisition data output from the ADC high-speed acquisition module is input into the optical module, and the power transmission section of the optical module is less than 0.3W per channel. The data output from the optical module is transmitted to the central control and signal processing unit via optical fiber.

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