Semiconductor structure, method of fabricating the same, and memory system

Abstract

The semiconductor structure includes: an active pillar array, including first active pillars and second active pillars arranged in an array along a first direction and a second direction, the first active pillars and the second active pillars each including a channel region and a first active region and a second active region located at opposite ends of the channel region along a third direction, the third direction being a direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction; a first storage structure located on a first side of the active pillar array; a second storage structure located on a second side of the active pillar array; a geometric center of a first plane projection of the first active pillar is offset from a geometric center of a first plane projection of the first storage structure along the second direction; and / or a geometric center of a first plane projection of the second active pillar is offset from a geometric center of a first plane projection of the second storage structure along the second direction; the first plane is perpendicular to the third direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory system. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, so too does the size of transistors. How to create DRAM with large storage capacity, small size, and high performance has become a pressing issue.

[0004] Public content

[0005] This disclosure presents a semiconductor structure, a method for fabricating the same, and a memory system.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] An active column array includes a first active column and a second active column arranged in an array along a first direction and a second direction. Each of the first active column and the second active column includes a channel region and a first active region and a second active region located at opposite ends of the channel region along a third direction, where the third direction is the direction in which the channel region extends. The first direction intersects the second direction and is perpendicular to the third direction.

[0008] A first storage structure is located on the first side of the active pillar array and is electrically connected to the first active region of the first active pillar;

[0009] The second storage structure is located on the second side of the active pillar array and is electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the third direction; the geometric center of the first active pillar projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; the first plane is perpendicular to the third direction;

[0010] The first line is located on the second side of the active column array and is connected to the second active region of the first active column;

[0011] The second bit line is located on the first side of the active pillar array and is connected to the first active region of the second active pillar; both the first bit line and the second bit line extend along the first direction.

[0012] In the above scheme, the first active column and the second active column constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the first direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column.

[0013] In the above scheme, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction;

[0014] The two first memory structures that are electrically connected to two first active columns belonging to the same column in the adjacent first row and second row of active columns have an offset from the geometric center of the projection on the second plane;

[0015] And / or,

[0016] The two second memory structures, which are electrically connected to two second active columns belonging to the same column in the adjacent first row and second row of active columns, are offset from the geometric center of the projection on the second plane; the second plane is perpendicular to the first direction.

[0017] In the above scheme, among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the multiple first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0018] And / or,

[0019] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0020] In the above scheme, the projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

[0021] In the above scheme, the projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

[0022] In the above scheme, the first bit line is connected to the second active region of the first active column arranged in the same column along the first direction;

[0023] The second bit line is connected to the first active region of the second active column arranged in the same column along the first direction.

[0024] In the above scheme, the first bit line is located between the active column array and the second memory structure, and the second bit line is located between the active column array and the first memory structure.

[0025] In the above scheme, the semiconductor structure further includes:

[0026] A first contact structure is located between the active column array and the first storage structure, and is used to electrically connect the first active region of the first active column to the first storage structure; the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active column projected onto the first plane.

[0027] The second contact structure is located between the active pillar array and the second storage structure, and is used to electrically connect the second active region of the second active pillar to the second storage structure; the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

[0028] In the above scheme, the semiconductor structure includes a dynamic random access memory, and both the first memory structure and the second memory structure include storage capacitors.

[0029] According to another aspect of this disclosure, a memory system is provided, comprising: one or more semiconductor structures as described in any of the above embodiments; and

[0030] A memory controller that is coupled to and controls the semiconductor structure.

[0031] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0032] An active column array is formed, comprising a first active column and a second active column arranged in an array along a first direction and a second direction. Each of the first and second active columns includes a channel region and a first active region and a second active region located at opposite ends of the channel region along a third direction, wherein the third direction is the direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction.

[0033] A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar.

[0034] A first bit line and a second memory structure are formed on the second side of the active pillar array, respectively; the first bit line is connected to the second active region of the first active pillar, and the second memory structure is electrically connected to the second active region of the second active pillar; the first side and the second side are opposite sides of the active pillar array along the third direction; both the first bit line and the second bit line extend along the first direction; the geometric center of the first active pillar projected onto the first plane and the geometric center of the first memory structure projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane and the geometric center of the second memory structure projected onto the first plane are offset along the second direction; the first plane is perpendicular to the third direction.

[0035] In the above scheme, the first active column and the second active column constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the first direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column.

[0036] In the above scheme, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction;

[0037] The two first memory structures that are electrically connected to two first active columns belonging to the same column in the adjacent first row and second row of active columns have an offset from the geometric center of the projection on the second plane;

[0038] And / or,

[0039] The two second memory structures, which are electrically connected to two second active columns belonging to the same column in the adjacent first row and second row of active columns, are offset from the geometric center of the projection on the second plane; the second plane is perpendicular to the first direction.

[0040] In the above scheme, among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the multiple first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0041] And / or,

[0042] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0043] In the above scheme, the projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

[0044] In the above scheme, the projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

[0045] In the above scheme, the first bit line is connected to the second active region of the first active column arranged in the same column along the first direction;

[0046] The second bit line is connected to the first active region of the second active column arranged in the same column along the first direction.

[0047] The above scheme forms the second bit line and the first storage structure, including:

[0048] A second bit line is formed on the first side of the active column array;

[0049] A first storage structure is formed on the second bit line;

[0050] Forming the first line and the second storage structure, including:

[0051] A first line is formed on the second side of the active column array;

[0052] A second storage structure is formed on the first line.

[0053] The method in the above scheme further includes:

[0054] Before forming the first storage structure, a first contact structure is formed on the first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure, and the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active pillar projected onto the first plane.

[0055] Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure, and the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

[0056] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system. The semiconductor structure fabrication method includes: forming an active pillar array, the active pillar array including first active pillars and second active pillars arranged in an array along a first direction and a second direction, each of the first and second active pillars including a channel region and first and second active regions located at opposite ends of the channel region along a third direction, the third direction being the direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction; forming a second bit line and a first memory structure on a first side of the active pillar array; the second bit line being connected to the first active region of the second active pillar, and the first memory structure being electrically connected to the first active region of the first active pillar. A first bit line and a second memory structure are formed on the second side of the active pillar array, respectively; the first bit line is connected to the second active region of the first active pillar, and the second memory structure is electrically connected to the second active region of the second active pillar; the first side and the second side are opposite sides of the active pillar array along the third direction; both the first bit line and the second bit line extend along the first direction; the geometric center of the first active pillar projected onto the first plane and the geometric center of the first memory structure projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane and the geometric center of the second memory structure projected onto the first plane are offset along the second direction; the first plane is perpendicular to the third direction. In this embodiment, a first memory structure and a second memory structure are formed on opposite sides of an active pillar array along a third direction, and a first bit line and a second bit line are formed on opposite sides of the active pillar array along a third direction. Firstly, since the first bit line and the second bit line are respectively located on opposite sides of the active pillar array along a third direction, the number of bit lines on each side is reduced. This increases the distance between adjacent first bit lines and adjacent second bit lines, reducing the parasitic capacitance between adjacent first bit lines and adjacent second bit lines, thereby improving memory performance. Secondly, since the first memory structure and the second memory structure are respectively located on opposite sides along a third direction, the area available for setting the first memory structure and the second memory structure is increased, reducing the manufacturing difficulty when forming a memory structure with a large storage capacity. Furthermore, in this embodiment, the geometric center of the first active pillar projected onto the first plane is offset from the geometric center of the first memory structure projected onto the first plane along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane is offset from the geometric center of the second memory structure projected onto the first plane along the second direction. This helps save memory area and facilitates device miniaturization. Attached Figure Description

[0057] Figure 1a This is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors in related technologies;

[0058] Figure 1b This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors in related technologies.

[0059] Figure 1c This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0060] Figure 2a This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0061] Figure 2b This is a schematic diagram of the circuit connection of a storage cell array provided in an embodiment of this disclosure;

[0062] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0063] Figures 4-21 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0064] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0065] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0066] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0067] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0068] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0069] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0070] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0071] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0072] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0073] In related technologies, the transistors of mainstream memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel array transistor, the source and drain are located on the horizontal sides of the gate in terms of their structure. Figure 1a A three-dimensional structural diagram of a semiconductor structure including planar transistors; Figure 1b This is a three-dimensional structural diagram of a semiconductor structure including a buried-channel transistor. (Example) Figure 1a and Figure 1b As shown, in the related technology, the source S and drain D of the transistor are located on opposite sides of the gate G. In this structure, the source and drain occupy different positions, resulting in a larger area for both planar transistors and buried channel transistors.

[0074] Furthermore, since transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM. Typically, DRAM consists of multiple memory cells, each primarily composed of a transistor and a capacitor controlled by the transistor; that is, DRAM has a structure of one transistor (T) and one capacitor (C) (1T1C). Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. Figure 1a and Figure 1b As shown, in a DRAM memory cell, the source (or drain) of the transistor is connected to the bit line, and the drain (or source) is connected to the capacitor. For chips formed using BCAT (Block Component Assembly), chip-on-board (COB) packaging is typically used to form the memory. Since the source and drain of planar transistors and buried channel transistors are located on opposite sides of the gate, the bit lines and capacitors in the DRAM memory cell are also located on the same side of the gate. Furthermore, subsequent processes require connections between the bit lines, transistors, and capacitors, as well as connections between word lines (WL) and transistors. This results in complex circuit routing and a high manufacturing difficulty in the DRAM memory array area.

[0075] Figure 1c This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; as shown below. Figure 1c As shown, the semiconductor structure includes a memory cell array 124, peripheral circuitry 125, and interconnects 126 connecting the memory cell array and the peripheral circuitry.

[0076] Figure 2a This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 2a As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line. The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on. Figure 2b This is a circuit connection diagram of a memory cell array provided in an embodiment of the present disclosure, as shown below. Figure 2b As shown, DRAM is equipped with row access strobe (RAS) line inputs and column access strobe (CAS) line inputs, which use the row address and column address of the memory cell to address a specific memory cell in order to read and write the cell.

[0077] As memory technology advances, the size of dynamic random access memory (DRAM) continues to shrink, making it increasingly difficult to manufacture DRAM with both large storage capacity and high performance.

[0078] In view of this, in order to solve the above problems, the present disclosure provides a method for fabricating a semiconductor structure that can form a dynamic random access memory with a large storage capacity, small size and high performance, and with relatively low process difficulty.

[0079] This disclosure also provides a method for fabricating a semiconductor structure. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 3 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0080] S100: Form an active column array, the active column array including a first active column and a second active column arranged in an array along a first direction and a second direction, each of the first active column and the second active column including a channel region and a first active region and a second active region respectively located at opposite ends of the channel region along a third direction, the third direction being the direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction;

[0081] S200: A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar;

[0082] S300: A first bit line and a second memory structure are formed on the second side of the active pillar array, respectively; the first bit line is connected to the second active region of the first active pillar, and the second memory structure is electrically connected to the second active region of the second active pillar; the first side and the second side are opposite sides of the active pillar array along the third direction; both the first bit line and the second bit line extend along the first direction; the geometric center of the first active pillar projected onto the first plane and the geometric center of the first memory structure projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane and the geometric center of the second memory structure projected onto the first plane are offset along the second direction; the first plane is perpendicular to the third direction.

[0083] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 4 to 21 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 4 to 21 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 3 , Figures 4 to 21 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0084] In step S100, the main task is to form an active column array, which includes a first active column and a second active column arranged in an array. The first active column and the second active column each include a channel region and a first active region and a second active region located at opposite ends of the channel region along a third direction, where the third direction is the direction in which the channel region extends.

[0085] In some embodiments, the first active column and the second active column constitute a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a first direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column.

[0086] In some specific examples, the method further includes forming a word line on one side of each row of active columns.

[0087] In some specific examples, the row active columns include first row active columns and second row active columns arranged alternately in a first direction; adjacent first row active columns and second row active columns constitute a row active column unit, and a dielectric layer is disposed between adjacent row active column units in the first direction;

[0088] The method further includes: forming a plurality of first gate structures and a plurality of second gate structures; wherein each first gate structure is located on the side of the first row of active pillars along the first direction away from the dielectric layer, and each second gate structure is located on the side of the second row of active pillars along the first direction away from the dielectric layer.

[0089] In some specific examples, word lines include:

[0090] A first word line is formed on the side of the first gate structure away from the first row of active pillars along the first direction.

[0091] A second word line is formed on the side of the second gate structure away from the second row of active pillars along the first direction; both the first word line and the second word line extend along the second direction.

[0092] The following is combined with Figures 4 to 7 The process of forming the active pillar array, the first word line, the second word line, the first gate structure, and the second gate structure is described in detail.

[0093] like Figure 4 as well as Figure 5 As shown, a semiconductor layer is provided, the semiconductor layer having a first surface and a second surface disposed opposite to each other in the thickness direction of the semiconductor layer, a portion of the semiconductor layer material is removed from the first surface to form a plurality of first grooves, the first grooves extending along a first direction, the first grooves dividing the semiconductor layer into a plurality of semiconductor strips 101.

[0094] here, Figure 5 It shows in Figure 4 A cross-sectional view of position AA', and Figure 4 The first insulating layer 115 is not shown.

[0095] In some specific examples, the semiconductor layer may include a substrate, which may include a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0096] In some specific examples, after forming the semiconductor strip 101, a first insulating layer 115 is filled in the first groove, the material of the first insulating layer 115 including but not limited to silicon oxide and silicon nitride.

[0097] In some specific examples, the methods for filling the first insulating layer 115 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0098] Next, as Figure 6 as well as Figure 7 As shown, a portion of the first insulating layer 115 and a portion of the semiconductor strip 101 are removed to form a plurality of second grooves. The plurality of second grooves extend along a second direction, and a first gate structure 106, a second gate structure 107, a first word line 110, and a second word line 111 are formed in the second grooves.

[0099] In some specific examples, the term "third direction" can be understood as... Figures 4-21 The Z-axis direction shown is not limited to the Z-axis direction; the second direction can be understood as... Figures 4-21 The X-axis direction shown in the diagram can be understood to mean that the second direction is not limited to the X-axis direction. The first direction can be understood as... Figures 4-21 The Y-axis direction shown in the figure can be understood to mean that the first direction is not limited to the Y-axis direction.

[0100] Here, the intersection of the second direction and the first direction can be understood as the angle between the second direction and the first direction being less than or equal to 90 degrees. In some specific examples, the angle between the second direction and the first direction is equal to 90 degrees.

[0101] In some specific examples, both the first gate structure 106 and the second gate structure 107 include a gate and a gate oxide layer. The gate material includes, but is not limited to, polysilicon, a conductive metal, or a conductive alloy; the conductive metal may include titanium, titanium nitride, molybdenum, tungsten, or copper. The gate oxide layer material includes, but is not limited to, silicon oxide. Methods for forming the gate oxide layer include, but are not limited to, PVD, CVD, and ALD processes.

[0102] Next, a portion of the first insulating layer 115 and a portion of the semiconductor strip 101 material are removed to form multiple third grooves 127 (e.g., Figure 6(as shown in the dashed box in the middle), the plurality of third grooves 127 extend along the second direction, and the second grooves and the third grooves together divide the semiconductor strip 101 into a plurality of first active pillars 102 and a plurality of second active pillars 104, with the third groove located between two adjacent rows of active pillars.

[0103] like Figure 6 as well as Figure 7 As shown, the first active regions 103 of the first active column 102 and the second active column 104 are both close to the first side, and the second active regions 105 of the first active column 102 and the second active column 104 are both close to the second side. The first active column 102 and the second active column 104 formed constitute a number of columns of active columns arranged along the second direction and a number of rows of active columns arranged along the first direction. The first active column 102 and the second active column 104 in each row of active columns are arranged alternately, and each column of active columns includes either the first active column 102 or the second active column 104. The row active pillars include alternating first row active pillars 108 and second row active pillars 109 arranged in a first direction. Adjacent first row active pillars 108 and second row active pillars 109 constitute a row active pillar unit. In subsequent process manufacturing, a dielectric layer will be filled in the third recess, so that adjacent row active pillar units in the first direction can be separated by the dielectric layer. The first gate structure 106 is located on the side of the channel region of the first row active pillar 108 along the first direction away from the dielectric layer. The second gate structure 107 is located on the side of the channel region of the second row active pillar 109 along the first direction away from the dielectric layer. The first word line 110 is formed on the side of the first gate structure 106 along the first direction away from the channel region of the first row active pillar 108. The second word line 111 is formed on the side of the second gate structure 107 along the first direction away from the channel region of the second row active pillar 109. Both the first word line 110 and the second word line 111 extend along the second direction.

[0104] here, Figure 7 It shows in Figure 6 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, and the second word line 111. Figure 6 The top view shown is a perspective view, and the first insulating layer 115 is omitted.

[0105] It should be noted that, Figure 6 as well as Figure 7 The first active post 102 and the second active post 104 shown are arranged alternately in the second direction, but Figure 6 as well as Figure 7This is merely an example of the arrangement of the first active column 102 and the second active column 104, and is not intended to limit the arrangement of the first active column 102 and the second active column 104 in the embodiments of this disclosure.

[0106] In some specific examples, the methods for forming the first groove, the second groove, and the third groove include, but are not limited to, dry plasma etching processes.

[0107] Next, a dielectric layer is formed in the third groove. In some specific examples, cavities are formed in the dielectric layer to isolate adjacent transistors and reduce mutual interference. In other specific examples, a metal shielding layer may be buried in the dielectric layer, and a fixed voltage is applied to the metal shielding layer to reduce mutual interference between adjacent transistors.

[0108] In some specific examples, after the first active pillar 102 and the second active pillar 104 are formed, a first active region 103 and a second active region 105 can be formed at both ends of the first active pillar 102 and the second active pillar 104 along the thickness direction of the semiconductor layer.

[0109] In some specific examples, the active pillars between the first active region 103 and the second active region 105 constitute the channel region of the transistor, and the gate oxide layer is located between the gate and the channel region to electrically isolate the channel region and the gate and reduce the hot carrier effect of the transistor.

[0110] Here, the first active region 103 can be the source or drain of a transistor, and the second active region 105 can also be the source or drain of a transistor. For example, the first active region 103 of the first active pillar 102 can be the source, and the second active region 105 of the first active pillar 102 can be the drain; the first active region 103 of the second active pillar 104 can be the drain, and the second active region 105 of the second active pillar 104 can be the source.

[0111] In some specific examples, the methods for forming the first active region 103 and the second active region 105 include, but are not limited to, doping processes and diffusion processes. In some specific examples, the formed semiconductor structure can be an N-type transistor or a P-type transistor.

[0112] In an N-type transistor, both the source and drain are doped with N-type doping; in a P-type transistor, both the source and drain are doped with P-type doping. For example, when the doping type is P-type, the P-type impurity source can be boron (B), aluminum (Al), etc., and is not limited to these; when the doping type is N-type, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and is not limited to these.

[0113] It should be noted that the above embodiments exemplify ways in which word lines and gate structures are formed, but the formation of word lines and gate structures is not limited thereto. In other specific examples, the gate structure surrounds the active pillar, and the word line surrounds the gate isolation structure.

[0114] In step S200, the main task is to form the first memory structure and the second bit line.

[0115] In some embodiments, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction;

[0116] The two first memory structures that are electrically connected to two first active columns belonging to the same column in the adjacent first row and second row of active columns have an offset from the geometric center of the projection on the second plane.

[0117] In some embodiments, among the plurality of first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the plurality of first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle.

[0118] In some embodiments, the second bit line is connected to the first active region of the second active pillars in the same column arranged along the first direction.

[0119] In some embodiments, forming a second bit line and a first storage structure includes:

[0120] A second bit line is formed on the first side of the active column array;

[0121] The first storage structure is formed on the second bit line.

[0122] In some embodiments, the method further includes:

[0123] Before forming the first storage structure, a first contact structure is formed on a first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure, and the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active pillar projected onto the first plane.

[0124] The following is combined with Figures 8 to 12 The specific process of forming the first memory structure and the second bit line is described in detail.

[0125] like Figure 8 as well as Figure 9As shown, a second bit line 113 is formed on the first side of the active pillar array, i.e., on the first surface of the semiconductor layer. The second bit line 113 extends along a first direction and is connected to the first active region 103 of the second active pillar 104. In some specific examples, the bit line can be formed by forming a metal line at a predetermined bit line location. The metal line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0126] It is understandable that the second active pillar 104 in the same column of active pillars shares the same second bit line 113, and the first active pillar 102 and the second active pillar 104 are arranged alternately in the second direction. The first bit line 112 of the first active pillar 102 will be set on the second side of the active pillar array in subsequent processes. Each second bit line 113 will form a first contact structure 120 in subsequent processes. The distance between adjacent second bit lines 113 is large, so the parasitic capacitance between adjacent second bit lines 113 is small. Similarly, the distance between adjacent first bit lines 112 formed in subsequent processes is large, so the parasitic capacitance between first bit lines 112 is small. This can improve the performance of the memory.

[0127] here, Figure 9 It shows in Figure 8 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, and the second bit line 113. Figure 8 The top view shown is a perspective view, and the first insulating layer 115 and the dielectric layer are omitted.

[0128] Here, the first side of the active column array and the second side of the active column array below are the two sides of the active column array that are set opposite each other along a third direction.

[0129] It is understood that the bit line BL is used to perform read or write operations on the transistor and the connected memory structure when the transistor is turned on.

[0130] Next, as Figure 10 As shown, a second insulating layer 116 is formed on the active pillar array, the second bit line 113 is located in the second insulating layer 116, and a first contact structure 120 is formed in the second insulating layer 116. The first contact structure 120 is used to electrically connect the first active region 103 of the first active pillar 102 to the first memory structure 122 formed in a subsequent process.

[0131] Here, connection and electrical connection can be understood as follows: connection refers to two parts being physically contacted and thus directly connected, while electrical connection refers to two parts being indirectly connected through other parts.

[0132] Here, the geometric center of the first contact structure 120 projected onto the first plane overlaps with the geometric center of the first active column 102 projected onto the first plane.

[0133] It should be noted that the overlap in the embodiments of this disclosure refers to the overlap that is designed in the design, and the deviation caused by the process is ignored in the embodiments of this disclosure.

[0134] In some specific examples, the process of forming the first contact structure 120 includes: forming a contact hole in the second insulating layer 116, and filling the contact hole with a conductive material to form the first contact structure 120.

[0135] In some specific examples, the material of the second insulating layer 116 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the second insulating layer 116 include, but are not limited to, PVD, CVD, and ALD.

[0136] Next, as Figure 11 as well as Figure 12 As shown, a third insulating layer 117 is formed on the second insulating layer 116, and a first storage structure 122 is formed in the third insulating layer 117. The first storage structure 122 is electrically connected to the first active region 103 of the first active post 102 through the first contact structure 120.

[0137] here, Figure 12 It shows in Figure 11 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, and the first memory structure 122. Figure 11 The top view shown is a perspective view, and some structures are omitted.

[0138] In some specific examples, the material of the third insulating layer 117 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the third insulating layer 117 include, but are not limited to, PVD, CVD, and ALD.

[0139] like Figure 11 as well as Figure 12 As shown, the geometric center of the first active column 102 projected onto the first plane is offset from the geometric center of the first storage structure 122 projected onto the first plane along the second direction; the first plane is perpendicular to the third direction.

[0140] It should be noted that the offset in the embodiments of this disclosure refers to the offset designed during the design phase, while offsets caused by process factors are not within the scope of protection of the embodiments of this disclosure.

[0141] Here, since the geometric center of the first contact structure 120 projected onto the first plane overlaps with the geometric center of the first active column 102 projected onto the first plane, the geometric center of the first contact structure 120 projected onto the first plane and the geometric center of the first storage structure 122 projected onto the first plane are offset along the second direction.

[0142] Here, the first storage structure 122 electrically connected to two first active columns 102 belonging to the same column of the adjacent first row active columns 108 and second row active columns 109 is offset from the geometric center of its projection onto the second plane; the second plane is perpendicular to the first direction. That is, the offset directions of the first storage structure 122 electrically connected to the first row active columns 108 and the first storage structure 122 electrically connected to the second row active columns 109 are opposite. Figure 11 As shown, the two first storage structures 122 enclosed by the dashed box are active columns of the same column of active columns. The geometric centers of the first storage structures 122 electrically connected to the first row of active columns 108 are all offset along the negative X-axis direction of the geometric center of the first active column in the first plane projection. The geometric centers of the first storage structures 122 electrically connected to the second row of active columns 109 are all offset along the positive X-axis direction of the geometric center of the first active column in the first plane projection.

[0143] It is understandable that the offset directions of the first memory structure 122 electrically connected to the first row of active pillars 108 and the first memory structure 122 electrically connected to the second row of active pillars 109 are opposite. This makes the distance between the first memory structure 122 electrically connected to the first row of active pillars 108 and the first memory structure 122 electrically connected to the second row of active pillars 109 larger. When forming a semiconductor structure with the same storage capacity, the size of the semiconductor structure in the first direction is reduced, thereby reducing the area of ​​the semiconductor structure and facilitating the miniaturization of devices.

[0144] like Figure 11 As shown, among the plurality of first storage structures 122 electrically connected to the first row of active columns 108, the geometric centers of two adjacent first storage structures 122 projected onto the first plane are C1 and C2, respectively; among the plurality of first storage structures 122 electrically connected to the second row of active columns 109 adjacent to the first row of active columns 108, the geometric center of the first storage structure 122 with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle.

[0145] It is understandable that when the lines connecting C1, C2, and C3 form an equilateral triangle, the first memory structure is more evenly distributed, which results in a larger area utilization rate for the semiconductor structure.

[0146] In some specific examples, forming the first storage structure 122 may include the following steps: forming a storage structure hole on the first contact structure 120; forming the first storage structure 122 in the storage structure hole, for example, forming a storage capacitor.

[0147] In some specific examples, the storage capacitor can present various structures. For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). Each of these capacitors includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom and top electrodes.

[0148] In some specific examples, the bottom electrode is electrically connected to the first active region 103 of the first active post 102, the top electrode of the cup-shaped capacitor CUP can be connected to 1 / 2 Vcc, and the bottom electrode of the cup-shaped capacitor CUP can be used to store the written data.

[0149] It should be noted that, when the bottom electrode areas of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode area of ​​the cylindrical capacitor (CYL) is the largest, followed by the cup-shaped capacitor (CUP) and the pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for improving the integration density of the memory.

[0150] It is understandable that a first memory structure 122 is formed on the first side of the active pillar array, and a second memory structure 123 is formed on the second side of the active pillar array in a subsequent process. The first memory structure 122 is connected to the first active region 103 of the first active pillar 102, and the second memory structure 123 is connected to the second active region 105 of the second active pillar 104. The first active pillar 102 and the second active pillar 104 are arranged alternately in the second direction, and the first active regions 103 of the first active pillar 102 and the second active regions 105 of the first active pillar 102 and the second active pillar 104 are all located on the same side. This allows the area occupied by the first memory structure 122 and the second memory structure 123 to increase while keeping the overall memory area unchanged. On the one hand, this reduces the process difficulty of forming the first memory structure 122 and the second memory structure 123 with larger storage capacity. On the other hand, it allows the formation of the first memory structure 122 and the second memory structure 123 with even larger storage capacity.

[0151] In step S300, the main task is to form the first bit line and the second storage structure.

[0152] In some embodiments, two second storage structures electrically connected to two second active columns belonging to the same column in the adjacent first row of active columns and second row of active columns are offset from the geometric center of the projection of the second plane; the second plane is perpendicular to the first direction.

[0153] In some embodiments, among the plurality of second memory structures electrically connected to the first row of active pillars, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the plurality of second memory structures electrically connected to the second row of active pillars adjacent to the first row of active pillars, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0154] In some embodiments, the projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

[0155] In some embodiments, the projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

[0156] In some embodiments, the first bit line is connected to the second active region of the first active column arranged in the same column along the first direction.

[0157] In some embodiments, forming a first line and a second storage structure includes:

[0158] A first line is formed on the second side of the active column array;

[0159] A second storage structure is formed on the first line.

[0160] In some embodiments, the method further includes:

[0161] Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure, and the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

[0162] The following is combined with Figures 13 to 21 The formation process of the first line and the second memory structure is described in detail.

[0163] In some specific examples, such as Figure 13 As shown, the method further includes: bonding a carrier layer 114 to a first side of the first storage structure 122, wherein the material of the carrier layer 114 includes, but is not limited to, silicon oxide.

[0164] It is understandable that in subsequent processes, process operations need to be performed on the second side of the active pillar array, that is, the second side of the semiconductor layer. The semiconductor layer needs to be flipped so that the first memory structure 122 is placed underneath. The carrier layer 114 can protect the first memory structure 122, the second bit line 113, and the first contact structure 120 to prevent them from being damaged in subsequent processes.

[0165] like Figure 14 As shown, the second side of the semiconductor layer is thinned to expose the second active region 105 of the first active pillar 102 and the second active pillar 104.

[0166] In some specific examples, the thinning process of the second side of the semiconductor layer includes, but is not limited to, chemical mechanical polishing (CMP) and etching processes.

[0167] Next, as Figure 15 as well as Figure 16 As shown, a first line 112 is formed on the second surface, extending along a first direction, and connected to the second active region 105 of the first active pillar 102. Here, Figure 16 It shows in Figure 15 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, the first memory structure 122, and the first bit line 112. Figure 15 The top view shown is a perspective view, and some structures are omitted.

[0168] Next, as Figure 17 As shown, a fourth insulating layer 118 is formed on the second surface, the first line 112 is located in the fourth insulating layer 118, and a second contact structure 121 is formed in the fourth insulating layer 118. The second contact structure 121 is used to electrically connect the second active region 105 of the second active post 104 to the second storage structure 123 formed in a subsequent process.

[0169] Here, the geometric center of the second contact structure 121 projected onto the first plane overlaps with the geometric center of the second active column 104 projected onto the first plane.

[0170] In some specific examples, the material of the fourth insulating layer 118 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the fourth insulating layer 118 include, but are not limited to, PVD, CVD, and ALD.

[0171] Next, as Figure 18 as well as Figure 19 As shown, a fifth insulating layer 119 is formed on the fourth insulating layer 118, and a second storage structure 123 is formed in the fifth insulating layer 119. The second storage structure 123 is electrically connected to the second active region 105 of the second active post 104 through the second contact structure 121.

[0172] here, Figure 19 It shows in Figure 18 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, the first memory structure 122, the first bit line 112, and the second memory structure 123. Figure 18 The top view shown is a perspective view, and some structures are omitted.

[0173] In some specific examples, the material of the fifth insulating layer 119 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the third insulating layer 117 include, but are not limited to, PVD, CVD, and ALD.

[0174] The second storage structure 123 is similar to the first storage structure 122 in structure and manufacturing method, and will not be described in detail here.

[0175] like Figure 18 as well as Figure 19 As shown, the geometric center of the second active column 104 projected onto the first plane is offset from the geometric center of the second storage structure 123 projected onto the first plane along the second direction.

[0176] Here, since the geometric center of the second contact structure 121 projected onto the first plane overlaps with the geometric center of the second active column 104 projected onto the first plane, the geometric center of the second contact structure 121 projected onto the first plane and the geometric center of the second storage structure 123 projected onto the first plane are offset along the second direction.

[0177] Here, the two second storage structures 123 electrically connected to two second active columns 104 belonging to the same column of the adjacent first row active columns 108 and second row active columns 109 are offset from the geometric center of the second plane projection. That is, the offset directions of the second storage structure 123 electrically connected to the first row active column 108 and the second storage structure 123 electrically connected to the second row active column 109 are opposite.

[0178] like Figure 18As shown, the two second storage structures 123 enclosed by the dashed box are active columns of the same column of active columns. The geometric centers of the second storage structures 123 electrically connected to the first row of active columns 108 are all offset along the negative X-axis direction of the geometric center of the second active column in the first plane projection. The geometric centers of the second storage structures 123 electrically connected to the second row of active columns 109 are all offset along the positive X-axis direction of the geometric center of the second active column in the first plane projection.

[0179] It is understandable that the offset directions of the second memory structure electrically connected to the first row of active pillars and the second memory structure electrically connected to the second row of active pillars are different. This results in a larger distance between the second memory structure electrically connected to the first row of active pillars and the second memory structure electrically connected to the second row of active pillars. When forming a semiconductor structure with the same storage capacity, the size of the semiconductor structure in the first direction is reduced, thereby reducing the area of ​​the semiconductor structure and facilitating the miniaturization of devices.

[0180] In some specific examples, the projection portions of the first storage structure 122 and the second storage structure 123 onto the first plane overlap. For example... Figure 18 as well as Figure 19 As shown, the first and second memory structures, which are electrically connected to the active columns in the same row, are offset in the same direction, for example, as shown in the figure. Figure 18 as well as Figure 19 As shown, the first storage structure 122 and the second storage structure 123, which are electrically connected to the first row of active columns 108, are both offset along the negative X-axis direction, so that the projection portions of the first storage structure 122 and the second storage structure 123 on the first plane overlap.

[0181] In other specific examples, the projections of the first storage structure 122 and the second storage structure 123 onto the first plane overlap. For example... Figure 20 as well as Figure 21 As shown, the first memory structure 122 and the second memory structure 123, which are electrically connected to the active columns in the same row, are offset in opposite directions, as exemplarily as... Figure 20 as well as Figure 21 As shown, the first storage structure 122, which is electrically connected to the first row of active pillars 108, is offset along the negative X-axis direction, and the second storage structure 123, which is electrically connected to the first row of active pillars 108, is offset along the positive X-axis direction, so that the projections of the first storage structure 122 and the second storage structure 123 on the first plane overlap.

[0182] like Figure 18As shown, among the multiple second storage structures 123 electrically connected to the first row of active columns, the geometric centers of two adjacent second storage structures 123 projected onto the first plane are C4 and C5, respectively; among the multiple second storage structures 123 electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second storage structure 123 with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0183] It is understandable that when the lines connecting C4, C5, and C6 form an equilateral triangle, the second memory structure is more evenly distributed, which results in a larger area utilization rate for the semiconductor structure.

[0184] In some specific examples, the ratio of (pitch of active pin)2:(pitch of word line)2:(pitch of bit line)2 is 1:3:4.

[0185] Here, the pitch of an active column can be understood as the distance between the geometric centers of the first and second adjacent active columns in the same row. The pitch of a word line can be understood as half the distance between the geometric centers of two adjacent first word lines, or half the distance between the geometric centers of two adjacent second word lines. The pitch of a bit line can be understood as the distance between the geometric centers of adjacent first bit lines or the distance between the geometric centers of adjacent second bit lines.

[0186] It should be noted that the values ​​of (active column pitch)2:(word line pitch)2:(bit line pitch)2 given in the above embodiments are merely exemplary demonstrations and are not intended to limit the values ​​of (active column pitch)2:(word line pitch)2:(bit line pitch)2 in this disclosure.

[0187] In some specific examples, the semiconductor structure includes a dynamic random access memory, and both the first memory structure 122 and the second memory structure 123 include storage capacitors.

[0188] This disclosure provides a method for fabricating a semiconductor structure, comprising: forming an active pillar array, the active pillar array including first active pillars 102 and second active pillars 104 arranged in an array along a first direction and a second direction, each of the first active pillars 102 and the second active pillars 104 including a channel region and a first active region 103 and a second active region 105 respectively located at opposite ends of the channel region along a third direction, the third direction being the direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction; forming a second bit line 113 and a first memory structure 122 on a first side of the active pillar array; the second bit line 113 being connected to the first active region 103 of the second active pillar 104, and the first memory structure 122 being electrically connected to the first active region 103 of the first active pillar 102; forming a second bit line 113 and a first memory structure 122 on a first side of the active pillar array; and forming a second bit line 113 and a first memory structure 122 on a first side of the active pillar array. The second side of the column array forms a first bit line 112 and a second storage structure 123, respectively; the first bit line 112 is connected to the second active region 105 of the first active column 102, and the second storage structure 123 is electrically connected to the second active region 105 of the second active column 104; the first side and the second side are opposite sides of the active column array along the third direction; both the first bit line and the second bit line extend along the first direction; the geometric center of the first active column 102 projected onto the first plane and the geometric center of the first storage structure 122 projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active column 104 projected onto the first plane and the geometric center of the second storage structure 123 projected onto the first plane are offset along the second direction; the first plane is perpendicular to the third direction.In this embodiment, a first memory structure 122 and a second memory structure 123 are formed on opposite sides of an active peg array along a third direction, and a first bit line 112 and a second bit line 113 are formed on opposite sides of the active peg array along a third direction. Firstly, since the first bit line 112 and the second bit line 113 are respectively located on opposite sides of the active peg array along a third direction, the number of bit lines on each side is reduced. This increases the distance between adjacent first bit lines 112 and adjacent second bit lines 113, thereby reducing the parasitic capacitance between adjacent first bit lines 112 and adjacent second bit lines 113, thus improving memory performance. Secondly, since the first memory structure 122... The first storage structure 122 and the second storage structure 123 are respectively disposed on opposite sides along a third direction, which increases the area available for setting the first storage structure 122 and the second storage structure 123, thereby reducing the manufacturing difficulty when forming a storage structure with a large storage capacity. In addition, in this embodiment of the present disclosure, the geometric center of the first active pillar 102 projected onto the first plane is offset from the geometric center of the first storage structure 122 projected onto the first plane along the second direction; and / or, the geometric center of the second active pillar 104 projected onto the first plane is offset from the geometric center of the second storage structure 123 projected onto the first plane along the second direction. This is beneficial for saving memory area and for device miniaturization.

[0189] According to another aspect of this disclosure, embodiments of this disclosure also provide a semiconductor structure, including: an active pillar array, comprising first active pillars and second active pillars arranged in an array along a first direction and a second direction, each of the first and second active pillars including a channel region and first and second active regions respectively located at opposite ends of the channel region along a third direction, the third direction being the direction in which the channel region extends; the first direction intersects the second direction and is perpendicular to the third direction; a first memory structure located on a first side of the active pillar array and electrically connected to a first active region of the first active pillars; a second memory structure located on a second side of the active pillar array and electrically connected to a second active region of the second active pillars; the first side is... The second side is the two sides opposite to each other of the active column array along the third direction; the geometric center of the first active column projected onto the first plane and the geometric center of the first storage structure projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active column projected onto the first plane and the geometric center of the second storage structure projected onto the first plane are offset along the second direction; the first plane is perpendicular to the third direction; the first bit line is located on the second side of the active column array and is connected to the second active region of the first active column; the second bit line is located on the first side of the active column array and is connected to the first active region of the second active column; both the first bit line and the second bit line extend along the first direction.

[0190] The semiconductor structures provided in this disclosure include various types of memory, such as NAND flash memory, Nor flash memory, DRAM, static random access memory (SRAM), and phase-change memory (PCM).

[0191] In some embodiments, the semiconductor structure includes a dynamic random access memory, and both the first and second memory structures include storage capacitors.

[0192] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory containing the semiconductor structure provided in the embodiments of this disclosure falls within the scope of protection of this invention.

[0193] In some embodiments, the first active column and the second active column constitute a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a first direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column.

[0194] In some embodiments, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction;

[0195] The two first memory structures that are electrically connected to two first active columns belonging to the same column in the adjacent first row and second row of active columns have an offset from the geometric center of the projection on the second plane;

[0196] And / or,

[0197] The two second memory structures, which are electrically connected to two second active columns belonging to the same column in the adjacent first row and second row of active columns, are offset from the geometric center of the projection on the second plane; the second plane is perpendicular to the first direction.

[0198] In some embodiments, among the plurality of first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the plurality of first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0199] And / or,

[0200] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0201] In some embodiments, the projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

[0202] In some embodiments, the projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

[0203] In some embodiments, the first bit line is connected to the second active regions of the first active pillars in the same column arranged along the first direction;

[0204] The second bit line is connected to the first active region of the second active column arranged in the same column along the first direction.

[0205] In some embodiments, the first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

[0206] In some embodiments, the semiconductor structure further includes:

[0207] A first contact structure is located between the active column array and the first storage structure, and is used to electrically connect the first active region of the first active column to the first storage structure; the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active column projected onto the first plane.

[0208] The second contact structure is located between the active pillar array and the second storage structure, and is used to electrically connect the second active region of the second active pillar to the second storage structure; the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

[0209] In some specific examples, the semiconductor structure also includes word lines; the word lines are located on one side of each row of active pillars.

[0210] In some specific examples, the row active columns include first row active columns and second row active columns arranged alternately in a first direction; adjacent first row active columns and second row active columns constitute a row active column unit, and a dielectric layer is disposed between adjacent row active column units in the first direction;

[0211] The semiconductor structure further includes: a plurality of first gate structures and a plurality of second gate structures; wherein each first gate structure is located on the side of the first row of active pillars along the first direction away from the dielectric layer, and each second gate structure is located on the side of the second row of active pillars along the first direction away from the dielectric layer.

[0212] In some specific examples, the character line includes: a first character line and a second character line; both the first character line and the second character line extend along the second direction;

[0213] The first word line is located on the side of the first gate structure along the first direction that is away from the first row of active pillars;

[0214] The second word line is located on the side of the second gate structure along the first direction that is away from the second row of active pillars.

[0215] The semiconductor structure provided in the above embodiments has been described in detail in the method section and will not be repeated here.

[0216] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:

[0217] One or more semiconductor structures as described in the above embodiments; and

[0218] A memory controller that is coupled to and controls the semiconductor structure.

[0219] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.

[0220] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0221] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0222] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: An active column array includes first and second active columns arranged in an array along a first direction and a second direction. Each of the first and second active columns includes a channel region and first and second active regions located at opposite ends of the channel region along a third direction, where the third direction is the direction in which the channel region extends. The first and second active columns constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the first direction. Each row of active columns includes alternating first and second active columns, and each column of active columns includes either a first or a second active column. The first direction intersects the second direction and is perpendicular to the third direction. A first storage structure is located on the first side of the active pillar array and is electrically connected to the first active region of the first active pillar; The second storage structure is located on the second side of the active pillar array and is electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the third direction; The geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; And / or, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; The first plane is perpendicular to the third direction; the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction; two first memory structures electrically connected to two first active columns belonging to the same column in adjacent first and second row active columns are offset from the geometric center of the projection on the second plane; and / or, two second memory structures electrically connected to two second active columns belonging to the same column in adjacent first and second row active columns are offset from the geometric center of the projection on the second plane; The second plane is perpendicular to the first direction; The first line is located on the second side of the active column array and is connected to the second active region of the first active column; The second bit line is located on the first side of the active pillar array and is connected to the first active region of the second active pillar; both the first bit line and the second bit line extend along the first direction.

2. The semiconductor structure according to claim 1, characterized in that, Among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively. Among the multiple first memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the first memory structure with the smallest sum of distances to C1 and C2 has C3 as its geometric center in the projection of the first plane, and the line connecting C1, C2, and C3 forms an equilateral triangle. And / or, Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively. Among the multiple second memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the second memory structure with the smallest sum of distances to C4 and C5 has C6 as its geometric center when projected onto the first plane, and the line connecting C4, C5, and C6 forms an equilateral triangle.

3. The semiconductor structure according to claim 1, characterized in that, The projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

4. The semiconductor structure according to claim 1, characterized in that, The projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

5. The semiconductor structure according to claim 1, characterized in that, The first bit line is connected to the second active region of the first active column in the same column arranged along the first direction; The second bit line is connected to the first active region of the second active column arranged in the same column along the first direction.

6. The semiconductor structure according to claim 1, characterized in that, The first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first contact structure is located between the active column array and the first storage structure, and is used to electrically connect the first active region of the first active column to the first storage structure; the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active column projected onto the first plane. The second contact structure is located between the active pillar array and the second storage structure, and is used to electrically connect the second active region of the second active pillar to the second storage structure; the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a dynamic random access memory, and both the first and second memory structures include storage capacitors.

9. A memory system, characterized in that, include: One or more semiconductor structures as described in any one of claims 1-8; as well as A memory controller that is coupled to and controls the semiconductor structure.

10. A method for fabricating a semiconductor structure, characterized in that, The method includes: An active column array is formed, comprising first and second active columns arranged in an array along a first direction and a second direction. Each of the first and second active columns includes a channel region and first and second active regions located at opposite ends of the channel region along a third direction, where the third direction is the direction in which the channel region extends. The first and second active columns constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the first direction. Each row of active columns includes alternating first and second active columns, and each column of active columns includes either a first or a second active column. The first direction intersects the second direction and is perpendicular to the third direction. A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar. A first bit line and a second memory structure are formed on the second side of the active pillar array, respectively; the first bit line is connected to the second active region of the first active pillar, and the second memory structure is electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the third direction; both the first bit line and the second bit line extend along the first direction; the geometric center of the first active pillar projected onto the first plane and the geometric center of the first memory structure projected onto the first plane are offset along the second direction; and / or, the geometric center of the second active pillar projected onto the first plane and the second memory structure are offset along the second direction. The geometric center of the projection of the first plane is offset along the second direction; the first plane is perpendicular to the third direction; the row active columns include a first row of active columns and a second row of active columns arranged alternately in the first direction; two first memory structures electrically connected to two first active columns belonging to the same column of adjacent first and second row active columns are offset at the geometric center of the projection of the second plane; and / or, two second memory structures electrically connected to two second active columns belonging to the same column of adjacent first and second row active columns are offset at the geometric center of the projection of the second plane; the second plane is perpendicular to the first direction.

11. The manufacturing method according to claim 10, characterized in that, Among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively. Among the multiple first memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the first memory structure with the smallest sum of distances to C1 and C2 has C3 as its geometric center in the projection of the first plane, and the line connecting C1, C2, and C3 forms an equilateral triangle. And / or, Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively. Among the multiple second memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the second memory structure with the smallest sum of distances to C4 and C5 has C6 as its geometric center when projected onto the first plane, and the line connecting C4, C5, and C6 forms an equilateral triangle.

12. The manufacturing method according to claim 10, characterized in that, The projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

13. The manufacturing method according to claim 10, characterized in that, The projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

14. The manufacturing method according to claim 10, characterized in that, The first bit line is connected to the second active region of the first active column in the same column arranged along the first direction; The second bit line is connected to the first active region of the second active column arranged in the same column along the first direction.

15. The manufacturing method according to claim 10, characterized in that, Forming the second bit line and the first storage structure includes: A second bit line is formed on the first side of the active column array; A first storage structure is formed on the second bit line; Forming the first line and the second storage structure, including: A first line is formed on the second side of the active column array; A second storage structure is formed on the first line.

16. The manufacturing method according to claim 10, characterized in that, The method further includes: Before forming the first storage structure, a first contact structure is formed on the first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure, and the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active pillar projected onto the first plane. Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure, and the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active pillar projected onto the first plane.

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