Semiconductor memory device and method for manufacturing semiconductor memory device
By employing a multi-layer alternating structure and columnar design in NAND flash memory, the problem of insufficient electrical characteristics of three-dimensional stacked memory cells is solved, thereby improving the electrical characteristics and reliability of the memory cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2022-02-18
- Publication Date
- 2026-07-21
Smart Images
Figure CN115835638B_ABST
Abstract
Description
[0001] [Related Applications]
[0002] This application enjoys priority to Japanese Patent Application No. 2021-152049 (filed on September 17, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field
[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology
[0004] NAND flash memory, which is formed by stacking storage cells in three dimensions, is well known. Summary of the Invention
[0005] The present invention provides a semiconductor memory device with improved electrical characteristics and a method for manufacturing the semiconductor memory device.
[0006] The semiconductor memory device of the embodiment includes: a stacked body comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are stacked alternately in a first direction; a columnar body extending in the stacked body along the first direction and comprising: an insulating core, a channel layer located between the plurality of gate electrode layers and the insulating core, and a memory film located between the plurality of gate electrode layers and the channel layer; and a bit line disposed on one side of the stacked body in the first direction; wherein the plurality of gate electrode layers include: a plurality of first gate electrode layers, wherein memory cell transistors are formed at the intersections with the channel layers; and one or more The second gate electrode layer, with the bit line side set to the top, is located above the plurality of first gate electrode layers and forms a selection transistor at the intersection with the channel layer; the channel layer includes: a first portion located between the uppermost first gate electrode layer and the insulating core; and a second portion extending from above the upper end of the uppermost second gate electrode layer of the plurality of second gate electrode layers to at least the same height as the lower end of the uppermost second gate electrode layer; the film thickness of the second portion in a second direction intersecting the first direction is greater than the film thickness of the first portion in the second direction. Attached Figure Description
[0007] Figure 1 This is a block diagram showing a portion of the configuration of the semiconductor memory device according to the first embodiment.
[0008] Figure 2 This is a diagram showing an equivalent circuit of a portion of the memory cell array in the first embodiment.
[0009] Figure 3 This is a perspective cross-sectional view showing a portion of the memory cell array of the first embodiment.
[0010] Figure 4 This is a cross-sectional view showing a portion of the storage cell array of the first embodiment.
[0011] Figure 5 It is along Figure 4 The cross-sectional view of the memory cell array shown along line F5-F5.
[0012] Figure 6 (a) to (c) are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment.
[0013] Figure 7 (d) to (f) are cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.
[0014] Figure 8 (g) to (i) are cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.
[0015] Figure 9 (j) to (l) are cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.
[0016] Figure 10 (m) and (n) are cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.
[0017] Figure 11 (e'), (f'), and (g') are cross-sectional views used to illustrate variations of the manufacturing method of the first embodiment.
[0018] Figure 12 (h'), (i'), and (k') are cross-sectional views used to illustrate variations of the manufacturing method of the first embodiment.
[0019] Figure 13 This is a cross-sectional view showing a portion of the storage cell array in the second embodiment.
[0020] Figure 14 This is a cross-sectional view showing a portion of the storage cell array in the third embodiment. Detailed Implementation
[0021] Hereinafter, a semiconductor memory device according to an embodiment and a method for manufacturing a semiconductor memory device will be described with reference to the drawings. In the following description, components having the same or similar functions are marked with the same symbols. Moreover, repeated descriptions of these components may sometimes be omitted. In the following description, components marked with reference symbols ending with numbers or letters for distinction may sometimes omit the numbers or letters at the end when they are not mutually distinguishable.
[0022] "Parallel," "orthogonal," or "identical" can respectively include cases of "approximately parallel," "approximately orthogonal," or "approximately identical." "Connection" is not limited to mechanical connections but can also include electrical connections. That is, "connection" is not limited to the direct connection of multiple elements but can include the connection of multiple elements through other elements. "Ring-shaped" is not limited to circular rings but can include rectangular or triangular rings. "Adjacent" is not limited to the connection of multiple elements but can include the separation of multiple elements (e.g., the connection of multiple elements through other elements).
[0023] First, the X, Y, Z, and R directions are defined. The X and Y directions are along the surface of the silicon substrate 21 described below (refer to...). Figure 3 The X direction is the direction of the letter line WL (see reference). Figure 3 The Y direction extends in the direction that intersects (e.g., is orthogonal) the X direction. The Y direction is the bit line BL described below (refer to...). Figure 3 The Z-direction extends in the direction of the X and Y directions. The Z-direction is the direction that intersects (e.g., is orthogonal) the X and Y directions. The Z-direction is the thickness direction of the silicon substrate 21. In the following description, the direction from the silicon substrate 21 toward the stack 30 described below is sometimes referred to as "up," and its opposite direction as "down." However, these expressions are provisional and do not specify the direction of gravity. The R-direction is the columnar structure 40 described below (see...). Figure 4 The radial direction of the direction. The R direction is a direction along the plane of the X and Y directions, and is a direction that intersects (e.g., is orthogonal) the Z direction. The Z direction is an example of the "first direction". The R direction is an example of the "second direction".
[0024] (First Embodiment)
[0025] <1. Composition of Semiconductor Memory Devices>
[0026] First, the configuration of the semiconductor memory device 1 according to the first embodiment will be described. In the following description, the illustrations of insulating parts that are not related to the description may be omitted. In some of the illustrations, the shading lines representing cross-sections may be partially omitted for ease of observation.
[0027] Figure 1This is a block diagram showing a portion of the configuration of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device, specifically a NAND flash memory. The semiconductor memory device 1 can, for example, be connected to an external device (hereinafter referred to as a "host device") and used as storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.
[0028] The memory cell array 11 contains multiple blocks BLK0 to BLK(k-1) (where k is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors that non-volatilely store data. Blocks BLK are used as units for data erasure. The memory cell array 11 includes multiple bit lines and multiple word lines. Each memory cell transistor is associated with one bit line and one word line.
[0029] Instruction register 12 stores instructions (CMD) received by semiconductor memory device 1 from host device. Instructions (CMD) may include commands such as causing control circuitry 14 to perform write, read, or erase operations on memory cell array 11.
[0030] Address register 13 stores address information ADD received by semiconductor memory device 1 from the host device. Address information ADD includes, for example, block address BA, page address PA, and column address CA. Block address BA, page address PA, and column address CA are used to select block BLK, word line, and bit line, respectively.
[0031] The control circuit 14 is a circuit that controls the operation of the semiconductor memory device 1. For example, the control circuit 14 controls the driver module 15, the line decoder module 16, and the sense amplifier module 17, etc., to perform write operations, read operations, and erase operations on the memory cell array 11 according to the instruction CMD stored in the instruction register 12.
[0032] Driver module 15 includes voltage generation circuitry that generates voltages used in write operations, read operations, or erase operations. For example, driver module 15 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PA stored in address register 13.
[0033] The row decoder module 16 selects one block BLK in the corresponding memory cell array 11 based on the block address BA stored in the address register 13. The row decoder module 16, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.
[0034] During the write operation, the sensing amplifier module 17 applies the required voltage to each bit line according to the write data DAT received by the semiconductor memory device 1 from the host device. During the read operation, the sensing amplifier module 17 determines the data value stored in each memory cell according to the voltage of the bit line, and transmits the determination result as read data DAT to the host device.
[0035] <2. Composition of Memory Cell Array>
[0036] <2.1 Electrical Configuration of Memory Cell Array>
[0037] Next, the electrical configuration of the memory cell array 11 will be explained.
[0038] Figure 2 This is a diagram showing the equivalent circuit of a portion of the memory cell array 11. Figure 2 This represents a block BLK contained in the storage cell array 11. The block BLK contains a plurality of (e.g., 4) string groups SU0 to SU3.
[0039] Each string group SU contains multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.
[0040] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section according to the voltage applied to the control gate via the word line WL, thus non-volatilely storing data.
[0041] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the line decoder 11 via the drain-side select gate line SGD. When a specific voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.
[0042] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to the source line SL. The control gate of the source-side select transistor STS is connected to the source-side select gate line SGS. The source-side select transistor STS is electrically connected to the line decoder 11 via the source-side select gate line SGS. When a specific voltage is applied to the source-side select gate line SGS, the source-side select transistor STS connects the NAND string NS to the source line SL.
[0043] Within the same block BLK, the control gates of memory cell transistors MT0 to MTn are commonly connected to their respective word lines WL0 to WLn. The control gates of the drain-side select transistors STD in the string groups SU0 to SU3 are commonly connected to their respective select gate lines SGD0 to SGD3. The control gates of the source-side select transistors STS are commonly connected to the select gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS in each string group SU that are assigned the same column address.
[0044] <2.2 Physical Structure of Storage Cell Array>
[0045] Next, the physical configuration of the storage cell array 11 will be explained.
[0046] Figure 3 This is a perspective cross-sectional view showing a portion of the memory cell array 11. The memory cell array 11 includes, for example, a silicon substrate 21, a semiconductor layer 22, a conductive layer 23, an insulating layer 24, a stack 30, a plurality of pillars 40, a plurality of contacts 81, and a plurality of bit lines BL.
[0047] <2.2.1 Lower Structure>
[0048] The silicon substrate 21 is a substrate that serves as the base for the semiconductor memory device 1. At least a portion of the silicon substrate 21 is formed in a plate shape along the X and Y directions. The silicon substrate 21 is, for example, formed of a semiconductor material containing silicon. The silicon substrate 21 is an example of a "substrate".
[0049] A semiconductor layer 22 is disposed on the silicon substrate 21. The semiconductor layer 22 is layered along both the X and Y directions. The semiconductor layer 22 is used to suppress memory holes MH (see reference) during the manufacturing process of the semiconductor memory device 1. Figure 6 The semiconductor layer 22 is formed of a semiconductor material such as polycrystalline silicon. Alternatively, the semiconductor memory device 1 may have an insulating layer that functions as a termination layer instead of the semiconductor layer 22.
[0050] A conductive layer 23 is disposed on the semiconductor layer 22. The conductive layer 23 is layered along the X and Y directions. The conductive layer 23 is formed of a conductive material such as tungsten. The lower end of the pillar 40 is connected to the conductive layer 23. The conductive layer 23 functions as the source line SL.
[0051] An insulating layer 24 is disposed on the conductive layer 23. The insulating layer 24 is layered along the X and Y directions. The insulating layer 24 is formed of an insulating material such as silicon oxide.
[0052] <2.2.2 Laminated Body>
[0053] Next, the laminate 30 will be described. The laminate 30 is disposed on the insulating layer 24. The laminate 30 includes, for example, a plurality of conductive layers 31 and a plurality of insulating layers 32. The plurality of conductive layers 31 and the plurality of insulating layers 32 are stacked alternately in the Z direction.
[0054] The conductive layer 31 is formed in a plate shape along the X and Y directions. Each conductive layer 31 includes, for example, a main body made of a conductive material such as tungsten, and a barrier film disposed on the surface of the main body. The barrier film is, for example, a titanium nitride film, or a laminated structure film of titanium nitride and titanium.
[0055] One or more (e.g., a plurality of) conductive layers 31 that are farthest from the silicon substrate 21 function as drain-side selected gate lines (SGDs). In this embodiment, the two conductive layers 31 that are farthest from the silicon substrate 21 function as drain-side selected gate lines (SGDs). Drain-side selected gate lines (SGDs) are provided in common with respect to the plurality of pillars 40 arranged in the X or Y direction. The intersection of the drain-side selected gate lines (SGDs) and the channel layer 42 serves as the drain-side selected transistor (STD) (see reference). Figure 2 To facilitate explanation, the drain-side gate selection line SGD that is farthest from the silicon substrate 21 among the plurality of drain-side gate selection lines SGDs (e.g., 2) will be referred to as "the first drain-side gate selection line SGD11". Similarly, the drain-side gate selection line SGD that is the second farthest from the silicon substrate 21 compared to the first drain-side gate selection line SGD11 will be referred to as "the second drain-side gate selection line SGD12". The drain-side gate selection line SGD is an example of a "second conductive layer". The first drain-side gate selection line SGD11 is an example of a "first layer". The second drain-side gate selection line SGD12 is an example of a "second layer".
[0056] One or more (e.g., a plurality of) conductive layers 31 closest to the silicon substrate 21 among the plurality of conductive layers 31 function as source-side selected gate lines (SGS). In this embodiment, the two conductive layers 31 closest to the silicon substrate 21 among the plurality of conductive layers 31 function as source-side selected gate lines (SGS). The source-side selected gate lines (SGS) are provided in common with respect to the plurality of pillars 40 arranged in the X or Y direction. The intersection of the drain-side selected gate line (SGD), the source-side selected gate line (SGS), and the channel layer 42 serves as the aforementioned source-side selected transistor (STS) (see reference). Figure 2 To fulfill its function.
[0057] The remaining conductive layer 31 sandwiched between the conductive layers 31 that function as either the drain-side selected gate line (SGD) or the source-side selected gate line (SGS) among the multiple conductive layers 31 functions as the word line WL (control gate line). In this embodiment, the intersection of the word line WL and the channel layer 42 serves as the memory cell transistor MT (refer to...). Figure 2 The memory cell transistor MT will be described in detail below. A word line WL is provided in common with respect to the multiple pillars 40 arranged in the X and Y directions. The word line WL is an example of the "first conductive layer".
[0058] The insulating layer 32 is an interlayer insulating film disposed between two adjacent conductive layers 31 along the Z direction to insulate the two conductive layers 31. The insulating layer 32 is formed into a plate shape along the X and Y directions. The insulating layer 32 is formed of an insulating material such as silicon oxide.
[0059] The laminate 30 also includes an insulating layer 39. The insulating layer 39 is disposed above the uppermost conductive layer 31 (the conductive layer 31 furthest from the silicon substrate 21). The insulating layer 39 is formed in a plate shape along the X and Y directions. The insulating layer 39 is formed of an insulating material such as silicon oxide.
[0060] <2.2.3 Columnar Body>
[0061] Next, columnar body 40 will be described.
[0062] Multiple columns 40 are arranged spaced apart from each other on planes along the X and Y directions. For example, the multiple columns 40 are divided into multiple columns RW extending along the X direction at different positions in the Y direction. The multiple columns 40 contained in the even-numbered column RW2 from the Y-direction end are offset in the X direction relative to the multiple columns 40 contained in the odd-numbered column RW1 from the Y-direction end. The multiple columns 40 extend along the Z direction within the stack 30. The columns 40 may also be referred to as "memory columns".
[0063] Figure 4This is a cross-sectional view showing a portion of the memory cell array 11. The column 40 is cylindrical or inverted frustum-shaped. The column 40 extends in the Z direction, penetrating the stacked layer 30, the insulating layer 24, and the conductive layer 23. The lower end of the column 40 enters the semiconductor layer 22. The column 40, for example, has a multilayer film 41, a channel layer 42, an insulating core 43, and a top cap 44.
[0064] A multilayer film 41 is disposed on the outer periphery of the channel layer 42. The multilayer film 41 is located between the plurality of conductive layers 31 and the channel layer 42 in the R direction. The multilayer film 41 is an example of a "storage film". The multilayer film 41, for example, has a tunnel insulating film 51, a charge trapping film 52, and a barrier insulating film 53.
[0065] The tunnel insulating film 51 is located in the R direction between the channel layer 42 and the charge trapping film 52. The tunnel insulating film 51 is formed, for example, in a ring shape along the outer peripheral surface of the channel layer 42, extending along the channel layer 42 in the Z direction. The tunnel insulating film 51 extends in the Z direction in a manner that covers most of the columnar body 40. The tunnel insulating film 51 acts as a potential barrier between the channel layer 42 and the charge trapping film 52. The tunnel insulating film 51 comprises silicon oxide, or silicon oxide and silicon nitride.
[0066] A charge trapping film 52 is disposed on the outer periphery of the tunnel insulating film 51. The charge trapping film 52 is located between the tunnel insulating film 51 and the barrier insulating film 53. From another viewpoint, the charge trapping film 52 is located between the plurality of conductive layers 31 and the channel layer 42. The charge trapping film 52 extends in the Z direction in a manner that covers most of the columnar body 40. The charge trapping film 52 is a functional film having multiple crystal defects (trapping energy levels) capable of trapping charges in these crystal defects. The charge trapping film 52 is formed, for example, of silicon nitride. The portion of the charge trapping film 52 adjacent to each word line WL is an example of a "charge storage section".
[0067] A barrier insulating film 53 is disposed on the outer periphery of the charge trapping film 52. The barrier insulating film 53 is located in the R direction between the plurality of conductive layers 31 and the charge trapping film 52. The barrier insulating film 53 is an insulating film that suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the word line WL to the charge trapping film 52. The barrier insulating film 53 extends in the Z direction, covering most of the columnar body 40. The barrier insulating film 53 is, for example, a multilayer structure film formed by stacking multiple insulating films such as silicon oxide or metal oxide films. An example of a metal oxide is aluminum oxide. The barrier insulating film 53 may also contain high-k materials such as silicon nitride or hafnium oxide.
[0068] A channel layer 42 is disposed inside the multilayer film 41. The channel layer 42 is formed in a ring shape and extends in the Z direction along the entire length (full height) of the columnar body 40. The portion of the multilayer film 41 at the same height as the source line SL is removed. Thus, the lower end of the channel layer 42 is connected to the source line SL. The channel layer 42 is formed of a semiconductor material such as polycrystalline silicon. The channel layer 42 may also be doped with impurities. The impurities contained in the channel layer 42 are, for example, any one selected from the group consisting of carbon, phosphorus, boron, and germanium. When a voltage is applied to the word line WL, the channel layer 42 forms a channel and electrically connects the bit line BL to the source line SL. In this embodiment, the channel layer 42 has a first portion 61, a second portion 62, and a third portion 63.
[0069] Part 1 61 is a thin film portion of the channel layer 42. Part 1 61 is located lower than Part 2 62 and Part 3 63. Part 1 61 is, for example, annular and extends in the Z direction. At least a portion of Part 1 61 is located in the R direction between the plurality of word lines WL and the insulating core 43. In this embodiment, a portion of Part 1 61 (e.g., the upper end) is located in the R direction between the second drain-side select gate line SGD12 and the insulating core 43. Another portion of Part 1 61 (e.g., the lower end) is located in the R direction between the plurality of source-side select gate lines SGS and the insulating core 43. Part 1 61 occupies most of the channel layer 42 in the Z direction and forms the main body of the channel layer 42. The lower end of Part 1 61 is connected to the source line SL.
[0070] Figure 5 It is along Figure 4 The image shows a cross-sectional view of the memory cell array 11 along line F5-F5. At the same height as each word line WL in the Z direction, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the column 40, the blocking insulating film 53, the charge trapping film 52, the tunnel insulating film 51, and the first part 61 of the channel layer 42.
[0071] Alternatively, the memory cell array 11 may have a floating gate charge storage section (floating gate electrode) instead of the charge trapping film 52 as the charge storage film. The floating gate electrode is formed, for example, from polysilicon containing impurities. The impurities contained in the polysilicon are, for example, phosphorus or boron. The floating gate electrode is disposed between the barrier insulating film 53 and the tunnel insulating film 51. In this case, the floating gate memory cell transistor MT is formed by the end of the word line WL adjacent to the pillar 40, the barrier insulating film 53, the charge storage section (floating gate electrode), the tunnel insulating film 51, and the first portion 61 of the channel layer 42.
[0072] return Figure 4 The second part 62 will be described. The second part 62 is the thick film portion of the channel layer 42. The second part 62 is located above the first part 61 and the third part 63. The second part 62 is, for example, annular and extends in the Z direction. The film thickness T2 of the second part 62 in the R direction is greater than the film thickness T1 of the first part 61 in the R direction. For example, the film thickness T2 of the second part 62 in the R direction is more than twice the film thickness T1 of the first part 61 in the R direction. According to other viewpoints, the film thickness T2 of the second part 62 in the R direction is more than 5 nm greater than the film thickness T1 of the first part 61 in the R direction.
[0073] In this embodiment, the second portion 62 forms the upper end of the channel layer 42. A portion of the second portion 62 is located between the insulating layer 39 and the top cover portion 44 in the R direction. The contact 81 described below is connected to the second portion 62 in the Z direction. The contact 81 has a lower end 81e2 that is connected to the columnar body 40. The inner diameter D2 of the second portion 62 of the channel layer 42 (for example, the inner diameter of the upper end 62e1 of the second portion 62) is smaller than the outer diameter D1 of the lower end 81e2 of the contact 81. The second portion 62 is connected to the contact 81.
[0074] In this embodiment, the lower end 62e2 of the second portion 62 is closer to the silicon substrate 21 than the upper end 43e1 of the insulating core 43. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to a point closer to the silicon substrate 21 than a portion of the insulating core 43. A portion of the second portion 62 is adjacent to the insulating core 43 in the R direction.
[0075] In this embodiment, the lower end 62e2 of the second portion 62 is closer to the silicon substrate 21 than the upper end (upper surface) 31e1 of the first drain-side select gate line SGD11. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to a point closer to the silicon substrate 21 than at least a portion of the first drain-side select gate line SGD11. A portion of the second portion 62 is located in the R direction between at least a portion of the first drain-side select gate line SGD11 and the insulating core 43. The upper end 31e1 of the first drain-side select gate line SGD11 is the end facing the opposite side of the silicon substrate 21 and is an example of the "first end".
[0076] Furthermore, in this embodiment, the lower end 62e2 of the second portion 62 is located at the same height as the lower end (lower surface) 31e2 of the first drain-side select gate line SGD11 in the Z direction, or is located closer to the silicon substrate 21 than the lower end 31e2 of the first drain-side select gate line SGD11. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to the same height as the lower end 31e2 of the first drain-side select gate line SGD11, or extends closer to the silicon substrate 21 than the lower end 31e2 of the first drain-side select gate line SGD11. The lower end 31e2 of the first drain-side select gate line SGD11 is the end facing the silicon substrate 21, and is an example of the "second end".
[0077] The film quality of part 62 is the same as that of part 61 throughout the entire film thickness along the R direction. "Same film quality" means, for example, that the concentration of impurities contained in the film is the same. In this case, the same impurity concentration means that the difference in impurity concentration is less than 2 times. That is, "same film quality" means, for example, that the lower impurity concentration in part 61 and part 62 is 1 × 10⁻⁶. 20 atoms·cm -3 In the case of the higher impurity concentrations in Part 1, 61 and Part 2, 62, the concentration is less than 2 × 10⁻⁶. 20 atoms·cm -3 Instead, "same membrane quality" can also refer to the same particle size of the materials contained in the membrane. In this case, "same particle size" means that the difference in particle size is less than 30%.
[0078] Part 3 63 is located between Part 1 61 and Part 2 62 in the Z direction. Part 3 63 is the portion where the film thickness continuously varies between Part 1 61 and Part 2 62. Part 3 63 is, for example, annular and extends in the Z direction. The film thickness T3 of Part 3 63 in the R direction is less than the film thickness T2 of Part 2 62 in the R direction, and greater than the film thickness T1 of Part 1 61 in the R direction.
[0079] In this embodiment, the film thickness T3 of the third portion 63 gradually decreases as it moves closer to the first portion 61 from the second portion 62. Within the third portion 63, the higher it is located (closer to the second portion 62 in the Z direction), the greater the variation in film thickness T3. "Variation in film thickness" refers to the amount by which the film thickness in the R direction changes per unit distance traveled in the Z direction. In this embodiment, the closer the third portion 63 is to the second portion 62 in the Z direction, the greater the change in film thickness T3. The third portion 63 is formed as an arc shape that bulges obliquely upwards towards the outer periphery.
[0080] Next, the insulating core 43 will be described. The insulating core 43 is disposed inside the channel layer 42, filling a portion of the interior of the channel layer 42. The insulating core 43 is formed of an insulating material such as silicon oxide. The insulating core 43 extends in the Z direction in such a way that it covers most of the columnar body 40 except for the upper end of the columnar body 40. The upper end 43e1 of the insulating core 43 is located at the same height as the upper end 31e1 of the first drain-side select gate line SGD11 in the Z direction, or is located above the upper end 31e1 of the first drain-side select gate line SGD11.
[0081] The insulating core 43 has a first portion 71 and a second portion 72. The first portion 71 of the insulating core 43 is located on the inner peripheral side of the first portion 61 of the channel layer 42. A portion of the first portion 71 of the insulating core 43 is formed in an annular shape along the inner peripheral surface of the first portion 61 of the channel layer 42, and has a space (air gap) S inside. However, the space S is not necessary. On the other hand, the second portion 72 of the insulating core 43 is located on the inner peripheral sides of the second portion 62 and the third portion 63 of the channel layer 42, and densely fills the inner peripheral sides of the second portion 62 and the third portion 63 of the channel layer 42.
[0082] A top cover portion 44 is disposed above the insulating core 43. The top cover portion 44 is a semiconductor portion formed of amorphous silicon or other semiconductor materials. The top cover portion 44 may also be doped with impurities. The impurities contained in the top cover portion 44 may be selected from any one of the group consisting of carbon, phosphorus, boron, and germanium. The top cover portion 44 fills the inner peripheral side of the second portion 62 of the channel layer 42. The top cover portion 44 and the second portion 62 of the channel layer 42 together form the upper end of the columnar body 40. The contact point 81 is connected to the top cover portion 44 in the Z direction.
[0083] <2.2.4 Upper Structure>
[0084] Multiple contacts 81 are respectively disposed on the columnar body 40. The contacts 81 extend in the Z direction and connect the bit line BL to the channel layer 42 of the columnar body 40. The contacts 81 are formed of conductive materials such as tungsten.
[0085] Multiple bit lines BL are respectively disposed on the contact 81. The bit lines BL are connected to the channel layer 42 of the pillar 40 via the contact 81. Thus, by combining the word line WL and the bit line BL, any memory cell transistor MT can be selected from the multiple memory cell transistors MT arranged in a three-dimensional manner.
[0086] <3. Manufacturing Method>
[0087] Next, an example of a method for manufacturing semiconductor memory device 1 will be described.
[0088] Figures 6 to 10This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device 1. First, a semiconductor layer 22, a sacrificial layer (not shown), and an insulating layer 24 are deposited on a silicon substrate 21. The sacrificial layer is, for example, formed of silicon nitride. This sacrificial layer is the insulating layer that will be replaced by a conductive layer 23 in a subsequent process.
[0089] Next, as Figure 6 As shown in (a), sacrificial layers 101 and insulating layers 32 are alternately deposited on insulating layer 24. Sacrificial layer 101 is formed of an insulating material such as silicon nitride. Sacrificial layer 101 is the insulating layer that is replaced by conductive layer 31 in a subsequent process. Sacrificial layer 101 is an example of an "intermediate layer". The uppermost sacrificial layer 101S (the sacrificial layer 101S furthest from silicon substrate 21) among the plurality of sacrificial layers 101 has an upper end (upper surface) 101e1 facing the opposite side of silicon substrate 21 and a lower end (lower surface) 101e2 facing silicon substrate 21. The upper end 101e1 of sacrificial layer 101S is at a height corresponding to the upper end 31e1 of the first drain-side select gate line SGD11 formed in a subsequent process. The lower end 101e2 of sacrificial layer 101 is at a height corresponding to the lower end 31e2 of the first drain-side select gate line SGD11 formed in a subsequent process. Alternatively, the conductive layer 31 and the insulating layer 32 can be directly and alternately laminated, instead of providing the sacrificial layer 101. In this case, the conductive layer 31 is equivalent to an example of an "intermediate layer". Next, the insulating layer 39 is laminated on the sacrificial layer S. Thus, an intermediate laminate 30A is formed.
[0090] Next, as Figure 6 As shown in (b), a memory hole MH is provided for the intermediate stack 30A. The memory hole MH is an opening extending in the Z direction. The memory hole MH is formed in the Z direction through the intermediate stack 30A, the insulating layer 24, and the sacrificial layer (not shown) to the middle of the semiconductor layer 22. The memory hole MH is an example of a "space portion". Next, as... Figure 6 As shown in (c), the materials of the barrier insulating film 53, the charge trapping film 52, and the tunnel insulating film 51 are sequentially supplied to the inner surface of the storage hole MH, thereby forming the barrier insulating film 53, the charge trapping film 52, and the tunnel insulating film 51 in sequence.
[0091] Next, as Figure 7 As shown in (d), material is supplied to the inside of the storage hole MH to form an annular semiconductor layer 111 along the inner peripheral surface of the tunnel insulating film 51. The film thickness T4 of the semiconductor layer 111 in the R direction is the same as the film thickness T2 of the second portion 62 of the channel layer 42 in the R direction.
[0092] Next, as Figure 7As shown in (e), an insulating material such as silicon oxide is supplied to the inner peripheral side of the semiconductor layer 111 to form an insulating portion 112A that fills the interior of the annular semiconductor layer 111. Then, for example, the upper part of the insulating portion 112A is removed by etching. In this embodiment, the portion of the insulating portion 112A that is above the lower end 101e2 of the sacrificial layer 101S is removed. Thus, an insulating portion 112 is formed inside the annular semiconductor layer 111. The material used to form the insulating portion 112 (e.g., silicon oxide) is an example of a "first material".
[0093] Next, as Figure 7 As shown in (f), an insulating material such as silicon nitride is supplied to the upper surface of the semiconductor layer 111, the inner peripheral surface of the semiconductor layer 111 located inside the memory hole MH, and the upper surface of the insulating portion 112, thereby forming a protective film 113 covering the upper surface of the semiconductor layer 111, the inner peripheral surface of the semiconductor layer 111 located inside the memory hole MH, and the upper surface of the insulating portion 112. The material used to form the protective film 113 (e.g., silicon nitride) is an example of a "second material". The second material is different from the first material. The protective film 113 covers the region from the upper part of the semiconductor layer 111 to a region closer to the silicon substrate 21 than the upper end 101e1 of the sacrificial layer 101S. Furthermore, in this embodiment, the protective film 113 covers the region from the upper part of the semiconductor layer 111 to a region closer to the silicon substrate 21 than the lower end 101e2 of the sacrificial layer 101S.
[0094] Next, as Figure 8 As shown in (g), the portions of the protective film 113 located on the upper surface of the semiconductor layer 111 and the upper surface of the insulating portion 112 are removed by, for example, reactive ion etching (RIE). This forms a protective film 113 with an opening 113a exposing the insulating portion 112.
[0095] Next, as Figure 8 As shown in (h), the insulating portion 112 is removed by etching through the opening 113a of the protective film 113. Then, as... Figure 8 As shown in (i), the semiconductor layer 111 is refined while the protective film 113 is provided. Thus, while maintaining the film thickness of the region in the semiconductor layer 111 corresponding to the second portion 62 of the channel layer 42, the regions in the semiconductor layer 111 corresponding to the first portion 61 and the third portion 63 of the channel layer 42 are thinned. This forms a channel layer 42 comprising the first portion 61, the second portion 62, and the third portion 63.
[0096] Next, as Figure 9 As shown in (j), the protective film 113 is removed, for example, by etching. Next, as... Figure 9As shown in (k), an insulating material such as silicon oxide is supplied to the inner peripheral side of the channel layer 42 to form an insulating portion 43A that fills the inner peripheral side of the channel layer 42. Then, the upper part of the insulating portion 43A is removed to a position corresponding to the upper end 43e1 of the insulating core 43 in the Z direction by means of etching, for example. Thus, an insulating core 43 is formed on the inner peripheral side of the channel layer 42. Next, as Figure 9 As shown in (l), a semiconductor material such as amorphous silicon is supplied to the inner peripheral side of the channel layer 42 to form the top cover 44.
[0097] Next, as Figure 10 As shown in (m), the excess portions of the multilayer film 41, the channel layer 42, the top cover 44, and the insulating layer 39 are removed by cutting along the cutting surface C, forming an intermediate laminate 30B and a columnar body 40.
[0098] Next, an etching solution is supplied through holes or trenches (not shown) to remove the sacrificial layer disposed between the semiconductor layer 22 and the insulating layer 24 in the lower structure. At this time, a portion of the multilayer film 41 located at the same height as the sacrificial layer to be removed is also removed. Then, conductive material is supplied to the space where the sacrificial layer has been removed to form a conductive layer 23 (source line SL). Next, an etching solution is supplied through holes or trenches (not shown) to remove the plurality of sacrificial layers 101 contained in the intermediate stack 30B. Then, material of the conductive layer 31 is supplied to the space where the plurality of sacrificial layers 101 have been removed to form a word line WL, a drain-side select gate line SGD, and a source-side select gate line SGS. Thus, the stack 30 is formed. Thereafter, as... Figure 10 As shown in (n), a semiconductor memory device 1 is completed by forming a contact 81 and a bit line BL.
[0099] <4. Advantages>
[0100] In recent years, researchers have been studying the thinning of channel layers to further improve the electrical characteristics of semiconductor memory devices. However, when the channel layer is a thin film along its entire Z-direction, the following issues arise. For example, the resistance (channel resistance) at the upper end of the channel layer can sometimes increase. If the resistance of the channel layer increases, for example, the current flowing through the channel layer during data readout (cell current) decreases, thereby reducing the data readout characteristics. Alternatively / furthermore, if the channel layer is thinner in the portion adjacent to the drain-side selected gate line (SGD), the efficiency of hole formation due to gate-induced drain leakage (GIDL) during data erasure operations decreases. In this case, the efficiency of the data erasure operation decreases. Furthermore, instead of these / furthermore, if the film thickness at the upper end of the channel layer is thin, a portion of the upper end of the channel layer may break during etching to form the insulating core 43 on the inner periphery of the channel layer, potentially damaging a portion of the sacrificial layer and insulating layer contained in the intermediate stack. In this case, the yield of the semiconductor memory device decreases.
[0101] Therefore, in this embodiment, the channel layer 42 includes: a first portion 61 (thin film portion) located between the plurality of word lines WL and the insulating core 43; and a second portion 62 (thick film portion) located on the opposite side of the silicon substrate 21 relative to the first portion 61, and the film thickness in the R direction is more than twice the R direction film thickness of the first portion 61. The second portion 62 extends in the Z direction to a point nearer to the silicon substrate 21 than a portion of the insulating core 43, and extends to a point nearer to the silicon substrate 21 than the upper end 31e1 of the drain-side select gate line SGD (e.g., the first drain-side select gate line SGD11). According to this configuration, the resistance decreases and the cell current increases at the upper end of the channel layer 42. In addition, instead of the above / furthermore, if a thick film portion of the channel layer 42 exists in the portion adjacent to the drain-side select gate line SGD, the generation efficiency of holes caused by gate-induced drain leakage during the data erasure operation can be improved. In this case, the efficiency of the data erasure operation can be improved. Furthermore, instead of the aforementioned / in addition, if a thick film portion is present at the upper end of the channel layer 42, damage to a portion of the sacrificial layer 101 and the insulating layer 32 contained in the intermediate stack 30A can be suppressed during etching to form the insulating core 43. In this case, the yield of the semiconductor memory device 1 can be improved.
[0102] In this embodiment, the second portion 62 of the channel layer 42 extends in the Z direction to the same height as the lower end 31e of the drain-side selected gate line SGD (e.g., the first drain-side selected gate line SGD11), or closer to the silicon substrate 21 than the lower end 31e of the drain-side selected gate line SGD (e.g., the first drain-side selected gate line SGD11). According to this configuration, the channel layer 42 is thicker in several portions adjacent to the drain-side selected gate line SGD, thus further improving the efficiency of hole generation caused by gate-induced drain leakage during data erasure.
[0103] In this embodiment, the channel layer 42 includes a third portion 63 located between the first portion 61 and the second portion 62 in the Z direction. The film thickness T3 gradually decreases as it moves closer to the first portion 61 from the second portion 62. The closer the third portion 63 is to the second portion 62 in the Z direction, the greater the variation in film thickness T3. With this configuration, the material of the insulating core 43 can easily penetrate to a lower position than the second portion 62 of the channel layer 42, thereby facilitating the formation of the insulating core 43 on the inner periphery of the first portion 61 of the channel layer 42. This makes it easier and more reliable to ensure the necessary insulation.
[0104] In this embodiment, the semiconductor memory device 1 further includes a contact 81 located on the opposite side of the silicon substrate 21 relative to the pillar 40 and connected to the pillar 40. The contact 81 is connected to the second portion 62 of the channel layer 42 in the Z direction. According to this configuration, the contact 81 is connected to the first portion 61 via the second portion 62 of the channel layer 42, thus reducing the resistance between the contact 81 and the first portion 61 of the channel layer 42. This increases the cell current, thereby improving data readout characteristics.
[0105] In this embodiment, the second portion 62 of the channel layer 42 is formed in an annular shape. The contact 81 has a lower end 81e2 that connects to the columnar body 40. The inner diameter D2 of the second portion 62 of the channel layer 42 is smaller than the outer diameter D1 of the lower end 81e2 of the contact 81. With this configuration, even with component tolerances, the contact 81 can easily connect to the second portion 62 of the channel layer 42. Therefore, the resistance between the contact 81 and the first portion 61 of the channel layer 42 can be reduced more reliably.
[0106] In this embodiment, the method for manufacturing the semiconductor memory device 1 includes: providing a protective film 113 relative to the semiconductor layer 111, the protective film 113 covering a region from the top of the semiconductor layer 111 to a region closer to the silicon substrate 21 than the upper end 101e1 of the sacrificial layer 101S; and refining the semiconductor layer 111 while the protective film 113 is provided, thereby forming a channel layer 42 including a first portion 61 and a second portion 62. According to this configuration, the second portion 62 can be easily formed over a relatively long region in the Z direction.
[0107] <5. Examples of Changes in Manufacturing Methods>
[0108] Next, a variation of the manufacturing method of the semiconductor memory device 1 will be described. In this variation, the materials used to form the insulating portion 112 and the protective film 113 are different from those in the first embodiment. Furthermore, the processes other than those described below are the same as those in the manufacturing method of the first embodiment.
[0109] Figure 11 and Figure 12 This is a cross-sectional view illustrating a variation of the manufacturing method of semiconductor memory device 1. The manufacturing method of this variation has been described up to the first embodiment. Figure 7 Up to step (d) in the process, the manufacturing method is the same as that in the first embodiment. Therefore, the method described in the first embodiment here is the same. Figure 7 The process following (d) will be explained. Figure 11 and Figure 12 In the text, (e'), (f'), (g'), (h'), (i'), and (k') represent the symbols described in the first embodiment, respectively. Figures 7 to 9 The processes corresponding to (f), (g), (h), (i), and (k) in the text.
[0110] like Figure 11 As shown in (e'), in this variation, an insulating material such as silicon nitride is supplied to the inner periphery of the semiconductor layer 111 to form an insulating portion 112A' that fills the interior of the annular semiconductor layer 111. Then, for example, the upper part of the insulating portion 112A' is removed by etching. In this embodiment, the portion of the insulating portion 112A' that is above the lower end 101e2 of the sacrificial layer 101S is removed. Thus, an insulating portion 112' is formed inside the annular semiconductor layer 111. The material used to form the insulating portion 112' (e.g., silicon nitride) is an example of a "first material".
[0111] Next, as Figure 11 As shown in (f'), an insulating material such as silicon oxide is supplied to the upper surface of the semiconductor layer 111, the inner peripheral surface of the semiconductor layer 111 located inside the memory hole MH, and the upper surface of the insulating portion 112', and a protective film 113' is formed covering the upper surface of the semiconductor layer 111, the inner peripheral surface of the semiconductor layer 111 located inside the memory hole MH, and the upper surface of the insulating portion 112'. The material forming the protective film 113' (e.g., silicon oxide) is an example of a "second material". The second material is different from the first material.
[0112] Next, as Figure 11As shown in (g'), portions of the protective film 113' located on the upper surface of the semiconductor layer 111 and the upper surface of the insulating portion 112' are removed by, for example, reactive ion etching (RIE). This forms a protective film 113' with an opening 113a' exposing the insulating portion 112'.
[0113] Next, as Figure 12 As shown in (h'), the insulating portion 112' is removed by etching through the opening 113a' of the protective film 113'. Then, as... Figure 12 As shown in (i'), the semiconductor layer 111 is refined while the protective film 113 is provided. Thus, while maintaining the film thickness of the region corresponding to the second portion 62 in the semiconductor layer 111, thinning is performed on the regions of the semiconductor layer 111 corresponding to the first portion 61 and the third portion 63. This forms a channel layer 42 comprising the first portion 61, the second portion 62, and the third portion 63.
[0114] In this variation, the process of removing the protective film 113' is not performed (as in the first embodiment). Figure 9 (j) corresponds to the process in the diagram). Therefore, next, as follows: Figure 12 As shown in (k'), an insulating material such as silicon oxide is supplied to the inner peripheral side of the channel layer 42 to form an insulating portion 43A' that fills the inner peripheral side of the channel layer 42. In this variation, the insulating portion 43A' that fills the inner peripheral side of the channel layer 42 is formed while the protective film 113' remains. Then, for example, by etching, most of the protective film 113' and the upper part of the insulating portion 43A' are removed to a position corresponding to the upper end 43e1' of the insulating core 43' in the Z direction. Thus, an insulating core 43' is formed on the inner peripheral side of the channel layer 42. The subsequent processes are the same as in the first embodiment.
[0115] According to this configuration, compared with the manufacturing method of the first embodiment, the step of removing the protective film 113' can be omitted. This improves the manufacturability of the semiconductor memory device 1. In this variation, a portion of the protective film 113' remains in the finished semiconductor memory device 1. For example, the insulating core 43' has an upper end portion 91 adjacent to the second portion 62 of the channel layer 42 in the R direction. The upper end portion 91 includes: an insulator 91a located at the center of the insulating core 43 in the R direction; and an insulating film 91b located between the insulator 91a and the channel layer 42 in the R direction. The insulator 91a is formed by... Figure 12 A portion of the insulating part 43A' formed in the (k') process is formed. The insulating film 91b is formed from... Figure 11A portion of the protective film 113' formed in process (f') is formed. The insulator 91a and the insulating film 91b have different compositions or properties. "Different compositions" means, for example, that the impurities contained are different. "Different properties" means, for example, that the density or film stress is different.
[0116] (Second Implementation)
[0117] Next, the second embodiment will be described. The second embodiment differs from the first embodiment at the point where the second portion 62 of the channel layer 42 extends further downward. The configuration other than that described below is the same as the first embodiment.
[0118] Figure 13 This is a cross-sectional view showing a portion of the memory cell array 11A according to the second embodiment. In this embodiment, the lower end 62e of the second portion 62 of the channel layer 42 is closer to the silicon substrate 21 than the upper end (upper surface) 31e3 of the second drain-side select gate line SGD12. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to a point closer to the silicon substrate 21 than at least a portion of the second drain-side select gate line SGD12. A portion of the second portion 62 is located in the R direction between at least a portion of the second drain-side select gate line SGD12 and the insulating core 43. The upper end 31e3 of the second drain-side select gate line SGD12 is the end facing the opposite side of the silicon substrate 21 and is an example of the "third end".
[0119] Furthermore, in this embodiment, the lower end 62e2 of the second portion 62 of the channel layer 42 is located at the same height as the lower end (lower surface) 31e4 of the second drain-side select gate line SGD12 in the Z direction, or closer to the silicon substrate 21 than the lower end 31e4 of the second drain-side select gate line SGD12. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to the same height as the lower end 31e4 of the second drain-side select gate line SGD12, or closer to the silicon substrate 21 than the lower end 31e4 of the second drain-side select gate line SGD12. According to this configuration, the generation efficiency of holes caused by gate-induced drain leakage during data erasure can be further improved.
[0120] (Third Implementation)
[0121] Next, the third embodiment will be described. The third embodiment differs from the second embodiment at the point where the second portion 62 of the channel layer 42 extends further downward. The configuration other than that described below is the same as the second embodiment.
[0122] Figure 14This is a cross-sectional view showing a portion of the memory cell array 11B according to the third embodiment. In this embodiment, the plurality of conductive layers 31 included in the stacked body 30 include dummy lines DL. The dummy lines DL are located in the Z direction between the drain-side select gate line SGD and the plurality of word lines WL. The dummy lines DL are conductive layers that are not connected to the transistors that function as cell transistors MT. The dummy lines DL function as a buffer between the drain-side select gate line SGD and the plurality of word lines WL, making it difficult for the voltage applied to the drain-side select gate line SGD to be transmitted to the word lines WL.
[0123] In this embodiment, the lower end 62e2 of the second portion 62 of the channel layer 42 is closer to the silicon substrate 21 than the upper end 31e5 of the dummy line DL. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to a position closer to the silicon substrate 21 than at least a portion of the dummy line DL. A portion of the second portion 62 is located in the R direction between at least a portion of the dummy line DL and the insulating core 43.
[0124] Furthermore, in this embodiment, the lower end 62e2 of the second portion 62 of the channel layer 42 is located at the same height as the lower end 31e6 of the dummy line DL in the Z direction, or closer to the silicon substrate 21 than the lower end 31e6 of the dummy line DL. That is, the second portion 62 extends from above the upper end 43e1 of the insulating core 43 to the same height as the lower end 31e6 of the dummy line DL, or closer to the silicon substrate 21 than the lower end 31e6 of the dummy line DL. According to this configuration, the resistance of the channel layer 42 can sometimes be made smaller.
[0125] The above describes several implementation methods and variations. However, the implementation methods and variations are not limited to the examples described above. For example, the number of drain-side select gate lines SGD, word lines WL, and dummy lines DL contained in a single stacked layer 30 are not limited to the examples described above.
[0126] Alternatively, the semiconductor memory device 1 may not have a silicon substrate 21. The semiconductor memory device 1 may, for example, include: an array chip comprising the aforementioned stacked body 30 and a plurality of pillars 40; and a circuit chip formed separately from the array chip; with the array chip flipped vertically and attached to the circuit chip. The array chip may, for example, include a memory cell array 11. The circuit chip may, for example, include an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17. In this semiconductor memory device 1, bonding metal is embedded at corresponding positions on the bonding surface of the array chip and the bonding surface of the circuit chip, through which the memory cell array 11 of the memory cell array is electrically connected to transistors formed on the substrate constituting the circuit chip (e.g., transistors constituting the row decoder module 16 and the sense amplifier module 17). In this semiconductor memory device 1, the silicon substrate 21 may also be stripped away and not present in the final product. Therefore, in the above description, "opposite side of silicon substrate 21" can be replaced with "above", and "side closer to silicon substrate 21" can be replaced with "below". In addition, "above" and "below" in this application are expedient expressions used to describe the positional relationship of the constituent elements, and do not specify the vertical direction (gravitational direction) in the final product.
[0127] According to at least one embodiment described above, a semiconductor memory device includes a stacked body and a channel layer. The stacked body includes a plurality of conductive layers, comprising a plurality of first conductive layers and one or more second conductive layers located above the plurality of first conductive layers. The channel layer includes: a first portion located between the plurality of first conductive layers and an insulating core; and a second portion located above the first portion, having a film thickness at least 5 nm greater than the film thickness of the first portion in the second direction, or at least twice the film thickness of the first portion in the second direction. The second portion extends below the upper end of the insulating core and below the upper surface of the uppermost of the one or more second conductive layers. With this configuration, improved electrical characteristics can be achieved.
[0128] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the invention described in the claims and the same scope thereof.
[0129] For example, amorphous silicon is exemplified as the constituent material of the top cover 44, but it can also be crystallized in a thermal process to become polycrystalline silicon, the same as the channel layer 42.
[0130] [Explanation of Symbols]
[0131] 1. Semiconductor memory device
[0132] 21. Silicon substrate (substrate)
[0133] 30 laminated bodies
[0134] 30A and 30B intermediate laminates
[0135] 31 Conductive layer
[0136] WL lettering (first conductive layer)
[0137] SGD drain-side selected gate line (second conductive layer)
[0138] SGD11 First drain-side gate selection line (layer 1)
[0139] SGD12 Second drain-side gate selection line (second layer)
[0140] DL dummy line
[0141] 32 Insulation layer
[0142] 40 columnar bodies
[0143] 41. Multilayer membranes (storage membranes)
[0144] 42 Channel Layer
[0145] 43 Insulating Core
[0146] 61 Part 1
[0147] 62 Part 2
[0148] 63 Part 3
[0149] 81 contacts
[0150] 111 Semiconductor Layer
[0151] 113, 113' Protective film.
Claims
1. A semiconductor memory device, characterized in that... have: A stacked body includes multiple gate electrode layers and multiple insulating layers, wherein the multiple gate electrode layers and the multiple insulating layers are stacked alternately in a first direction; A columnar body extending along the first direction within the stacked body, and comprising: an insulating core, a channel layer located between the plurality of gate electrode layers and the insulating core, and a storage film located between the plurality of gate electrode layers and the channel layer; and Bit lines are disposed on one side of the first direction in the stacked volume; and The plurality of gate electrode layers include: a plurality of first gate electrode layers forming memory cell transistors at their intersections with the channel layer; and one or more second gate electrode layers located above the plurality of first gate electrode layers when the bit line side is set to the top, and forming selection transistors at their intersections with the channel layer. The channel layer includes: a first portion located between the uppermost first gate electrode layer of the plurality of first gate electrode layers and the insulating core, and having an annular cross-sectional shape orthogonal to the first direction; and a second portion extending from above the upper end of the uppermost second gate electrode layer of the plurality of second gate electrode layers to at least the same height as the lower end of the uppermost second gate electrode layer, and having an annular cross-sectional shape. The film thickness of the second part in the second direction, which intersects the first direction, from the outer periphery to the inner periphery is greater than the film thickness of the first part in the second direction from the outer periphery to the inner periphery.
2. The semiconductor memory device according to claim 1, characterized in that: The film thickness in the second direction of the second part is more than 5 nm greater than the film thickness in the second direction of the first part.
3. The semiconductor memory device according to claim 1, characterized in that: The film thickness in the second direction of the second part is more than twice the film thickness in the second direction of the first part.
4. The semiconductor memory device according to claim 1, characterized in that: The second part extends below the upper end of the insulating core.
5. The semiconductor memory device according to any one of claims 1 to 4, characterized in that: The second gate electrode layer comprises two or more layers, and The second gate electrode layer includes: the uppermost second gate electrode layer, i.e., the first layer, and the second layer located below the first layer; The second part extends to at least the same height as the lower end of the second layer.
6. The semiconductor memory device according to any one of claims 1 to 4, characterized in that: The membrane material of the second part is the same as that of the first part.
7. The semiconductor memory device according to any one of claims 1 to 4, characterized in that: The channel layer includes: a third portion located between the first portion and the second portion in the first direction, which gradually thins as it moves from the second portion closer to the first portion. The closer the third part is to the second part in the first direction, the greater the variation in film thickness in the second direction.
8. The semiconductor memory device according to any one of claims 1 to 4, characterized in that... It also includes: a contact located above the columnar body, electrically connecting the columnar body to the bit line. The contact point is connected to the upper end of the second part in the first direction.
9. The semiconductor memory device according to claim 8, characterized in that: At least a portion of the second part is ring-shaped. The contact point has a lower end that connects to the columnar body. The inner diameter of the second part at the upper end is smaller than the outer diameter of the contact at the lower end.
10. The semiconductor memory device according to claim 9, characterized in that... It also has: The top cover is located inside the second part.
11. The semiconductor memory device according to any one of claims 1 to 4, characterized in that: The insulating core has an upper end portion adjacent to the second portion in the second direction. The upper end portion includes: an insulator and an insulating film located between the insulator and the second portion in the second direction. The composition or properties of the insulator are different from those of the insulating film.
12. The semiconductor memory device according to any one of claims 1 to 4, characterized in that: The insulating core includes a spatial portion.
13. A method for manufacturing a semiconductor memory device, characterized in that... include: A laminate is formed by alternately stacking multiple first layers and multiple second layers with different materials in a first direction; A spatial portion extending in the first direction is formed within the laminated body; A storage film is formed on the inner surface of the space. After the storage film is formed, a semiconductor layer is formed on the inner surface of the space, the semiconductor layer including a first region and a second region located above the first region; A protective film is provided such that, when one side of the first direction of the stack is set to the top, the protective film covers a position from the top end of the semiconductor layer to a position lower than the top end of the uppermost of the plurality of first layers; After the protective film is applied, the semiconductor layer is etched such that the thickness of the first region in the second direction intersecting the first direction is thinner than the thickness of the second region in the second direction. as well as The uppermost first layer serves as the gate electrode layer, and a selection transistor is formed at the intersection of the second region of the semiconductor layer and the gate electrode layer.