Memory stick failure prediction method and apparatus, computing device, and storage medium

Abstract

Embodiments of the present application provide a memory bank failure prediction method and device, a computing device and a storage medium. In the embodiments of the present application, a plurality of aggregated failure features of each storage array included in a memory bank are mined from error log data of the memory bank. The plurality of aggregated failure features represent the failure information of the storage array from multiple dimensions such as rows, columns and storage units. A machine learning method is used to predict the failure of the memory bank based on the plurality of aggregated failure features of each storage array. Thus, the accuracy and efficiency of the memory bank failure prediction are greatly improved, and the availability, reliability and serviceability of the memory bank are ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, computing device, and storage medium for predicting memory module failures. Background Technology

[0002] Memory failure is one of the most common hardware system failures. Memory failures can result in correctable errors (CE) and uncorrectable errors (UE), with UE leading to computer system malfunctions. As memory access frequency increases, the failure rate of 8x8 memory modules is significantly higher than that of 4x4 memory modules, greatly impacting the reliability, availability, and serviceability of computer systems. Therefore, accurate and efficient failure prediction for x8 memory modules is essential. Summary of the Invention

[0003] This application provides a method, apparatus, computing device, and storage medium for predicting memory module failures, thereby improving the accuracy and efficiency of memory module failure prediction.

[0004] This application provides a memory module failure prediction method. The memory module includes at least one storage array, and the storage array includes multiple storage units. The method includes: acquiring error log data of the memory module, the error log data recording information about correctable errors (CEs) occurring in the memory module within a historical time period; determining multiple aggregated failure features corresponding to each of the at least one storage array based on the error log data, wherein the multiple aggregated failure features include a first aggregated failure feature representing CEs occurring in rows of the storage array, a second aggregated failure feature representing CEs occurring in columns of the storage array, and a third aggregated failure feature representing CEs occurring in storage units; inputting the multiple aggregated failure features corresponding to each of the at least one storage array into a machine learning model to predict the probability of uncorrectable errors (UEs) occurring in each of the at least one storage array, and performing failure prediction on the memory module based on the probability of UEs occurring in each of the at least one storage array.

[0005] This application embodiment also provides a memory module fault prediction device. The memory module includes at least one storage array, and the storage array includes multiple storage units. The device includes: an acquisition module, used to acquire error log data of the memory module, the error log data recording information about correctable errors (CEs) occurring in the memory module within a historical time period; a feature aggregation module, used to determine, based on the error log data, a first aggregated fault feature representing a row-level CE, a second aggregated fault feature representing a column-level CE, and a third aggregated fault feature representing a storage unit CE for each of the at least one storage array; and a prediction module, used to input the multiple aggregated fault features corresponding to each of the at least one storage array into a machine learning model to predict the probability of an uncorrectable error (UE) occurring in each of the at least one storage array, and to perform fault prediction on the memory module based on the probability of an UE occurring in each of the at least one storage array.

[0006] This application also provides a computing device, including: a memory and a processor; the memory for storing a computer program; and the processor coupled to the memory for executing the computer program to perform steps in a memory module failure prediction method.

[0007] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the steps in the memory module failure prediction method.

[0008] In this embodiment, multiple aggregated fault features of the various storage arrays included in the memory module are mined from the error log data of the memory module. These aggregated fault features characterize the fault information of the storage array from multiple dimensions such as rows, columns, and storage units. Machine learning is used to predict memory module faults based on these aggregated fault features of each storage array. This greatly improves the accuracy and efficiency of memory module fault prediction, ensuring the availability, reliability, and serviceability of the memory module. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0010] Figure 1 This is a schematic diagram of an exemplary memory module.

[0011] Figure 2 This is an application scenario diagram applicable to the embodiments of this application;

[0012] Figure 3 A flowchart illustrating a memory module failure prediction method provided in this application embodiment;

[0013] Figure 4 Here is an example data area diagram;

[0014] Figure 5 This is a schematic diagram of the structure of a memory module fault prediction device provided in an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the access relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates that the preceding and following associated objects have an "or" relationship. Furthermore, in the embodiments of this application, "first," "second," "third," etc., are only used to distinguish the content of different objects and have no other special meaning.

[0018] With the increasing frequency of memory access, the failure rate of 8x8 memory modules is significantly higher than that of 4x4 memory modules, greatly impacting the reliability, availability, and serviceability of computer systems. Therefore, it is essential to accurately and efficiently predict the failures of x8 memory modules. To this end, this application provides a memory module failure prediction method, apparatus, computing device, and storage medium. In this application, multiple aggregated failure features of the various storage arrays included in the memory module are mined from the memory module's error log data. These aggregated failure features characterize the failure information of the storage array from multiple dimensions, such as rows, columns, and storage units. Machine learning is used to predict memory module failures based on these aggregated failure features of each storage array. This greatly improves the accuracy and efficiency of memory module failure prediction, ensuring the availability, reliability, and serviceability of the memory module.

[0019] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0020] Figure 1This is a schematic diagram of an exemplary memory module. The following section combines... Figure 1 This section provides a brief overview of the internal structure of memory modules. (See also...) Figure 1 Memory modules typically consist of two memory rows (ranks), each row containing multiple memory chips, such as DRAM (Dynamic Random Access Memory) chips. Each memory chip typically includes multiple memory banks, and each memory bank usually consists of multiple memory cells. A memory cell on a memory bank is uniquely identified by its row and column addresses. These memory cells are arranged in a two-dimensional matrix. Each memory cell can store one or more bits of data. For more information on the internal structure of memory modules, please refer to relevant technical documentation.

[0021] Figure 2 This is an application scenario diagram applicable to an embodiment of this application. See also... Figure 2 First, during the model training phase, the centralized management system collects error log data from each server and stores it in a data warehouse.

[0022] Next, the centralized management system performs data mining on the error log data in the data warehouse to obtain the fault characteristics of each row, each column, each storage unit, and each bit sequence of each storage array.

[0023] Next, the centralized management system aggregates the fault features of each row in each storage array to obtain aggregated fault features at the row level; it aggregates the fault features of each column in each storage array to obtain aggregated fault features at the column level; it aggregates the fault features of each storage cell in each storage array to obtain aggregated fault features at the storage cell level; and it aggregates the fault features of each bit sequence in each storage array to obtain aggregated fault features at the bit level.

[0024] Next, the centralized management system selects multiple storage arrays as sample storage arrays and prepares a training sample set based on these arrays. Each training sample in the training sample set includes multiple aggregated fault features, annotation results, and static features of the sample storage array. The annotation results indicate whether a UE (User Equipment) has occurred or not in the sample storage array. The centralized management system uses the training sample set to train the model and obtain a machine learning model for predicting X8 memory module faults, thus completing the machine learning model training task.

[0025] In practical applications, a centralized management system can deploy trained machine learning models to various servers. Each server then uses these models to predict X8 memory module failures based on local error log data. The centralized management system can also perform X8 memory module failure prediction locally using machine learning models based on error log data uploaded from the servers; there are no restrictions on this. In some application scenarios, when the centralized management system predicts a memory module failure risk on a particular server, it can also issue a migration command to that server, allowing it to migrate data to other servers and ensure data security.

[0026] It is worth noting that centralized management systems include, but are not limited to, distributed server clusters consisting of a single server or multiple servers. Of course, a centralized management system can also be a software module deployed on a distributed server cluster consisting of a single server or multiple servers. Furthermore, Figure 2 The application scenario shown is merely an example, and the embodiments of this application do not limit the application scenario.

[0027] In this embodiment, a machine learning model for fault prediction of X8 memory modules is pre-trained. In some application scenarios, the machine learning model predicts faults in X8 memory modules based on multiple aggregated fault features of the storage array. Therefore, during the model training phase, multiple training samples can be obtained. Each training sample includes multiple aggregated fault features of the sample storage array and their annotation results. The annotation results indicate whether a user experience (UE) has occurred or not in the sample storage array. An initial machine learning model is trained using these multiple training samples to obtain the machine learning model. This model is used to predict the probability of a UE occurring in the storage array and to predict faults in the memory modules containing the storage array based on this probability.

[0028] Specifically, during the training of the machine learning model, in each round of model training, multiple aggregated fault features of the sample storage array can be input into the initial machine learning model to predict the probability of UE occurrence in the sample storage array. A loss function is calculated based on the labeled results of the sample storage array and the predicted probability of UE occurrence. The model parameters of the initial machine learning model are adjusted according to the loss function. If the training round meets the model training termination condition, training stops, and the updated initial machine learning model becomes the final machine learning model. If the training round does not meet the termination condition, model training continues using new training samples until the training round meets the termination condition. The termination condition is set according to the actual situation; for example, the model parameters converge, or the maximum number of training iterations is reached.

[0029] In this application embodiment, no limitation is made on the loss function. The loss function includes, but is not limited to, the logarithmic loss function, the cross-entropy loss function, and the Focal loss function used to solve the data imbalance problem.

[0030] It's worth noting that a well-trained machine learning model can not only predict the probability of a memory module failure (UE) occurring in the storage array, but also predict the failure of the memory modules within the storage array based on this probability. Specifically, the machine learning model compares the probability of a UE occurring with a preset probability threshold. If the probability is greater than or equal to the preset threshold, it confirms that the memory modules within the storage array have failed. If the probability is less than the preset threshold, it confirms that the memory modules within the storage array have not failed.

[0031] In other application scenarios, machine learning models predict the failure of X8 memory modules based on multiple aggregated fault features and static features of the storage array. Static features include, but are not limited to, the device information of the memory module and the device information of the CPU associated with the memory module. The device information of the memory module includes, but is not limited to, its model, bandwidth frequency, and memory capacity. The device information of the CPU includes, but is not limited to, its model, generation, clock speed, and number of cores. Based on this, during the model training phase, multiple training samples can be obtained. Each training sample includes multiple aggregated fault features of the sample storage array and their labeled results. The labeled results indicate whether a user experience (UE) has occurred or not in the sample storage array. An initial machine learning model is trained using these multiple training samples and static features to obtain the machine learning model. This machine learning model is used to predict the probability of a UE occurring in the storage array and to predict the failure of the memory modules containing the storage array based on this probability.

[0032] Specifically, during the training of the machine learning model, in each round of model training, multiple aggregated fault features and static features of the sample storage array can be input into the initial machine learning model to predict the probability of UE occurrence in the sample storage array. A loss function is calculated based on the labeled results of the sample storage array and the predicted probability of UE occurrence. The model parameters of the initial machine learning model are adjusted according to the loss function. If the model training in this round meets the model training termination condition, model training stops, and the updated initial machine learning model is used as the final machine learning model. If the model training in this round does not meet the model training termination condition, model training continues using new training samples until the model training in this round meets the model training termination condition.

[0033] After training the machine learning model, it can be used to predict faults in X8 memory modules. The following section combines... Figure 3 This article introduces a method for predicting faults in X8 memory modules. Figure 3 A flowchart illustrating a memory module fault prediction method provided in an embodiment of this application. See also... Figure 3 The method may include the following steps:

[0034] 301. Obtain the error log data of the memory module. The error log data records information about correctable errors (CEs) that occurred on the memory module within a historical time period.

[0035] 302. Based on the error log data, determine at least one storage array's corresponding first aggregated fault feature representing a row of the storage array experiencing a CE, a second aggregated fault feature representing a column of the storage array experiencing a CE, and a third aggregated fault feature representing a storage cell experiencing a CE.

[0036] 303. Input multiple aggregated fault features corresponding to at least one storage array into a machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage array, and perform fault prediction on the memory module based on the probability of an UE occurring in each of the at least one storage array.

[0037] In this embodiment, for any X8 memory module requiring fault prediction, error log data is first collected. The error log data records information about correctable errors that occurred on the memory module within a historical time period. The historical time period can be flexibly set according to actual application needs, and may include, but is not limited to, the past hour, the past day, and the past week.

[0038] Typically, error log data records detailed information about correctable errors, including but not limited to: memory column information, memory chip information, and row and column addresses of the storage array where the correctable error occurred. By analyzing error log data, it is possible to determine which storage arrays within the memory module experienced correctable errors.

[0039] In this embodiment, for each storage array in at least one storage array within the memory module, error log data associated with that storage array is extracted from the error log data, and data analysis is performed on the error log data of that storage array to obtain multiple aggregated fault features of that storage array. These multiple aggregated fault features include row-level aggregated fault features, column-level aggregated fault features, and storage cell-level aggregated fault features. Further, the multiple aggregated fault features may also include bit-level aggregated fault features. For ease of understanding and differentiation, the row-level aggregated fault features are referred to as the first aggregated fault feature, which represents fault information indicating a cell-level error (CE) in the storage array's rows; the column-level aggregated fault features are referred to as the second aggregated fault feature, which represents fault information indicating a column-level error (CE) in the storage array; the third aggregated fault feature represents fault information indicating a storage cell-level error (CE); and the fourth aggregated fault feature represents fault information indicating a bit-level error (CE).

[0040] In this embodiment, for each storage array, error log data related to each row of the storage array is obtained from the error log data. Analyzing the error log data related to each row yields the fault characteristics of each row, such as the number of error CEs (Error Correction) occurring in each row within a historical time period, which row addresses in each row experienced CEs, and the total number of row addresses experiencing CEs. Aggregating the fault characteristics of each row yields the first aggregated fault characteristics of the storage array. Based on this, as an example, an optional implementation of determining the first aggregated fault characteristics representing the occurrence of CEs in rows of at least one storage array based on the error log data is as follows: For each of the at least one storage arrays, row fault characteristics are determined based on the error log data. These row fault characteristics include the number of error CEs occurring in the row, the number of row addresses, and the address range. Aggregating the row fault characteristics of each row in the storage array yields the first aggregated fault characteristics representing the occurrence of CEs in rows of the storage array.

[0041] In practical applications, when aggregating the row fault characteristics of each row in a storage array, the number of errors that cause CE in each row can be accumulated, averaged, or weighted to obtain the aggregated number of CE errors in the row of the storage array; the number of row addresses that cause CE in each row can be accumulated, averaged, or weighted to obtain the aggregated number of row addresses that cause CE in the row of the storage array; and the address range of row addresses that cause CE in each row can be statistically analyzed to obtain the aggregated address range of row addresses that cause CE in the row of the storage array.

[0042] In practical applications, row fault characteristics can be aggregated for all rows in the storage array, or they can be aggregated for rows that meet specified conditions. Specified conditions include, for example, rows where the number of Complete Error (CE) errors exceeds a specified number. The specified number can be, for example, a number greater than 1.

[0043] In this embodiment, for each storage array, error log data related to each column of the storage array is obtained from the error log data. Analyzing the error log data related to each column yields the fault characteristics of each column, such as the number of error CEs (Error Correction) occurring in each column within a historical time period, which column addresses in each column experienced CEs, and the number of column addresses that experienced CEs. Aggregating the fault characteristics of each column yields a second aggregated fault characteristic of the storage array. Based on this, as an example, determining the second aggregated fault characteristic representing the occurrence of CEs in columns corresponding to at least one storage array based on the error log data includes: for each of the at least one storage arrays, determining the column fault characteristics of each column in the storage array based on the error log data; the column fault characteristics include the number of error CEs occurring in rows, the number of column addresses, and the address range; and aggregating the column fault characteristics of each column in the storage array to obtain the second aggregated fault characteristic representing the occurrence of CEs in columns of the storage array.

[0044] In practical applications, when aggregating the column fault characteristics of each column in a storage array, the number of column CE errors occurring in each column can be accumulated, averaged, or weighted to obtain the aggregated number of column CE errors in the storage array; the number of row addresses where CE occurred in each column can be accumulated, averaged, or weighted to obtain the aggregated number of column addresses where CE occurred in the storage array; and the address range of column addresses where CE occurred in each column can be statistically analyzed to obtain the aggregated address range of column addresses where CE occurred in the storage array.

[0045] In practical applications, column failure characteristics can be aggregated for all columns in the storage array, or aggregated for columns that meet specified conditions. Specified conditions include, for example, columns where the number of Complete Error (CE) errors exceeds a specified number. The specified number can be, for example, a number greater than 1.

[0046] In this embodiment, for each storage array, error log data related to each storage unit of the storage array is obtained from the error log data. Analyzing the error log data related to each storage unit yields the fault characteristics of each storage unit, such as the number of error CEs (Error Correction) occurring in each storage unit within a historical time period and information about the fault bits associated with the CE. Aggregating the fault characteristics of each storage unit yields a third aggregated fault characteristic of the storage array. Based on this, as an example, determining the third aggregated fault characteristic representing the CE of a storage unit corresponding to at least one storage array based on the error log data includes: for each storage unit in each storage array, determining the fault characteristics of the storage unit based on the error log data. The fault characteristics of the storage unit include the number of error CEs occurring in the storage unit, the position of the fault bit associated with the CE in the bit sequence, and the position region to which the fault bit belongs. The position region is either the first position region containing the first N bits in the bit sequence or the second position region containing the last M bits in the bit sequence, where N and M are both positive integers; aggregating the fault characteristics of each storage unit in the storage array yields the third aggregated fault characteristic representing the CE of the storage unit corresponding to the storage array.

[0047] Typically, in a single access to an X8 memory module, a memory chip transmits multiple bit sequences in batches, with each bit sequence consisting of 8 bits. Let's assume a memory chip transmits 8 bit sequences in batches, denoted as Burst0, Burst1, Burst2, Burst3, Burst4, Burst5, Burst6, and Burst7. Each bit in a bit sequence corresponds to a data transmission channel; let's assume the 8 data transmission channels corresponding to the 8 bits in the bit sequence are denoted as DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7. The same bit positions in different Bursts share a group of DQs. The memory data returned by an X8 memory module in a single access can be represented as two data regions: one consisting of the first 4 bits of each bit sequence and another consisting of the last 4 bits of each bit sequence. See also... Figure 4 The two data regions are 4DQ data region A and 4DQ data region B. Black dots represent bits that have experienced CE errors, and white dots represent bits that have not experienced CE errors.

[0048] In practical applications, a single Burst or a bit on the same DQ is prone to simultaneous CE errors. For X4 memory modules, these errors can be corrected. However, for X8 memory modules, if a Burst bit that causes a CE error is distributed across two data areas, a UE error is likely to occur, causing the X8 memory module to fail and greatly reducing the reliability of the X8 memory.

[0049] Therefore, in this embodiment, when analyzing the fault characteristics of a memory cell, it is necessary to analyze not only the number of error CEs (Error Correction) occurring in the memory cell, but also the position of the faulty bit associated with the CE in the bit sequence and the position region to which the faulty bit belongs. The position region is either the first position region containing the first N bits in the bit sequence or the second position region containing the last M bits in the bit sequence. N and M are flexibly set as needed. For example, both N and M are 4; or N is 3 and M is 5, etc. Figure 4 For example, the black dots are the fault bits associated with the CE (Cycles and Errors) occurrence in the memory cell. The first location area to which the fault bit belongs is the 4DQ data area A, and the second location area to which the fault bit belongs is the 4DQ data area B.

[0050] In practical applications, when aggregating the fault characteristics of each storage cell in a storage array, the number of CE (Error Detection) occurrences in each storage cell can be accumulated, averaged, or weighted to obtain the aggregated number of CE occurrences for the storage cells of the storage array. Furthermore, the positions of the fault bits associated with each CE occurrence in the bit sequence and the location regions to which the fault bits belong are statistically analyzed to obtain the aggregated number of CE occurrences for each bit and the aggregated number of CE occurrences for each location region. In this embodiment, CE information based on each location region can more accurately predict UE (User Equipment) errors.

[0051] In this embodiment, for each storage array, error log data related to each bit sequence provided by the storage array is obtained from the error log data. Analyzing the error log data related to each bit sequence yields the fault characteristics of each bit sequence, such as information about the faulty bit associated with a CE (Error Execution) in the bit sequence. Aggregating the fault characteristics of each bit sequence yields a fourth aggregated fault characteristic for the storage array. Based on this, as an example, determining the fourth aggregated fault characteristic representing a CE in a bit corresponding to at least one storage array based on the error log data includes: for each storage array, determining the fault characteristics of each bit sequence provided by the storage array based on the error log data; the fault characteristics of the bit sequence include the position of the faulty bit that caused the CE in the bit sequence and the location region to which the faulty bit's position belongs; and aggregating the fault characteristics of each bit sequence to obtain the fourth aggregated fault characteristic representing a CE in a bit corresponding to the storage array.

[0052] In practical applications, after obtaining the fault characteristics of each bit sequence, the number of errors resulting in CE (Complete Error) for each bit and the number of errors resulting in CE for each location region can be counted. These two counts are then used as the fourth aggregated fault characteristic to characterize bit CE occurrence. (See also...) Figure 4 For each bit sequence, if a faulty bit (CE) occurs, the DQ and data region to which the faulty bit belongs are determined. By statistically analyzing the DQ and data region to which the faulty bit belongs, the number of CE errors for each DQ and the number of CE errors for each data region can be obtained.

[0053] In this embodiment, after obtaining multiple aggregated fault features corresponding to each storage array, a machine learning model is used to predict faults based on these features. In practical applications, if the machine learning model predicts faults solely based on the aggregated fault features of the storage arrays, then multiple aggregated fault features corresponding to at least one storage array can be input into the machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage arrays, and fault prediction of the memory modules can be performed based on the probability of an UE occurring in each of the at least one storage arrays.

[0054] In practical applications, if a machine learning model combines aggregated fault features and static features of the storage array for fault prediction, then the static features and multiple aggregated fault features corresponding to at least one storage array are input into the machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage array, and fault prediction is performed on the memory module based on the probability of an UE occurring in each of the at least one storage array. The static features include at least one of the device information of the memory module and the device information of the central processing unit associated with the memory module.

[0055] In this embodiment, when the machine learning model predicts memory module failures based on the probability of each memory array experiencing a UE (User Execution) in at least one storage array, it confirms a memory module failure if the probability of a UE in one storage array is greater than or equal to a preset probability threshold. If no storage array has a UE probability less than the preset probability threshold, the memory module is confirmed not to have failed. Alternatively, if more than a first specified number of storage arrays have a UE probability greater than or equal to the preset probability threshold, the memory module is confirmed to have failed. If no more than a first specified number of storage arrays have a UE probability less than the preset probability threshold, the memory module is confirmed not to have failed. Here, the first specified number is an integer greater than 1. Alternatively, if more than or equal to a second specified number of memory chips in a storage array have a UE probability greater than or equal to the preset probability threshold, the memory module is confirmed to have failed. If less than a second specified number of memory chips in a storage array have a UE probability greater than or equal to the preset probability threshold, the memory module is confirmed not to have failed. Of course, the specific implementation method of the machine learning model predicting memory module failures based on the probability of each memory array experiencing a UE is not limited. In practical applications, when a memory module failure is predicted, a warning message can be output to indicate the impending failure. Maintenance personnel then use this message to troubleshoot and pinpoint the cause of the memory module failure. For example, the maintenance personnel might remove the memory module from the motherboard slot, clean its gold contacts, remove dust from the slot, and clean the slot itself before reinserting the memory module. Next, they collect the error log data of the reinserted memory module. If the error log data predicts that the memory module will not fail, then the problem lies in poor contact between the memory module and the motherboard slot. If the error log data still predicts that the memory module will fail, then the problem is not related to poor contact between the memory module and the motherboard slot. As another example, the memory module might be removed and inserted into a different memory slot to rule out damage to the previous slot. The error log data for the memory module in the different slot is then collected. If the error log data predicts that the memory module will not fail, then the previous memory slot was damaged. If the error log data still predicts that the memory module will fail, it indicates that the memory slot into which the memory module was previously inserted was not damaged, but rather the memory module itself is damaged. The technical solution provided in this application extracts multiple aggregated fault features from the error log data of the memory module, representing the fault information of the storage array from multiple dimensions such as rows, columns, and storage units. Machine learning is then used to predict memory module failures based on these aggregated fault features. This significantly improves the accuracy and efficiency of memory module failure prediction, ensuring the availability, reliability, and serviceability of the memory module.

[0056] Figure 5 This is a schematic diagram of a memory module fault prediction device provided in an embodiment of this application. Figure 5 As shown, the device may include:

[0057] The acquisition module 51 is used to acquire the error log data of the memory module. The error log data records information about correctable errors (CEs) that occurred on the memory module within a historical time period.

[0058] The feature aggregation module 52 is used to determine multiple aggregated fault features corresponding to at least one storage array based on error log data. The multiple aggregated fault features include a first aggregated fault feature characterizing a row of the storage array to experience a CE, a second aggregated fault feature characterizing a column of the storage array to experience a CE, and a third aggregated fault feature characterizing a storage cell to experience a CE.

[0059] The prediction module 53 is used to input multiple aggregated fault features corresponding to at least one storage array into a machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage array, and to perform fault prediction on the memory module based on the probability of an UE occurring in each of the at least one storage array.

[0060] Optionally, when the feature aggregation module 52 determines the first aggregated fault feature representing the occurrence of CE in a row of at least one storage array based on the error log data, it is specifically used to: for each of the at least one storage arrays, determine the row fault features of each row in the storage array based on the error log data, the row fault features including the number of errors in which CE occurs in the row, the number of addresses in the row address, and the address range; and perform aggregation processing on the row fault features of each row in the storage array to obtain the first aggregated fault feature representing the occurrence of CE in a row of the storage array.

[0061] Optionally, when the feature aggregation module 52 determines the second aggregated fault features representing the occurrence of CE in the columns of at least one storage array based on the error log data, it is specifically used to: for each of the at least one storage arrays, determine the column fault features of each column in the storage array based on the error log data, the column fault features including the number of errors in the row that cause CE, the number of addresses of the column address, and the address range; and perform aggregation processing on the column fault features of each column in the storage array to obtain the second aggregated fault features representing the occurrence of CE in the columns of the storage array.

[0062] Optionally, when the feature aggregation module 52 determines the third aggregated fault feature representing the occurrence of CE in each of the at least one storage array corresponding to the storage cell based on the error log data, it is specifically used to: for each storage cell in each storage array, determine the fault feature of the storage cell based on the error log data. The fault feature of the storage cell includes the number of errors in which the storage cell has CE, the position of the fault bit associated with the occurrence of CE in the bit sequence, and the position region to which the position of the fault bit belongs. The position region is either the first position region where the first N bits in the bit sequence are located or the second position region where the last M bits in the bit sequence are located, where N and M are both positive integers; and perform aggregation processing on the fault features of each storage cell in the storage array to obtain the third aggregated fault feature representing the occurrence of CE in the storage cell corresponding to the storage array.

[0063] Further optionally, the multiple aggregated fault features also include a fourth aggregated fault feature characterizing the occurrence of CE in a bit. When the feature aggregation module 52 determines the fourth aggregated fault feature characterizing the occurrence of CE in a bit corresponding to at least one storage array based on the error log data, it is specifically used to: for each storage array, determine the fault features of each bit sequence provided by the storage array based on the error log data. The fault features of the bit sequence include the position of the faulty bit that caused CE in the bit sequence and the location region to which the position of the faulty bit belongs; and perform aggregation processing on the fault features of each bit sequence to obtain the fourth aggregated fault feature characterizing the occurrence of CE in a bit corresponding to the storage array.

[0064] Optionally, when the prediction module 53 inputs multiple aggregated fault features corresponding to each of the at least one storage array into the machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage array, it is specifically used to: input multiple aggregated fault features and static features corresponding to each of the at least one storage array into the machine learning model to predict the probability of an uncorrectable UE occurring in each of the at least one storage array; wherein, the static features include at least one of the device information of the memory module and the device information of the central processing unit associated with the memory module.

[0065] Further optionally, the above apparatus further includes: a training module for acquiring multiple training samples, each training sample including multiple aggregated fault features of the sample storage array and their annotation results, the annotation results representing whether the sample storage array has experienced a UE or not; training an initial machine learning model using the multiple training samples to obtain a machine learning model, the machine learning model predicting the probability of a UE occurring in the storage array and performing fault prediction on the memory module where the storage array is located based on the probability of a UE occurring in the storage array.

[0066] Figure 5 The device shown can perform Figure 3The implementation principle and technical effects of the method shown will not be elaborated further. Regarding the above embodiments... Figure 5 The specific methods by which each module and unit of the device performs its operations have been described in detail in the embodiments of the method, and will not be elaborated here.

[0067] It should be noted that the execution subject of each step of the method provided in the above embodiments can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 301 to 303 can be device A; or the execution subject of steps 301 and 302 can be device A, and the execution subject of step 303 can be device B; and so on.

[0068] Furthermore, in some of the processes described in the above embodiments and accompanying drawings, multiple operations appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or they may be executed in parallel. The operation numbers, such as 301, 302, etc., are merely used to distinguish different operations and do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first" and "second" in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0069] Figure 6 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 6 As shown, the computing device includes: a memory 61 and a processor 62;

[0070] Memory 61 is used to store computer programs and can be configured to store various other data to support operation on the computing platform. Examples of this data include instructions for any application or method operating on the computing platform, contact data, phone book data, messages, pictures, videos, etc.

[0071] The memory 61 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0072] The processor 62, coupled to the memory 61, is used to execute a computer program in the memory 61 for: acquiring error log data of the memory module, the error log data recording information about correctable errors (CEs) occurring in the memory module within a historical time period; determining, based on the error log data, a first aggregated fault feature representing a row-level CE, a second aggregated fault feature representing a column-level CE, and a third aggregated fault feature representing a memory cell-level CE for each of at least one storage array; inputting the aggregated fault features corresponding to each of the at least one storage array into a machine learning model to predict the probability of an uncorrectable error (UE) occurring in each of the at least one storage array, and performing fault prediction on the memory module based on the probability of an UE occurring in each of the at least one storage array.

[0073] Furthermore, such as Figure 6 As shown, the computing device also includes other components such as a communication component 63, a display 64, a power supply component 65, and an audio component 66. Figure 6 The diagram only shows some components and does not mean that the computing device includes only these components. Figure 6 The components shown. Additionally... Figure 6 The components within the dashed box are optional, not mandatory, and their specific requirements depend on the form factor of the computing device. The computing device in this embodiment can be a desktop computer, laptop computer, smartphone, or IoT (Internet of Things) device, or a server-side device such as a conventional server, cloud server, or server array. If the computing device in this embodiment is implemented as a desktop computer, laptop computer, or smartphone, it may include... Figure 6 The components within the dashed box; if the computing device in this embodiment is implemented as a conventional server, cloud server, or server array, etc., it may be omitted. Figure 6 The component within the dashed box.

[0074] For a detailed description of the implementation process of each action by the processor, please refer to the relevant descriptions in the foregoing method embodiments or device embodiments, which will not be repeated here.

[0075] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed, can perform the steps that can be executed by a computing device in the above method embodiments.

[0076] Accordingly, this application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, enable the processor to perform the steps that can be executed by a computing device in the above method embodiments.

[0077] The aforementioned communication components are configured to facilitate wired or wireless communication between the device containing the communication components and other devices. The device containing the communication components can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G / LTE, 5G, or combinations thereof. In one exemplary embodiment, the communication components receive broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication components also include a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wide Band (UWB), Bluetooth (BT), and other technologies.

[0078] The aforementioned display includes a screen, which may include a Liquid Crystal Display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation.

[0079] The aforementioned power supply components provide power to various components within the device in which they reside. These power supply components may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device in which they reside.

[0080] The aforementioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) configured to receive external audio signals when the device containing the audio component is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals can be further stored in memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0081] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0083] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0084] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (central processing unit, CPU), input / output interfaces, network interfaces, and memory.

[0086] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0087] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined in this article, computer-readable media do not include transient media, such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0089] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for predicting memory module failures, characterized in that, The memory module includes at least one storage array, the storage array includes multiple storage cells, and the method includes: Obtain the error log data of the memory module, which records information about correctable errors (CEs) that occurred on the memory module within a historical time period; Based on the error log data, multiple aggregated fault features corresponding to each of the at least one storage array are determined, wherein the multiple aggregated fault features include a first aggregated fault feature characterizing a row of the storage array to experience a CE, a second aggregated fault feature characterizing a column of the storage array to experience a CE, and a third aggregated fault feature characterizing a storage cell to experience a CE. Multiple aggregated fault features and static features corresponding to each of the at least one storage array are input into a machine learning model to predict the probability of each of the at least one storage arrays experiencing an uncorrectable UE error, and to predict the fault of the memory module based on the probability of each of the at least one storage arrays experiencing a UE error, wherein the static features include at least one of the device information of the memory module and the device information of the central processing unit associated with the memory module.

2. The method according to claim 1, characterized in that, Based on the error log data, determine the first aggregated fault characteristic representing the occurrence of CE (Error Detection) in the rows of at least one storage array, including: For each of at least one storage array, row fault characteristics of each row in the storage array are determined based on the error log data. The row fault characteristics include the number of CE errors that occur in the row, the number of addresses in the row address, and the address range. The row fault features of each row in the storage array are aggregated to obtain a first aggregated fault feature characterizing the occurrence of CE in a row of the storage array.

3. The method according to claim 1, characterized in that, Based on the error log data, determine at least one second aggregated fault characteristic representing the occurrence of a CE (Error Detection) in a column corresponding to each storage array, including: For each of at least one storage array, the column fault characteristics of each column in the storage array are determined based on the error log data. The column fault characteristics include the number of CE errors that occur in the row, the number of column addresses, and the address range. The column fault features of each column in the storage array are aggregated to obtain a second aggregated fault feature characterizing the occurrence of CE in the column of the storage array.

4. The method according to claim 1, characterized in that, Based on the error log data, at least one third aggregated fault characteristic representing a CE (Error Detection) event is determined for each corresponding storage cell in at least one storage array, including: For each storage cell in each storage array, the fault characteristics of the storage cell are determined based on the error log data. The fault characteristics of the storage cell include the number of errors where the storage cell experiences a CE, the position of the fault bit associated with the CE in the bit sequence, and the location region to which the fault bit belongs. The location region is either the first location region where the first N bits in the bit sequence are located or the second location region where the last M bits in the bit sequence are located, where N and M are both positive integers. The fault characteristics of each storage cell in the storage array are aggregated to obtain the third aggregated fault characteristic of the storage cell corresponding to the storage array, which represents the occurrence of CE (Complete Error).

5. The method according to claim 1, characterized in that, The plurality of aggregated fault features also includes a fourth aggregated fault feature characterizing bit CE (Complete Error Detection). The fourth aggregated fault feature characterizing bit CE is determined based on the error log data for at least one storage array, including: For each storage array, the fault characteristics of each bit sequence provided by the storage array are determined based on the error log data. The fault characteristics of the bit sequence include the position of the faulty bit where the CE occurred in the bit sequence and the location region to which the position of the faulty bit belongs. The fault features of each bit sequence are aggregated to obtain the fourth aggregated fault feature representing the occurrence of CE (Complete Error) in the corresponding bit of the storage array.

6. The method according to claim 1, characterized in that, Also includes: Multiple training samples are obtained, each training sample including multiple aggregated fault features of the sample storage array and their annotation results, wherein the annotation results characterize whether the sample storage array has experienced a UE or not. An initial machine learning model is trained using multiple training samples to obtain a machine learning model. The machine learning model is used to predict the probability of a UE (User Equipment) occurring in the storage array and to predict the failure of the memory modules where the storage array is located based on the probability of a UE occurring in the storage array.

7. A memory module fault prediction device, characterized in that, The memory module includes at least one storage array, the storage array includes multiple storage cells, and the device includes: The acquisition module is used to acquire the error log data of the memory module, wherein the error log data records information about correctable errors (CEs) that occurred on the memory module within a historical time period; The feature aggregation module is used to determine multiple aggregated fault features corresponding to at least one storage array based on the error log data. The multiple aggregated fault features include a first aggregated fault feature characterizing a row of the storage array to experience a CE (Error Execution) event, a second aggregated fault feature characterizing a column of the storage array to experience a CE event, and a third aggregated fault feature characterizing a storage cell to experience a CE event. The prediction module is used to input multiple aggregated fault features and static features corresponding to each of the at least one storage array into a machine learning model to predict the probability of each of the at least one storage arrays experiencing an uncorrectable UE error, and to perform fault prediction on the memory module based on the probability of each of the at least one storage arrays experiencing a UE error, wherein the static features include at least one of the device information of the memory module and the device information of the central processing unit associated with the memory module.

8. A computing device, characterized in that, include: Memory and processor; The memory is used to store computer programs; The processor is coupled to the memory for executing the computer program to perform the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it causes the processor to perform the steps of the method according to any one of claims 1-6.

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