DRAM-less recovery from hmb loss
By identifying the HMB connection loss through the controller of the data storage device, loading and updating the FTL table, the instability of the data storage device caused by the HMB loss was resolved, and safe recovery and stable operation were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANDISK TECH
- Filing Date
- 2022-08-25
- Publication Date
- 2026-07-21
Smart Images
Figure CN115840661B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application is a continuation-in-part of co-pending U.S. Patent Application Serial No. 17 / 479,795, filed on September 20, 2021, which is incorporated herein by reference. Background Technology Technical Field
[0004] The embodiments disclosed herein relate generally to DRAM-free data storage devices, such as DRAM-free solid-state drives (SSDs), and more specifically, to recovery from loss of host memory buffer (HMB).
[0005] Description of related fields
[0006] A portion of the host device's Dynamic Random Access Memory (DRAM) can be utilized by the data storage device to store information that would typically be stored on the data storage device's DRAM. A portion of the host device's DRAM can be a host memory buffer (HMB). The HMB is provided by the host device to the data storage device, allowing the data storage device to access, write to, and read from the HMB without host device interaction. Therefore, data storage devices can be manufactured with less DRAM or even no DRAM to reduce their cost.
[0007] However, the amount of control data that the controller of the data storage device needs to retain will not decrease. Therefore, control data can be stored on the HMB or on the memory device of the data storage device. Accessing the HMB, retrieving data from the HMB, and writing data to the HMB is faster than accessing the memory device, retrieving data from the memory device, and writing data to the memory device. However, since the data stored in the HMB is external to the data storage device, a viable copy of the data can be stored on the memory device in case of power failures, connectivity problems between the data storage device and the HMB, etc. Furthermore, since the HMB belongs to the host device, the host device can reclaim the DRAM area allocated to the HMB at any time. In such cases, the data storage device must be able to recover safely without causing the host device to time out.
[0008] Therefore, there is a need in this field for recovery from HMB loss. Summary of the Invention
[0009] This disclosure relates generally to DRAM-free data storage devices, such as DRAM-free solid-state drives (SSDs), and more specifically to recovery from HMB loss. A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-free. The controller is configured to: determine that a connection to the host memory buffer (HMB) of the host device has been lost; load a current copy of a flash translation layer (FTL) table from the memory device; generate one or more updates to the current copy of the FTL table; and re-enable command fetching. The controller is further configured to flag one or more commands in a command database with an error status during the determination. After re-establishing a connection, the controller is further configured to: copy the FTL table from the memory device to the HMB; execute commands; save the FTL table differences between the HMB and the memory device; and update the FTL table in the memory device.
[0010] In one embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: determine if a connection to the host memory buffer (HMB) of the host device has been lost; load the latest copy of the Flash Translation Layer (FTL) table from the memory device; generate one or more updates to the latest copy of the FTL table; and re-enable command fetching.
[0011] In another embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: determine that the connection between the controller and the host memory buffer (HMB) of the host device has been restored; copy a flash translation layer (FTL) table from the memory device to the HMB, wherein the copying occurs after the connection between the controller and the HMB has been restored; and execute one or more commands stored in a command database.
[0012] In another embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: initially receive a command from a host device; send an error indication with a retry suggestion to the host device for the command; receive the command again from the host device; and execute the command. The controller is further configured to load a flash translation layer (FTL) table from the memory device between sending the error indication and executing the command. Attached Figure Description
[0013] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.
[0014] Figure 1A and Figure 1B This is a schematic block diagram illustrating a storage system according to certain embodiments, wherein the data storage device can be used as a storage device for the host device.
[0015] Figure 2A This is a schematic diagram illustrating a data storage device with DRAM ownership according to certain implementation schemes.
[0016] Figure 2B This is based on certain implementation schemes demonstrating ownership of HMB. Figure 2A A schematic diagram of a data storage device.
[0017] Figure 3 This is a schematic diagram of the NVMe command flow according to certain implementation schemes.
[0018] Figure 4 This is a schematic block diagram illustrating a storage system according to certain embodiments, wherein the data storage device can be used as a storage device for the host device.
[0019] Figure 5 This is a flowchart illustrating a method for executing commands from the hardware side and the firmware side according to certain implementation schemes.
[0020] Figure 6A This is a flowchart illustrating a method for issuing host commands according to certain implementation schemes.
[0021] Figure 6B This is a flowchart illustrating a method for handling HMB loss by a data storage device according to certain implementation schemes.
[0022] Figure 6C This is a flowchart illustrating a method for power-on self-test booting of a data storage device according to certain implementation schemes.
[0023] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation
[0024] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.
[0025] This disclosure relates generally to DRAM-free data storage devices, such as DRAM-free solid-state drives (SSDs), and more specifically to recovery from HMB loss. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to: determine that a connection to the host memory buffer (HMB) of the host device has been lost; load a current copy of a flash translation layer (FTL) table from the memory device; generate one or more updates to the current copy of the FTL table; and re-enable command fetching. The controller is further configured to flag one or more commands in a command database with an error status during the determination. After re-establishing a connection, the controller is further configured to: copy the FTL table from the memory device to the HMB; execute commands; save the FTL table differences between the HMB and the memory device; and update the FTL table in the memory device.
[0026] Figure 1AA schematic block diagram of a storage system 100 according to some embodiments is shown, in which a host device 104 communicates with a data storage device 106. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host DRAM 138, which includes a host memory buffer (HMB) 140. The HMB 140 is a portion of the host DRAM 138 allocated for use by a controller 108 of the data storage device 106. The HMB 140 may store control information, metadata, parity data, error correction codes, and other data that may typically be stored in the controller 108 memory or similar memory. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured to collectively serve as a low-cost / independent disk (RAID) redundant array of high-capacity storage devices for the host device 104.
[0027] Host device 104 can store data to and / or retrieve data from one or more storage devices (such as data storage device 106). Figure 1A As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.
[0028] Data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, and a write buffer 116. In some examples, data storage device 106 may include components not shown for clarity. Figure 1AAdditional components are shown in the diagram. For example, data storage device 106 may include a printed circuit board (PCB) to which components of data storage device 106 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of data storage device 106, etc. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini cards, MiniPCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of host device 104.
[0029] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to controller 108, thereby providing an electrical connection between host device 104 and controller 108, allowing data exchange between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1A As shown, power supply 111 can receive power from host device 104 via interface 114.
[0030] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data and a message from controller 108 instructing the memory cell to store the data. Similarly, a memory cell may receive a message from controller 108 instructing the memory cell to retrieve data. In some examples, each memory cell in the memory cell may be referred to as a die. In some examples, NVM 110 may include multiple dies (e.g., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).
[0031] In some examples, each memory cell may include any type of non-volatile memory device, such as flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.
[0032] NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory devices may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistors for each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each of the multiple dies comprising multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.
[0033] Power supply 111 can provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can use power provided by external devices such as host device 104 to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 may include one or more power storage components configured to power one or more components when operating in a shutdown mode, such as when power is stopped from external devices. In this way, power supply 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electricity that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of such one or more power storage components. In other words, as the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.
[0034] Volatile memory 112 can be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1A As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), static RAM (SRAM), flip-flops, and registers.
[0035] Data storage device 106 includes a controller 108, which may include volatile memory 112. For example, controller 108 may include SRAM. Furthermore, controller 108 can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to NVM. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operating characteristic of storage system 100 and store that at least one operating characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores the data associated with the write command in internal memory or write buffer 116 before sending the data to NVM 110.
[0036] Figure 1B This is a schematic block diagram illustrating a storage system 150 according to certain embodiments, wherein data storage device 106 can be used as a storage device for host device 104. For simplicity purposes, Figure 1A Common components between storage system 100 and storage system 150 may be indexed by the same reference numerals. Storage system 150 is similar to... Figure 1A The storage system is shown in the diagram. However, in storage system 150, data storage device 152 includes dynamic RAM (DRAM) 154, while in storage system 100, data storage device 106 is DRAM-free. In the embodiments described herein, in the presence of DRAM 154 (such as in storage system 150), data and pointers corresponding to one or more commands may be temporarily stored in DRAM 154 before being processed. It should be understood that the previously exemplified elements that can be stored in DRAM 154 are not intended to be limiting. For example, DRAM 154 may also store data management tables, such as logic-to-physical (L2P) tables.
[0037] However, in the embodiments described herein, in the absence of DRAM 154 (such as in storage system 100, where data storage device 106 has no DRAM), data and pointers corresponding to one or more commands may be temporarily stored in HMB 140 or in other volatile memory such as SRAM. Furthermore, Figure 1B Examples of volatile memory 112 may further include, but are not limited to, DRAM and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Therefore, data storage device 106 may be referred to as a DRAM-free data storage device.
[0038] Figure 2A This is a schematic diagram illustrating a data storage device 202 with DRAM ownership, according to certain embodiments. The data storage device 202 may be... Figure 1B The data storage device 152. The data storage device 202 includes a DRAM 204 and a DRAM controller 206, the DRAM being... Figure 1B The DRAM 154, the DRAM controller can be Figure 1B The controller 108. It should be understood that DRAM 204 can be any applicable volatile memory, such as SRAM. When DRAM 204 experiences a fatal failure, such as a double fault detected by SECDED, the failure is a reset of the data storage device 202 initiated by the DRAM controller 206. Therefore, the DRAM controller 206 has control over DRAM 204.
[0039] Figure 2B This is based on certain implementation schemes demonstrating ownership of HMB. Figure 2A A schematic diagram of data storage device 202. The data storage device includes a PCIe, MAC, and PHY module 254, which may be coupled to an HMB controller 256. Figure 1A Interface 114. PCIe, MAC, and PHY modules 254 are coupled to host devices (such as...) Figure 1A The host device 104 has a host PCIe interface and a host DRAM 252, where the host DRAM includes an HMB. When working with the host PCIe interface and the host DRAM 252's HMB, the host device 104 can revoke the HMB controller 256's access to the HMB, or the connection between the HMB and the HMB controller 256 can be broken. When the connection is broken, the data storage device 202 must be able to recover safely without causing the host device 104 to experience a "blue screen" effect or timeout scenario. Recovery can be completed in cases of SECDED, authentication errors, link problems, and other situations that invalidate DRAM data. A "blue screen" effect or timeout scenario can be caused by the host device 104 not responding at the PCIe level or by commands timed out at the NVMe level.
[0040] Figure 3 This is a schematic diagram of an NVMe command stream 300 according to certain implementation schemes. The NVMe command stream 300 includes a host device 302 and a data storage device 304, the host device being... Figure 1A The host device 104, the data storage device may be Figure 1A The data storage device 106. When the host device 302 generates a read command or a write command, the read command or write command is stored in the commit queue of the host device 302. This commit queue can be implemented in the host DRAM, such as... Figure 1A The host DRAM 138. The host device 302 operates a submission queue doorbell of the data storage device 304, which instructs the data storage device 304, or more specifically, the controller of the data storage device 304 (such as controller 108), that the submission queue has a queuing command.
[0041] Data storage device 304 responds by reading a command from the commit queue of host device 302. In one example, this command is a read command, causing the data storage device 304 to read from a memory device (such as...) Figure 1AThe NVM 110 reads the relevant data and transmits it back to the host device 302. After completing the read command, the controller 108 of the data storage device 304 generates a completion message for the completed command and writes the completion message to the completion queue of the host device 302, which may reside in the host DRAM 138. The data storage device 304 also sends an interrupt message to the host device 302. Upon receiving both the completion message and the interrupt message, the host device 302 indicates that the command has been completed. The host device 302 confirms the completion of the command by running the command completion queue doorbell of the data storage device 304.
[0042] Figure 4 This is a schematic block diagram illustrating a storage system 400 according to certain embodiments, wherein data storage device 412 can be used as a storage device for host device 402. Aspects of the storage system 400 may be similar to... Figure 1A The storage system 100 is configured such that the data storage device 412 is a DRAM-free storage device. It should be understood that the storage system 400 may include additional components and streams not shown for simplification purposes. The host device 402 includes a host DRAM 404 and a host central processing unit (CPU) 410. The host DRAM 404 includes a command queue 406 and a data queue 408, the command queue including a submission queue and a completion queue. The host CPU 410 is configured to process at least interrupt messages received from an interrupt manager 428 of the data storage device 412, which may be an interrupt state machine. The command queue 406 stores commands to be retrieved by the controller 414 of the data storage device 412 and completion messages sent by the completion manager 426 of the controller 414, which may be a completion state machine.
[0043] Data storage device 412 includes controller 414 and NVM 438, the NVM being... Figure 1A The NVM 110. Controller 414 includes a PCIe protocol interface 416, a control path 418, a command database 422, and a data path 424. The PCIe protocol interface 416 is configured to retrieve data and commands from host DRAM 404 and send data, completion messages, and interrupt messages to host device 402. When the PCIe protocol interface 416 retrieves a command from command queue 406, the command is sent to control path 418, where it is received at processor 420. Simultaneously, the command is passed to command database 422. After processor 420 processes and analyzes the command, control path 418 generates a request for command execution to data path 424.
[0044] Command data is transferred from data 408 to PCIe protocol interface 416, where PCIe interface 416 passes the data to Direct Memory Access (DMA) 430. DMA 430 can be configured to indirectly access NVM 438 via encoder / decoder 432, error correction code (ECC) engine 434, and flash interface module (FIM) 436 or controller 414's internal memory (such as SRAM). Storage system 400 includes data storage devices with DRAM (such as... Figure 1B In one embodiment of the data storage device 152, DMA 430 may be configured to access DRAM 154. Data is passed to encoder / decoder 432, which may be a separate component in other embodiments.
[0045] The encoder / decoder 432 may include logic components for protecting data from errors or logic components for correcting errors in the data when reading data from the NVM 438. For example, the encoder in the encoder / decoder 432 encodes data to be stored in the NVM 438, and the decoder in the encoder / decoder 432 decodes data retrieved from the NVM 438. The encoded data may include data shaping and data encryption. The encoded data is passed from the encoder / decoder 432 to the ECC engine 434. The ECC engine 434 programs ECC data into the encoded data so that when data is read from the NVM, the ECC data can be used to correct errors. In some embodiments, the data path 424 also includes a low-density parity check (LDPC) engine and / or an XOR parity check engine. The data is then passed to the FIM 436, which schedules and programs the data to the NVM 438.
[0046] When a read command is executed, FIM 436 retrieves the relevant data from NVM 438, and ECC engine 434 corrects any errors within its capabilities before passing the data to the decoder in encoder / decoder 432 for decoding / decryption. The data is then transferred to DMA and sent to host DRAM 404 via PCIe protocol interface 416. When the data is transferred to host DRAM, completion manager 426 generates a completion message and sends it to the completion queue of command queue 406. Similarly, interrupt manager 428 generates an interrupt message, which is sent to host CPU 410 to notify host CPU 410 that a completion message has been published to the command queue.
[0047] If no error occurs during data reading in data path 424, the read command in command database 422 is updated with a data transfer success indicator. However, if an error occurs during data reading in data path 424, the read command in command database 422 is updated with the data transmitted with the error indicator.
[0048] Figure 5 This is a flowchart illustrating a method 500 for executing commands from a hardware side 550 and a firmware side 560 according to certain embodiments. Method 500 may be... Figure 4 The controller 414 is implemented. Therefore, for illustrative purposes, various aspects of the storage system 400 may be referenced in the description herein.
[0049] At block 502, controller 414 receives commands from host device 402. Commands may be retrieved from command queue 406, or more specifically, from the submission queue of command queue 406. At block 504, processor 420 retrieves the namespace and host logical block address (LBA) associated with the retrieved command. At block 506, controller 414 retrieves the information stored in the HMB (such as...) Figure 1A The translation table (e.g., flash translation layer (FTL) table) is stored in the HMB140 or in the NVM 438. In implementations where the data storage device includes DRAM (such as... Figure 1B The translation table can optionally be stored in DRAM 154, in a data storage device 152. In some examples, the translation table may be stored in DRAM or HMB, as the access time of NVM 438 may be too long to meet performance requirements. Therefore, controller 414 can obtain the relevant translation table from HMB, or in implementations where the data storage device includes DRAM (such as...). Figure 1B The data storage device 152) retrieves the relevant translation table from the DRAM, where the relevant portions of the translation table are cached. At block 506, the processor 420 uses the retrieved translation table to calculate the relevant location associated with the retrieved command on the NVM 438. At block 508, the firmware side 560 triggers the hardware engine of the hardware side 550.
[0050] At box 510, controller 414 determines whether the command has completed successfully. If the command has completed successfully at box 510, the hardware (such as completion manager 426) sends a completion message back to host device 402 at box 512. However, if the command has not completed successfully at box 510, the firmware sends a completion failure message to the host device. The completion failure message may include error information associated with the failed command. The firmware (e.g., processor 420) may be responsible for triggering the hardware engine (e.g., data path 424).
[0051] Figure 6A This illustrates a host device (such as...) according to certain implementation schemes. Figure 4 The flowchart illustrates a method 600 for issuing host commands from the host device 402. Method 600 can be performed by... Figure 4 The controller 414 is implemented. Therefore, for illustrative purposes, various aspects of the storage system 400 may be referenced in the description herein.
[0052] At box 602, host device 402 issues a command. The command may be stored in a submission queue, where host device 402 sends a doorbell message to data storage device 412 to notify data storage device 412 that the submission queue has a queued command to be retrieved. At box 604, host device 402 determines whether the command has been successfully completed. For example, completion manager 426 of controller 414 may issue a completion message with a success indicator or an error indicator to host device 402 in response to executing the retrieved command. If the command has not been successfully completed, host device 402 retryes the command at box 606 by resending it (e.g., ringing another doorbell). At box 608, host device 402 determines whether the retry command has been successfully completed.
[0053] If the command has completed successfully at box 604 or box 608, method 600 returns to box 602. However, if the command has not completed successfully at box 608, then at box 610, host device 402 determines whether the retry limit for the command has been reached. For example, the retry limit could be one retrieval. It should be understood that the retry limit can be any positive integer optimized or tuned for system performance. In some examples, controller 414 may receive an indication to prepare for a connection restart (e.g., a restart command issued by host device 402) because host device 402 has reached the retry limit.
[0054] If the retry limit has not been reached at box 610, host device 402 retryes the command at box 606. However, if the retry limit has been reached at box 610, the connection between data storage device 412 and host device 402 is restarted. In some examples, host device 402 may determine to restart data storage device 412. When the connection is restarted, controller 414 may be temporarily unable to access the HMB. Therefore, data stored in the HMB (such as...) Figure 1A Any FTL tables and other information in the HMB 140 may be inaccessible until the connection is re-established.
[0055] Figure 6B To illustrate, according to certain embodiments, a data storage device (such as...) Figure 4 The flowchart of method 625 for handling HMB loss in data storage device 412) is shown. Method 625 can be performed by... Figure 4The controller 414 is implemented. Therefore, for illustrative purposes, various aspects of the storage system 400 may be referenced in the description herein.
[0056] At box 626, controller 414 determines that an HMB 140 loss has occurred. For example, an HMB 140 loss could be... Figure 6A At box 612, a restart or any other applicable HMB 140 connection loss, such as a connection reset or noise in the connection channel, occurs. At box 628, controller 414 marks all commands in command database 422 that have not been successfully executed or do not have a successful completion indicator with an error status (e.g., an error indicator). At box 628, controller 414 also disables command retrieval from host device 402 when it determines that the connection to HMB 140 has been lost. At box 630, the last copy of the FTL table (i.e., the translation table) is loaded from NVM 438. It is contemplated that the last copy of the FTL table loaded from NVM 438 may not be the same as the FTL table stored in HMB 140.
[0057] At box 632, controller 414 recreates the latest FTL table using the loaded FTL table and commands from command database 422. One or more updates to the generated FTL table may be stored in NVM 438 and transferred to HMB 140 when the HMB 140 connection is restored. At box 634, command fetching is re-enabled, allowing one or more commands to be fetched or re-fetched from host device 402. Host device 402 can retry failed commands (e.g., commands marked with an error status) by having controller 414 fetch failed commands from host device 402 in order to successfully complete the failed commands.
[0058] Figure 6C To illustrate, according to certain embodiments, a data storage device (such as...) Figure 4 The flowchart illustrates a method 650 for power-on self-test boot processing of a data storage device 412. Method 650 can be performed by... Figure 4 The controller 414 is implemented. Therefore, for illustrative purposes, various aspects of the storage system 400 may be referenced in the description herein.
[0059] At box 652, a connection to HMB 140 is initiated. At box 654, the FTL table is copied from NVM 438 to HMB 140. The copy may include copying the entire FTL table from NVM 438 to HMB 140 or only copying the updated portion of the FTL table from NVM 438 to HMB 140. For example, the updated portion may be the difference between the FTL table located in NVM 438 and the FTL table located in HMB 140. Furthermore, during operation of data storage device 412, updates to the FTL table may be stored in the history buffer of local SRAM of data storage device 412 or any other suitable buffer such as DRAM.
[0060] For example, at box 656, an FTL table update is generated when controller 414 executes a queuing command or a fetch command. At box 658, the FTL table update (i.e., the difference between HMB 140 and NVM 438) is stored in SRAM or any other suitable buffer as well as in HMB 140. In some examples, the buffer may be DRAM when data storage device 412 includes DRAM. Since accessing HMB 140 is generally faster than accessing NVM 438, the FTL update is stored in both SRAM and HMB 140. Therefore, HMB 140 may have an updated version of the FTL table compared to NVM 438.
[0061] At box 660, controller 414 determines whether NVM 438 needs to be updated to match the FTL table stored in NVM 438 with the FTL table stored in HMB 140. For example, controller 414 may determine that NVM 438 needs to be updated for reasons such as: Forced Cell Access (FUA) command, history buffer filling, periodic updates due to transaction volume or time elapsed, NVM 438 being idle due to a lack of commands to execute, or history buffer clearing. If NVM 438 is not required to be updated at box 660, method 650 returns to box 656. However, if NVM 438 is required to be updated at box 660, controller 414 updates the FTL table in NVM 438 at box 662 to match the FTL table stored in HMB 140. In one example, the update may copy the update portion from the FTL table stored in HMB 140 or SRAM to the FTL table in NVM 438. In another example, the differences between the FTL table of HMB 140 and the FTL table of NVM 438 can be determined, and the FTL table of NVM 438 can be updated based on the determined differences.
[0062] Recovery from HMB loss can be performed without causing host device timeout by executing commands with an error status so that the host device can retry the command.
[0063] In one embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: determine if a connection to the host memory buffer (HMB) of the host device has been lost; load the latest copy of the Flash Translation Layer (FTL) table from the memory device; generate one or more updates to the latest copy of the FTL table; and re-enable command fetching.
[0064] The controller is further configured to disable command acquisition when it is determined that the connection to the HMB of the host device has been lost. Re-enabling acquisition involves acquiring one or more commands from the host device. The memory device is a non-volatile memory device. The controller is configured to store the FTL table in both the HMB and the memory device. One or more updates generated are stored in the memory device. The controller is configured to update the FTL table stored in the HMB with the one or more updates generated in the memory device when the connection to the HMB is restored. The controller is further configured to mark one or more commands in the command database with an error status during determination. The error status suggests that the host device retry sending the marked one or more commands to the controller to be executed. The controller is further configured to execute the marked one or more commands after re-enabling and receiving the marked one or more commands from the host device.
[0065] In another embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: determine that the connection between the controller and the host memory buffer (HMB) of the host device has been restored; copy a flash translation layer (FTL) table from the memory device to the HMB, wherein the copying occurs after the connection between the controller and the HMB has been restored; and execute one or more commands stored in a command database.
[0066] The one or more commands include commands marked with one or more tags. The one or more marked commands include commands marked with an error status due to HMB loss. The controller is further configured to update the FTL table stored in the HMB using the executed one or more commands. The controller is further configured to determine that the FTL table stored in the memory device is different from the FTL table stored in the HMB. The controller is further configured to update the FTL table stored in the memory device using the FTL table stored in the HMB when it is determined that the FTL table stored in the memory device is different from the FTL table stored in the HMB. The controller is further configured to determine that the FTL table stored in the HMB is different from the FTL table stored in the memory device. Copying includes updating the FTL table stored in the HMB using the changes to the FTL table stored in the memory device when it is determined that the FTL table stored in the HMB is different from the FTL table stored in the memory device.
[0067] In another embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The data storage device does not have DRAM. The controller is configured to: initially receive a command from a host device; send an error indication with a retry suggestion to the host device for the command; receive the command again from the host device; and execute the command. The controller is further configured to load a flash translation layer (FTL) table from the memory device between sending the error indication and executing the command.
[0068] The controller is further configured to determine that the connection to the host memory buffer (HMB) has been lost. The controller is further configured to receive an indication of a restart operation from the host device due to the retry limit being reached. The controller is further configured to receive a restart command from the host device due to the indication of a restart operation.
[0069] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.
Claims
1. A data storage device, the data storage device comprising: Memory devices; and A controller coupled to the memory device, wherein the data storage device has no DRAM, and wherein the controller is configured to: A connection to the host memory buffer (HMB) of a host device is determined to be lost, wherein the connection between the host device and the data storage device is restarted in response to the retry limit of a command being reached, wherein retrying the command includes retransmitting the command from the host device to the data storage device in response to a retry suggestion sent by the controller to the host device; Load the latest copy of the flash translation layer table, i.e., the FTL table, from the memory device; One or more updates to generate the latest copy of the FTL table; as well as Re-enable command retrieval.
2. The data storage device of claim 1, wherein the controller is further configured to disable the command acquisition when it is determined that the connection with the HMB of the host device is lost.
3. The data storage device of claim 1, wherein re-enabling the acquisition includes acquiring one or more commands from the host device.
4. The data storage device according to claim 1, wherein the memory device is a non-volatile memory device.
5. The data storage device of claim 1, wherein the controller is configured to store the FTL table in both the HMB and the memory device.
6. The data storage device of claim 1, wherein one or more updates generated are stored in the memory device.
7. The data storage device of claim 6, wherein the controller is configured to update the FTL table stored in the HMB with one or more updates generated and stored in the memory device when re-establishing connection with the HMB.
8. The data storage device of claim 1, wherein the controller is further configured to mark one or more commands in the command database with an error status when making the determination.
9. The data storage device of claim 8, wherein the error state suggests that the host device retry sending the marked one or more commands to the controller to be executed, and wherein the controller is further configured to execute the marked one or more commands after the reactivation and receipt of the marked one or more commands from the host device.
10. A data storage device, the data storage device comprising: Memory devices; and A controller coupled to the memory device, wherein the data storage device has no DRAM, and wherein the controller is configured to: It is determined that the connection between the controller and the host memory buffer (HMB) of the host device has been restored, wherein the connection between the host device and the data storage device is restarted in response to the retry limit of the command being reached, wherein retrying the command includes retransmitting the command from the host device to the data storage device in response to a retry suggestion sent by the controller to the host device; The flash translation layer table (FTL table) is copied from the memory device to the HMB, wherein the copying occurs after the connection between the controller and the HMB has been restored; and Execute one or more commands stored in the command database.
11. The data storage device of claim 10, wherein the one or more commands include one or more marked commands, and wherein the one or more marked commands include commands marked with an error status due to HMB loss.
12. The data storage device of claim 11, wherein the controller is further configured to update the FTL table stored in the HMB using one or more commands executed.
13. The data storage device of claim 12, wherein the controller is further configured to determine that the FTL table stored in the memory device is different from the FTL table stored in the HMB.
14. The data storage device of claim 13, wherein the controller is further configured to update the FTL table stored in the memory device using the FTL table stored in the HMB when it is determined that the FTL table stored in the memory device is different from the FTL table stored in the HMB.
15. The data storage device of claim 10, wherein the controller is further configured to determine that the FTL table stored in the HMB is different from the FTL table stored in the memory device.
16. The data storage device of claim 15, wherein the replication includes updating the FTL table stored in the HMB with the change in the FTL table stored in the memory device when it is determined that the FTL table stored in the HMB is different from the FTL table stored in the memory device.
17. A data storage device, the data storage device comprising: Memory devices; and A controller coupled to the memory device, wherein the data storage device has no DRAM, and wherein the controller is configured to: Receive commands from the host device for the first time; Send an error indication with a retry suggestion for the command to the host device, wherein the connection between the host device and the data storage device is restarted in response to the retry limit of the command being reached; After the connection is restarted, in response to sending the retry suggestion, the command is received again from the host device; as well as The controller is configured to load a flash translation layer table (FTL) from the memory device between sending the error indication and executing the command.
18. The data storage device of claim 17, wherein the controller is further configured to determine that the connection to the host memory buffer, i.e., the HMB, has been lost.
19. The data storage device of claim 17, wherein the controller is further configured to receive an instruction for a restart operation from the host device due to the retry limit being reached.
20. The data storage device of claim 19, wherein the controller is further configured to receive a restart command from the host device in response to the instruction of the restart operation.