Semiconductor memory device

Abstract

The present embodiment provides a semiconductor storage device capable of shortening the time tPROG required for writing. The semiconductor storage device of the embodiment receives a write instruction and an address, performs data writing, and includes: a plurality of memory strings each including a plurality of memory cell transistors connected in series and connected in parallel to each other; a plurality of word lines connected to gates of the plurality of memory cell transistors, respectively; a block including the plurality of memory strings to which the plurality of word lines are commonly connected; and a control circuit that controls a write operation on at least a part of the plurality of memory cell transistors, and the write operation is performed in accordance with the reception of the write instruction and the address, and the control circuit determines whether or not to perform a first voltage application operation before the write operation ends, the first voltage application operation applying a specific voltage to the plurality of word lines, based on the address.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-153545 (filed on September 21, 2021) and Japanese Patent Application No. 2022-16615 (filed on February 4, 2022). This application incorporates the entire contents of the aforementioned basic applications by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] NAND (Not And) type memory is known as a type of semiconductor memory device. In this type of semiconductor memory device, it is required to reduce the time required for data writing (tPROG). Summary of the Invention

[0005] This embodiment provides a semiconductor memory device that can shorten the write time tPROG.

[0006] The semiconductor memory device of the embodiment receives a write instruction and an address to write data, and includes: a plurality of memory strings, each containing a plurality of memory cell transistors connected in series and connected in parallel; a plurality of word lines connected to the gates of the plurality of memory cell transistors; a block containing the plurality of memory strings that are commonly connected to the plurality of word lines; and a control circuit that controls a write operation for at least a portion of the plurality of memory cell transistors; wherein the write operation is executed according to the receipt of the write instruction and the address, and the control circuit determines, based on the address, whether to perform a first voltage application operation before the end of the write operation, the first voltage application operation applying a specific voltage to the plurality of word lines. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system.

[0008] Figure 2 It means Figure 1 A block diagram of an example of non-volatile memory 2 in the diagram.

[0009] Figure 3 This is a diagram illustrating a block configuration example of a 3D constructed memory cell array 20.

[0010] Figure 4 This is a cross-sectional view of a portion of the BLK block.

[0011] Figure 5This is an illustrative diagram representing an example of the threshold distribution and encoding of a memory cell array.

[0012] Figure 6 It means Figure 2 A block diagram of an example of the sensing amplifier unit group 28 and data register 29.

[0013] Figure 7 It means Figure 6 The circuit diagram shows an example of the specific configuration of the sensing amplifier unit SAU in the circuit.

[0014] Figure 8A It means Figure 3 A block diagram of an example of the line decoder 26 in the diagram.

[0015] Figure 8B This is a diagram illustrating the junction leakage characteristics of the switches that constitute the line decoder 26.

[0016] Figure 9 It is a waveform diagram showing the write operation, with time taken in the horizontal direction and voltage taken in the vertical direction.

[0017] Figure 10 This is an explanation Figure 9 The waveform diagram of the creeping of the word line WL after the action.

[0018] Figure 11 The waveform diagrams represent other examples of write operations, with time taken in the horizontal direction and voltage taken in the vertical direction.

[0019] Figure 12 This is an explanation Figure 11 The waveform diagram of the creeping of the word line WL after the action.

[0020] Figure 13 The waveform diagrams represent other examples of write operations, with time taken in the horizontal direction and voltage taken in the vertical direction.

[0021] Figure 14 It is a waveform diagram that takes time in the horizontal direction and voltage in the vertical direction to illustrate the method of determining the object word line WL or non-object word line WL for all string reading actions.

[0022] Figure 15 It is a waveform diagram that takes time in the horizontal direction and voltage in the vertical direction to illustrate the method of determining the object word line WL or non-object word line WL for all string reading actions.

[0023] Figure 16 This is an explanatory diagram used to illustrate the operation of the first embodiment.

[0024] Figure 17 It is a waveform diagram representing the waveforms of each part of the refresh and read operation.

[0025] Figure 18 It is a waveform diagram representing the waveforms of each part of the refresh and read operation.

[0026] Figure 19 This is a flowchart illustrating an example of the specific actions of the string reading control circuit.

[0027] Figure 20 It is used to explain Figure 19 A diagram of the address received in S2.

[0028] Figure 21 It is a sequence diagram of the basic programming actions performed on a per-page basis.

[0029] Figure 22 It is a sequence diagram of cache programming operations.

[0030] Figure 23 This is an illustrative diagram representing an example of a write operation in cache programming.

[0031] Figure 24 This is an illustrative diagram illustrating a write example of a cache programming action.

[0032] Figure 25 This is an illustrative diagram illustrating a write example of a cache programming action.

[0033] Figure 26 This is an illustrative diagram illustrating a write example of a cache programming action.

[0034] Figure 27 This is an illustrative diagram illustrating a write example of a cache programming action.

[0035] Figure 28 This is a flowchart used to illustrate the second embodiment.

[0036] Figure 29 This is an explanatory diagram used to illustrate the second embodiment.

[0037] Figure 30 This is an explanatory diagram used to illustrate the second embodiment.

[0038] Figure 31 This is a flowchart used to illustrate the second embodiment.

[0039] Figure 32 This is a flowchart used to illustrate the third embodiment.

[0040] Figure 33 This is a flowchart used to illustrate the third embodiment. Detailed Implementation

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] (First Embodiment)

[0043] In this embodiment, when writing is performed by applying programming voltage to a portion of the word lines WL that are sequentially programmed during writing, the read voltage application operation of the All String Read Pulse (hereinafter referred to as the All String Read operation) is omitted, thereby shortening the write time tPROG.

[0044] (The structure of a memory system)

[0045] Figure 1 This is a block diagram illustrating an example configuration of a memory system. The memory system 1 of this embodiment includes a memory controller 3 and a non-volatile memory 2. Alternatively, the non-volatile memory 2 may contain multiple memory chips. The memory system 1 can be connected to a host device 4. The host device 4 is, for example, an electronic device such as a personal computer or a portable terminal.

[0046] The memory system 1 can be constructed by mounting multiple chips constituting the memory system 1 on a motherboard equipped with the host device 4, or it can be constructed as a system LSI (Large-Scale Integrated Circuit) or SoC (System-on-a-Chip) that implements the memory system 1 as a single module. Examples of memory systems 1 include memory cards such as SD cards (Secure digital cards), SSDs (Solid-State Drives), and eMMCs (embedded Multi-Media Cards).

[0047] Non-volatile memory 2 is a NAND-type memory with multiple memory cells that stores data non-volatilely. The specific structure of non-volatile memory 2 is described below.

[0048] The memory controller 3, for example, responds to commands from the host device 4 to write (also known as program), read, and erase commands on the non-volatile memory 2. Furthermore, the memory controller 3 manages the memory space of the non-volatile memory 2. The memory controller 3 includes a host interface (host I / F) circuit 10, a processor 11, RAM (Random Access Memory) 12, a buffer memory 13, a memory interface circuit (memory I / F) circuit 14, and an ECC (Error Checking and Correcting) circuit 15, etc.

[0049] The host I / F circuit 10 is connected to the host device 4 via the host bus and performs interface processing with the host device 4. In addition, the host I / F circuit 10 and the host device 4 exchange commands, addresses and data.

[0050] The processor 11 is, for example, a CPU (Central Processing Unit). The processor 11 controls the overall operation of the memory controller 3. For example, when the processor 11 receives a write command from the host device 4, it issues the write command corresponding to the write command from the host device 4 to the non-volatile memory 2 via the memory I / F circuit 14. The same applies to read and erase operations. Furthermore, the processor 11 performs various processes, such as wear leveling, to manage the non-volatile memory 2.

[0051] RAM 12 is used as the working area of ​​processor 11, storing firmware data loaded from non-volatile memory 2, and various tables created by processor 11. RAM 12 is composed of, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0052] The buffer memory 13 temporarily stores data sent from the host device 4 and temporarily stores data sent from the non-volatile memory 2.

[0053] The memory I / F circuit 14 is connected to the non-volatile memory 2 via a bus and performs interface processing with the non-volatile memory 2. In addition, the memory I / F circuit 14 and the non-volatile memory 2 exchange commands, addresses, and data.

[0054] When writing data, the ECC circuit 15 generates an error correction code for the written data, appends the error correction code to the written data, and sends it to the memory I / F circuit 14. Furthermore, when reading data, the ECC circuit 15 uses the error correction code contained in the read data to perform error detection and / or error correction on the read data. Alternatively, the ECC circuit 15 may also be located within the memory I / F circuit 14.

[0055] (The structure of non-volatile memory)

[0056] Figure 2 It means Figure 1A block diagram of an example of non-volatile memory 2. Non-volatile memory 2 includes memory cell array 20, input / output circuit 21, logic control circuit 22, register 23, control circuit 24, voltage generation circuit 25, row decoder 26, column decoder 27, sense amplifier cell group 28, and data register (data cache) 29.

[0057] The memory cell array 20 includes j blocks BLK0~BLK(j-1) and a block BLKX. j is an integer greater than or equal to 1. Each block BLK has multiple memory cell transistors. The memory cell transistors constitute electrically rewritable memory cells. To control the voltage applied to the memory cell transistors, the memory cell array 20 is provided with multiple bit lines BL, multiple word lines WL, and source lines CELSRC, etc. The specific structure of the block BLK is described below.

[0058] The input / output circuit 21 and the logic control circuit 22 are connected to the memory controller 3 via a bus. The input / output circuit 21 and the memory controller 3 communicate via the bus to send and receive signals DQ (e.g., DQ0~DQ7).

[0059] The logic control circuit 22 receives external control signals (such as chip start signal CEn, instruction latch start signal CLE, address latch start signal ALE, write start signal WEn, read start signal REen, and write protect signal WPn) from the memory controller 3 via the bus. The 'n' in the signal name indicates active low. Furthermore, the logic control circuit 22 sends a ready / busy signal R / Bn to the memory controller 3 via the bus.

[0060] The signal CEn is used in systems using multiple non-volatile memories 2 to select and activate a specific non-volatile memory 2. The signal CLE latches the instruction sent as the DQ signal into register 23. The signal ALE latches the address sent as the DQ signal into register 23. The signal WEn enables writing. The signal REn enables reading. The signal WPn disables writing and erasing. The signal R / Bn indicates whether, when using basic operation instructions, the non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources).

[0061] Furthermore, when using the cache programming instruction (15h) described later (and the cache read instruction unrelated to this invention), the system first returns to the ready state at the moment the data latch circuit XDL is released. Hereinafter, unless otherwise specified, the cache programming operation will be described based on the basic operation of R / Bn. The memory controller 3 can determine the state of the non-volatile memory 2 by receiving the signal R / Bn.

[0062] Register 23 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of non-volatile memory 2. Register 23 may be constructed from SRAM, for example.

[0063] The control circuit 24 receives instructions from the register 23 and, in order based on the instructions, comprehensively controls the non-volatile memory 2.

[0064] The voltage generation circuit 25 receives a power supply voltage from an external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 25 supplies the generated multiple voltages to the memory cell array 20, the line decoder 26, and the sense amplifier unit group 28, etc. For example, the voltage generation circuit 25 supplies various voltages to the line decoder 26 via wiring group 25A.

[0065] The row decoder 26 receives the row address from register 23 and decodes it. Based on the decoded row address, the row decoder 26 performs word line selection. Furthermore, the word line connected to the memory cell transistor MT that will be written to and read from is called the select word line. The row decoder 26 also transmits multiple voltages required for write, read, and erase operations to the selected block BLK.

[0066] Column decoder 27 receives the column address from register 23 and decodes the column address. Based on the decoded column address, column decoder 27 supplies a specific voltage to each bit line BL.

[0067] During data readout, the sensing amplifier unit group 28 detects and amplifies the data read from the memory cell transistor to the bit line. Furthermore, during data writeout, the sensing amplifier unit group 28 supplies the write data to the bit line BL.

[0068] When data is read out, data register 29 temporarily stores the data transmitted from the sense amplifier unit group 28 and serially transmits it to the input / output circuit 21. Furthermore, when data is written, data register 29 temporarily stores the data serially transmitted from the input / output circuit 21 and transmits it to the sense amplifier unit group 28. Data register 29 is constructed using SRAM or the like.

[0069] (Block structure of a memory cell array)

[0070] Figure 3 This is a diagram illustrating an example of the structure of a block of a 3D memory cell array 20. Figure 3 The diagram shows one of the blocks BLK that constitute the memory cell array 20. The other blocks of the memory cell array also have the same characteristics. Figure 3 Same composition.

[0071] As shown in the figure, block BLK, for example, contains four string cells SU0 to SU3 (hereinafter referred to as string cells SU). Furthermore, each string cell SU has a NAND string NS containing multiple memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. Additionally, the number of memory cell transistors MT contained in the NAND string NS is... Figure 3 The number of gate selectors is set to eight, but more can be used. The select gate transistors ST1 and ST2 are represented as a single transistor in the circuit, but their construction can be the same as that of the memory cell transistors. Furthermore, multiple select gate transistors can be used as both ST1 and ST2. Additionally, a dummy cell transistor can be placed between the memory cell transistor MT and the select gate transistors ST1 and ST2.

[0072] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end (bit line side) is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end (source line side) is connected to the select gate transistor ST2.

[0073] The gates of the select gate transistors ST1 of each of the series units SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3 (hereinafter, these are referred to as select gate lines SGD). Furthermore, the gates of the select gate transistors ST2 of each of the series units SU0 to SU3 are respectively connected to select gate lines SGS0 to SGS3 (hereinafter, these are referred to as select gate lines SGS). Additionally, the gates of the multiple select gate transistors 2 located within each BLK block can also be connected to a common select gate line SGS.

[0074] The gates of memory cell transistors MT0 to MT7 located within the same block BLK are all connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 are shared among multiple string cells SU0 to SU3 within the same block BLK. Correspondingly, the select gate line SGD is independent for each string cell SU0 to SU3 within the same block BLK. Within the block BLK, the gates of memory cell transistors MTi located in the same row are connected to the same word line WLi.

[0075] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistors ST1, ST2, or other memory cell transistors MT contained in the NAND string NS. Generally, the data on the memory cell transistors MT located within the same block BLK is erased uniformly. On the other hand, typically, multiple memory cell transistors MT that are commonly connected to a single word line WL disposed in one string cell SU are read and written uniformly. This group of memory cell transistors MTs that share a word line WL within one string cell SU is called a cell group CU.

[0076] Write operations to a unit group (CU) are performed on a page-by-page basis. For example, if each unit is a Triple Level Cell (TLC) capable of storing 3 bits (8 values) of data, one CU can store 3 pages of data. The 3 bits that each memory cell transistor (MT) can store correspond to the 3 pages.

[0077] (Layered structure of block BLK)

[0078] Figure 4 This is a cross-sectional view of a portion of a block BLK. The X direction is the direction in which the gate select line (SGD) extends, the Y direction which intersects the X direction in the horizontal plane is the direction in which the bit line extends, and the Z direction is the stacking direction.

[0079] Multiple NAND strings NS are disposed on the p-well region 30. That is, on the well region 30, a wiring layer 31 that functions as the select gate line SGS, an 8-layer wiring layer 32 that functions as word lines WL0~WL7, and a wiring layer 33 that functions as the select gate line SGD are sequentially stacked. An insulating layer (not shown) is disposed between the stacked wiring layers.

[0080] Memory via 34 penetrates wiring layers 31, 32, and 33 to reach well region 30. A columnar semiconductor layer (semiconductor pillar) 35 is disposed within memory via 34. Alternatively, semiconductor layer 35 may be cylindrical, arranged to surround an insulator (not shown). On the side of semiconductor layer 35, a gate insulating film 36, a charge storage layer (insulating film) 37, and a barrier insulating film 38 are sequentially disposed. This forms the memory cell transistor MT and select gate transistors ST1 and ST2. Semiconductor layer 35 functions as the current path for the NAND string NS, becoming the region through which each transistor is formed. The upper end of semiconductor layer 35 is connected to metal wiring layer 40, which functions as bit line BL, via contact plug 39.

[0081] Thus, between the select gate transistors ST1 and ST2 of each NAND string NS, a channel region is formed, consisting of multiple memory cell transistors MT contained in each NAND string NS, which functions as the current path for each NAND string NS. Each channel region is connected to one of the multiple bit lines BL via the select gate transistor ST1, and to the well region 30, which serves as the substrate, via the select gate transistor ST2. Each channel region is disposed above the substrate and has a pillar shape.

[0082] Within the surface region of the well region 30, an n+ type diffusion layer 41 with a high concentration of n-type impurities is formed. A contact plug 42 is formed on the diffusion layer 41 and connected to a metal wiring layer 43 that functions as a source line. Furthermore, within the surface region of the well region 30, a p+ type diffusion layer 44 with a high concentration of p-type impurities is formed. A contact plug 45 is formed on the diffusion layer 44 and connected to a metal wiring layer 46 that functions as a well wiring CPWELL. The well wiring CPWELL is a wiring used to apply voltage to the semiconductor layer 35 via the well region 30.

[0083] The above constitutes Figure 4 Multiple NAND strings NS are arranged along the depth direction (X direction) of the paper, forming a string unit SU.

[0084] (Threshold Distribution and Coding)

[0085] Figure 5 This is an illustrative diagram representing an example of the threshold distribution and encoding of a memory cell array. Figure 5 The diagram illustrates an example of the threshold distribution for a 3-bit / cell non-volatile memory 2. In the non-volatile memory 2, the threshold voltage of the memory cell transistor MT is set based on the data values ​​of the multi-valued data stored in the memory cell transistor MT. Since the amount of charge injected into the charge storage layer 37 (charge storage region) is random, as shown... Figure 5 As shown, the threshold voltages of the transistors MT in each memory cell also exhibit a statistical distribution.

[0086] Figure 5 The lower layer takes the threshold voltage in the horizontal direction and the number of memory cells in the vertical direction. The distribution of the threshold voltage (threshold distribution) is represented by eight mountain-shaped regions: Er, A, B, C, D, E, F, and G. Each region is called the Er level, A level, B level, C level, D level, E level, F level, and G level. Figure 5 In the example, by setting the threshold voltage of the memory cell transistor MT to any one of the eight levels, the memory cell transistor MT can store 8 values ​​of data (3 bits of data).

[0087] Voltages VA, VB, VC, VD, VE, VF, and VG are reference voltages that serve as the boundaries of each level. During the read operation, these voltages VA~VG are applied to the word line WL as the read voltage for reading, and the transistor MT of the target memory cell is determined to be on or off, thereby allowing data to be read.

[0088] Various methods can be employed to correspond data values ​​to different voltage levels (i.e., threshold distributions) of the memory cell transistor MT. As an example of encoding, Figure 5 The upper layer shows 2-3-2 encoding.

[0089] Figure 5 In the example, the following cases are shown: Er level memory cell transistors store data (1, 1, 1), A level memory cell transistors store data (0, 1, 1), B level memory cell transistors store data (0, 0, 1), C level memory cell transistors store data (0, 0, 0), D level memory cell transistors store data (0, 1, 0), E level memory cell transistors store data (1, 1, 0), F level memory cell transistors store data (1, 0, 0), and G level memory cell transistors store data (1, 0, 1).

[0090] The upper, middle, and lower data groups of each memory cell transistor are referred to as the Upper page, Middle page, or Lower page, respectively. Generally, reads are performed in units of these pages.

[0091] Assuming that the read operation involves determining which of the three bits of data stored in each memory cell transistor is being read, rather than a page-level read, the read voltage applied to the select word line WL needs to be varied seven times from voltage VA to voltage VG. In contrast, a page-level read can be performed by varying the voltage only two or three times. Furthermore, Figure 5 AR, BR, CR, DR, ER, FR, and GR represent the readouts when the readout voltages VA, VB, VC, VD, VE, VF, and VG are applied, respectively.

[0092] For example, when reading the Lower page value of each memory cell transistor, it is sufficient to change the read voltage from voltage VA to voltage VE twice. For example, the read voltage VA is applied to the read (select word line WL)... Figure 5 When the AR is detected, if the memory cell transistor of the read-out object is determined to be in the on state by the sensing amplifier unit group 28, the Lower page of the memory cell transistor of the read-out object can be determined to be "1".

[0093] Furthermore, for example, when the readout voltage VA is applied to the readout (AR) of the select word line WL, if the sense amplifier unit group 28 determines that the memory cell transistor to be read is in a non-conducting state, the lower page of the memory cell transistor to be read may be "0" or "1". Therefore, readout (ER) is then performed with the readout voltage VE. As a result, if the sense amplifier unit group 28 determines that the memory cell transistor to be read is in a conducting state, the lower page of the memory cell transistor to be read can be determined to be "0", and if it is determined to be in a non-conducting state, the lower page of the memory cell transistor to be read can be determined to be "1".

[0094] in this way, Figure 5 In the 2-3-2 encoding, the read voltage can be determined by ensuring it changes a maximum of 2 times in the Upper page, 3 times in the Middle page, and 2 times in the Lower page. Additionally, Figure 5 The encoding shown is a Gray code where the data changes by only one bit between any two adjacent regions.

[0095] (Composition of the sensing amplifier unit and data register)

[0096] Figure 6 It means Figure 2 A block diagram of an example of the sensing amplifier unit group 28 and data register 29.

[0097] The sense amplifier unit group 28 includes sense amplifier units SAU0 to SAU(m-1) corresponding to bit lines BL0 to BL(m-1) (hereinafter, these are referred to as sense amplifier units SAU). Each sense amplifier unit SAU includes a sense amplifier SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier SA and the data latch circuits SDL, ADL, BDL, and CDL are connected in a manner that allows data to be transmitted between them.

[0098] The data latch circuits SDL, ADL, BDL, and CDL temporarily store data. During a write operation, the sense amplifier SA controls the voltage of the bit line BL based on the data stored in the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations where the memory cell transistor MT stores more than two bits of data. That is, the data latch circuit ADL is used to store the write data for the Lower page. The data latch circuit BDL is used to store the write data for the Mid-Del page. The data latch circuit CDL is used to store the write data for the Upper page. The number of data latch circuits in the sense amplifier unit SAU is determined by the number of bits stored by one memory cell transistor MT.

[0099] During a read operation, the sense amplifier SA detects the data read onto the corresponding bit line BL and determines whether the data is 0 or 1. Furthermore, during a write operation, the sense amplifier SA applies a voltage to the bit line BL based on the data being written.

[0100] Data register 29 has a number of data latch circuits XDL corresponding to the number of sense amplifier units SAU0 to SAU(m-1). The data latch circuits XDL are connected to input / output circuit 21. The data latch circuits XDL temporarily store write data sent from input / output circuit 21, and also temporarily store read data sent from sense amplifier units SAU. More specifically, data transmission between input / output circuit 21 and sense amplifier unit group 28 is performed via a one-page data latch circuit XDL. Write data received by input / output circuit 21 is transmitted via the data latch circuit XDL to any one of data latch circuits ADL, BDL, and CDL. Read data read from sense amplifier SA is transmitted to input / output circuit 21 via the data latch circuit XDL.

[0101] (Sensing amplifier circuit)

[0102] Figure 7 It means Figure 6 A circuit diagram illustrating an example of the specific configuration of the sensing amplifier unit SAU.

[0103] Sensing amplifier unit SAU, such as Figure 7 As shown, it includes a sense amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier section SA and the data latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS in a manner that allows them to receive data from each other.

[0104] The data latch circuit SDL includes, for example, inverters 60 and 61, and n-channel MOS (Metal Oxide Semiconductor) transistors 62 and 63. The input node of inverter 60 and the output node of inverter 61 are connected to node LAT. The input node of inverter 61 and the output node of inverter 60 are connected to node / LAT. Inverters 60 and 61 store data in nodes / LAT and LAT. Write data is supplied to node LAT. The data stored in node / LAT is the inverted version of the data stored in node LAT.

[0105] One end of the drain / source path of transistor 62 is connected to node LAT, and the other end is connected to the bus LBUS. Similarly, one end of the drain / source path of transistor 63 is connected to node LAT, and the other end is connected to the bus LBUS. A control signal STL is input to the gate of transistor 63, and a control signal STI is input to the gate of transistor 62.

[0106] Furthermore, since the circuit configurations of data latch circuits ADL, BDL, CDL, and XDL are the same as those of data latch circuit SDL, their descriptions are omitted. Additionally, the various control signals supplied to the sense amplifier unit SAU are provided by control circuit 24.

[0107] The sensing amplifier section SA includes, for example, a p-channel MOS transistor 50, n-channel MOS transistors 51-58, and a capacitor 59.

[0108] During the readout operation, the sensing amplifier section SA senses the data read from the corresponding bit line BL and determines whether the read data is "0" or "1". Furthermore, during the programming operation, the sensing amplifier section SA sets the corresponding bit line BL to the voltage value corresponding to the written data "0" or "1".

[0109] In the sensing amplifier section SA, transistors 50-54 participate in the programming operation. Between the power line supplying the internal power supply voltage (VDD) and node COM, the source / drain paths of transistor 50 (the second transistor) and transistor 51 (the drain / drain path) are connected in series. Furthermore, between node COM and node CELSRC (the ground voltage (VSS)), the drain / drain path of transistor 54 (the third transistor) is connected. Additionally, between node COM and bit line BL, the drain / drain paths of transistor 52 and transistor 53 (the first transistor) are connected in series.

[0110] The gates of transistors 50 and 54 are connected to node / LAT. Therefore, when node LAT is low (hereinafter referred to as L level) corresponding to data "0", node / LAT remains high (hereinafter referred to as H level), transistor 50 is off, and transistor 54 is on. Conversely, when node LAT is high (H level) corresponding to data "1", node / LAT remains low, transistor 50 is on, and transistor 54 is off.

[0111] During programming, the control signals HLL and XXL supplied to the gates of transistors 55 and 56 are at the low level, respectively, and transistors 55 and 56 are turned off. The control signal BLX supplied to transistor 51 is at the high level, and transistor 51 is turned on. In addition, during normal programming, transistors 52 and 53 are turned on by the control signals BLC and BLS.

[0112] Therefore, when a "0" data is stored at node LAT, transistor 50 is turned off and transistor 54 is turned on, supplying the bit line voltage VSS (e.g., 0 V) ​​from node CELSRC to bit line BL. Furthermore, when a "1" data is stored at node LAT, transistor 50 is turned on and transistor 54 is turned off, and according to the control signals BLC and BLS given to transistors 52 and 53, for example, a bit line voltage of 2.5 V is supplied to bit line BL.

[0113] (Verification action)

[0114] The verification operation, performed after the programming operation, involves reading the data from the memory cell transistor MT and determining whether the threshold voltage of the memory cell transistor MT has reached the desired level. During this verification operation, all transistors 50-58 of the sensing amplifier section SA and capacitor 59 are involved. The drain / source paths of transistors 55 and 56 are connected in series between the drain of transistor 50 and node COM. Furthermore, the drain / source paths of transistors 58 and 57 are connected in series between the bus LBUS and the reference potential point. The source of transistor 55 and the drain of transistor 56 are connected to the sensing node SEN, which is connected to the gate of transistor 57. Control signals HLL, XXL, the voltage of the sensing node SEN, or the control signal STB are applied to the gates of transistors 55-58, respectively. The sensing node SEN is clocked with CLK via capacitor 59.

[0115] During the verification action, firstly, the line decoder 26 applies Vvfy (e.g., to the selection word line) corresponding to the target state. Figure 5 A nonselect read voltage VREAD (e.g., 5-7 V) higher than the voltages VA-VG is applied to the nonselect word line as a verification voltage (any one of the voltages VA-VG, or a voltage near these voltages).

[0116] During the verification operation, control circuit 24 first sets node / LAT to level L, turning on transistor 50. Furthermore, transistor 51 is turned on via control signal BLX, and control signals BLC and BLS are set to specific voltages, thereby fixing bit line BL to a fixed voltage (e.g., 0.5 V). Additionally, by setting control signal HLL to a specific voltage, sensing node SEN is charged to a specific pre-charge voltage Vpre higher than the voltage of bit line BL. In this state, if control signal XXL is set to level H, current flows from sensing node SEN through transistors 56, 52, and 53 to bit line BL, and the voltage of sensing node SEN gradually decreases.

[0117] The voltage of the sensing node SEN varies depending on the threshold voltage of the memory cell being verified (the selected memory cell). Specifically, when the threshold voltage of the selected memory cell is lower than the verification voltage Vvfy, the selected memory cell is in the ON state, a larger cell current flows to it, and the voltage of the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage of the selected memory cell is higher than the verification voltage Vvfy, the selected memory cell is in the OFF state, a smaller cell current flows to it, or no cell current flows to it at all, and the voltage of the sensing node SEN decreases more slowly.

[0118] Therefore, if the discharge of the charge of the sensing node SEN begins, and the first point of the first period has elapsed since the discharge begins, that is, after the control signal XXL is set to H level, the control signal XXL is set to L level, and the control signal STB is set to H level, and the transistor 58 is turned on, then the transistor 57 will turn on or off depending on whether the voltage of the sensing node SEN is L level or H level.

[0119] For example, when the selected memory cell is an insufficiently written cell, its threshold voltage is lower than the verification voltage Vvfy, and the difference between the two is large. Therefore, the selected memory cell is in a fully on state, and a large cell current flows to the selected memory cell. As a result, the voltage of the sensing node SEN drops rapidly, and the voltage drop reaches the judgment level before reaching the first time point. At the first time point, the sensing node SEN becomes low, transistor 57 is turned off, and current does not flow from the bus LBUS to the reference voltage point.

[0120] Furthermore, when the selected memory cell is a write-complete cell, its threshold voltage is higher than the verification voltage Vvfy, so the selected memory cell is in an off state, and the current flowing to the selected memory cell is very small, or no cell current flows to the selected memory cell. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop does not reach the judgment level before reaching point 1. At point 1, the sensing node SEN remains at level H. Therefore, transistor 57 is turned on, and current flows from the bus LBUS to the reference voltage point.

[0121] In this way, it is possible to distinguish between insufficiently written cells and fully written cells. Furthermore, the operation of the sensing amplifier unit SA is only one example. The control circuit 24 determines whether it is an insufficiently written cell or a fully written cell, and controls the sensing amplifier unit SAU based on the determination result, setting the bit line voltage.

[0122] (The structure of a line decoder)

[0123] Figure 8A It means Figure 2A block diagram of an example of line decoder 26 in the example. Figure 8A Only the circuitry for block BLK0 and block BLK1 in the output decoder 26 is shown; the other block circuits have the same circuitry configuration. Furthermore, Figure 8B This is a diagram illustrating the junction leakage characteristics of the switches that constitute the line decoder 26.

[0124] In the following description, the selection gate line SGD of the memory cell transistor MT used to select the block BLK to be written or read is called selSGD, and the selection gate line SGD of the memory cell transistor MT not used to select the block BLK is called uselSGD. Furthermore, the selection gate line SGS of the memory cell transistor MT used to select the BLK to be written or read is called selSGS, the selection gate line SGD used to deselect BLKs other than those to be written or read is called USGD, and the selection gate line SGS used to deselect BLKs other than those to be written or read is called USGS.

[0125] Wiring group 25A from voltage generation circuit 25 has signal lines SSGD / 1 / 2 / 3 for supplying voltages to selSGD and uselSGD, as described later. Figure 20 The serial cell address input provides a voltage to selSGD for any one of the inputs and a voltage to uselSGD for the remaining three. It also includes a signal line SSGS for supplying voltage to selSGD, a signal line USGD for supplying voltage to SGD of a BLK that is not the object of writing or reading, and a signal line USGS for supplying voltage to SGS of a BLK that is not the object of writing or reading. USGD and USGS are biased to VSS during write and read operations and during the ready period. Furthermore, wiring group 25A includes signal lines CG0, CG1, ... (hereinafter referred to as signal lines CG) for supplying voltage to each word line WL. Figure 8A An example is shown where wiring group 25A includes signal lines CG0 to CG63 corresponding to word lines WL0 to WL63.

[0126] The line decoder 26 has switches SW01~SW05 (hereinafter referred to as switches SW0) for block BLK0, and switches SW11~SW15, ... (hereinafter referred to as switches SW1) for block BLK1. Additionally, the representatives of switches SW0, SW1, ... are referred to as switches SW. Signal lines SSGD0 / 1 / 2 / 3 are connected to the select gate lines SGD0 / 1 / 2 / 3 of each block BLK via switches SWn1 (n is 0, 1, 2, ...). <0> SGD0 / 1 / 2 / 3 <1> ..., the signal line CG is connected to the word line WL0-63 of each BLK via switch SWn2 (n is 0, 1, 2, ...). <0> Word line WL0-63 <1> The signal line SSGS is connected to the select gate line SGS of each BLK block via switch SWn3 (n is 0, 1, 2, ...). <0> SGS <1> ... In addition, the signal line USGD is connected to the select gate lines SGD0 / 1 / 2 / 3 of each BLK block via switch SWn4 (n is 0, 1, 2, ...). <0> SGD0 / 1 / 2 / 3 <1> The signal line USGS is connected to the select gate line SGS of each BLK block via switch SWn5 (n is 0, 1, 2, ...). <0> SGS <1> ... In addition, SWn1 and SWn4 are connected in parallel to provide a series number of switches. For example, Figure 8A For convenience, a switch SW01 is shown, but in reality, it is connected to the four signal lines SSGD0 / 1 / 2 / 3 and the four select gate lines SGD0 / 1 / 2 / 3. <0> There are four switches SW01 connected to each other.

[0127] The line decoder 26 has an AND circuit AN0 for controlling block BLK0 of switch SW0, a high-voltage level phase shifter L0 and an inverter INV0, and an AND circuit AN1 for controlling block BLK1 of switch SW1, a high-voltage level phase shifter L1 and an inverter INV1. The AND circuits AN0, AN1, ... (hereinafter referred to as AND circuit AN) are given the line address from register 23. The outputs of the AND circuits AN0, AN1, ... are given to the high-voltage level phase shifters L0, L1, ... (hereinafter referred to as high-voltage level phase shifters L), and to the inverters INV0, INV1, ... (hereinafter referred to as inverters INV).

[0128] For example, the switch SW can be generated by Figure 8BThe NMOS transistor shown is constructed using a p-well structure. Specifically, the switch SW has a p-well 72 formed in a specific region of the P-type semiconductor substrate (Psub) 71. The P-type semiconductor substrate (Psub) 71 and the p-well 72 are biased to the VSS electrode via the P+ contact 73. Furthermore, a source region 74 and a drain region 75 are formed within the p-well 72. A gate electrode 76 containing conductive material is disposed on the semiconductor substrate between the source region 74 and the drain region 75, acting as a gate insulating film. The switch SW is formed by the source region 74, the drain region 75, and the gate region 76. A signal line CG is connected to the drain region 75, and a signal line WL is connected to the source region 74. Each transistor is electrically separated from the p+ contact 73 by a component separation region 77.

[0129] When the signal R / Bn is, for example, at a ready state of H level, the line decoder 26 is in a stopped state, and all word lines WL of all blocks become floating, sometimes having a fixed potential due to the influence of the previous action. Afterwards, WL eventually decreases due to the leakage of SWn2 over time. Figure 8B The arrow-like characteristic becomes the bias voltage VSS of the P-well 72 at the leakage end. When the signal R / Bn is, for example, at a busy state of L level, the line decoder 26 is in an active state, applying various bias voltages such as read voltage, programming voltage, and verification voltage to each word line WL of the selection block BLK.

[0130] In the AND circuit AN, the output of any one of the AND circuits becomes high (hereinafter referred to as H level), and the outputs of the other AND circuits become low (hereinafter referred to as L level), selecting one block BLK from BLK0, BLK1, ... When the output of the block BLK in the AND circuit AN is H level, the switch connected to the current path via the output of the high-voltage phase shifter L, and the switches in the switch SW with signal lines SSGD0 / 1 / 2 / 3, CG, and SSGS connected to the current path, are turned on. Conversely, when the output of the block BLK in the AND circuit AN becomes L level, the switch connected to the current path via the output of the high-voltage phase shifter L (signal BLKSEL), and the switches in the switch SW with signal lines SSGD0 / 1 / 2 / 3, CG, and SSGS connected to the current path, are turned off. Conversely, when the output of the block BLK in the AND circuit AN becomes L level, the switch connected to the current path via the output of the high-voltage phase shifter L (signal BLKSEL), and the switches in the switch SW with signal lines SSGD0 / 1 / 2 / 3, CG, and SSGS connected to the current path, are turned on.

[0131] Thus, for the selected block BLK, the voltage from signal lines SSGD0 / 1 / 2 / 3 and SSGS is supplied to the select gate lines SGD0 / 1 / 2 / 3 and SGS, and the voltage from signal line CG is supplied to the word line WL. That is, when signal R / Bn is busy, the signal BLKSEL for selecting BLK becomes H level, and signal line CG becomes essentially the same waveform as the word line WL for selecting block BLK. Furthermore, for the non-selected block BLK, the voltage from signal lines USGD and USGS is supplied to the select gate lines SGD0 / 1 / 2 / 3 and SGS. Additionally, WL becomes a floating state, eventually becoming the VSS voltage due to the junction-drain characteristics of SWn2 over time.

[0132] (Write action 1)

[0133] Figure 9 It is a waveform diagram showing the write operation, with time taken in the horizontal direction and voltage taken in the vertical direction.

[0134] When writing data to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to a value corresponding to the data value. If a programming voltage VPGM and a bit line voltage are applied to the memory cell transistor MT, electrons are injected into the charge storage layer 37, and the threshold voltage rises. By increasing the programming voltage VPGM, the amount of electron input can be increased, thereby increasing the threshold voltage of the memory cell transistor MT. However, due to the non-uniformity of the memory cell transistors MT, even when the same programming voltage VPGM is applied, the amount of electron injection varies for each memory cell transistor MT. The temporarily injected electrons are retained until an erase operation is performed. Therefore, the programming voltage VPGM is gradually increased while performing multiple programming operations and verification operations (loops) to verify the programming operations, in a manner that does not exceed the range of the threshold voltage that should be set for each memory cell transistor MT. In addition, during the write operation, an erase operation is first performed to restore the threshold voltage of the memory cell transistor MT to the Er level (erasure level).

[0135] Thus, in the write operation, a programming loop containing programming and verification actions is repeated multiple times, and in each loop, the programming voltage VPGM increases. Figure 9 The example shows a write operation performed in n loops, where in the first loop, Prog1 is programmed and Pvfy1 is verified; in the second loop, Prog2 is programmed and Pvfy2 is verified; and in the nth loop, Progn is programmed and Pvfyn is verified.

[0136] Figure 9The waveform from the m-th loop is shown. That is, it shows that in the m-th loop, Progm is programmed and Pvfym is verified, in the (m+1)-th loop, Progm+1 is programmed and Pvfym+1 is verified, and in the n-th loop, Progn is programmed and Pvfyn is verified.

[0137] During programming, a programming voltage VPGM (dashed line) that gradually increases with each cycle is applied to the select word line WL (hereinafter also referred to as selWL). A specific voltage VPASS (solid line) lower than the programming voltage VPGM is applied to the other non-select word lines WL (hereinafter also referred to as uselWL). Furthermore, during programming, a ground voltage VSS is applied to the select gate line SGS, a voltage (dashed line) is applied to selSGD to turn on the select gate transistor ST1, and a voltage (solid line) is applied to uselSGD to turn off the select gate transistor ST1. Additionally, a ground voltage VSS (dashed line) is applied to the bit line BL (Prog) connected to the memory cell transistor MT that is being written to, and a specific voltage (solid line) is applied to the bit line BL (Inhibit) connected to the memory cell transistor MT that is not being written to. Finally, a specific voltage is applied to the source line CELSRC to more reliably turn off the select gate transistor ST2.

[0138] Therefore, when a charge (electrons) corresponding to the programming voltage VPGM is injected into the charge storage layer of the memory cell transistor MT during writing, the threshold voltage of the memory cell transistor MT rises. Furthermore, the threshold voltage of the memory cell transistor MT during non-writing is maintained by preventing the injection of electrons into the charge storage layer.

[0139] During the verification process, a verification voltage (dashed line) corresponding to each level is applied to the select word line selWL, and a specific voltage VREAD (solid line) is applied to the non-select word line uselWL to turn on each memory cell transistor MT. Additionally, during the verification process, a voltage is applied to the select gate line SGS to turn on the select gate transistor ST2, a voltage is applied to selSGD to turn on the select gate transistor ST1 (dashed line), and a voltage is applied to uselSGD to turn off the select gate transistor ST1 (solid line). Furthermore, a specific voltage is applied to the bit line BL, and a ground voltage VSS is applied to the source line CELSRC. Figure 9 As shown, when the write operation is performed during the L level (busy period) of the signal R / Bn, and the write operation ends, the signal R / Bn changes to the H level.

[0140] Furthermore, in order to apply a specific voltage to the bit line BL, as described above, a control signal BLC is supplied to the transistor 52 within the sense amplifier unit SAU. That is, a relatively high level control signal BLC is provided to the transistor 52 connected to the bit line BL during programming, and a relatively low level control signal BLC is provided during verification, and the bit line BL is connected to the memory cell transistor MT that is being written to. Thus, as described above, during verification, the bit line BL is fixed at a relatively low fixed voltage (e.g., 0.5 V).

[0141] Therefore, when the verification voltage selWL applied to the memory cell transistor MT connected to the read target is higher than the threshold voltage, current easily flows through the channel; when the verification voltage applied to selWL is lower than the threshold voltage, current does not easily flow through the channel. By reading out the state of the current flowing through the channel through the sensing amplifier unit group 28, it can be determined whether the threshold voltage of the memory cell transistor MT has reached the desired level. Furthermore, the case where the threshold voltage of the memory cell transistor MT reaches the desired level is called "verification passed," and the case where the desired level is not reached is called "verification failed."

[0142] (Vertical ascent)

[0143] Figure 10 This is a diagram illustrating the word line (WL) creep of the selected block after verification is performed before the write sequence ends and all blocks become non-selected. Figure 10 It takes time in the horizontal direction and voltage in the vertical direction to represent the voltage waveform of each part. Additionally, Figure 10 In the diagram, the period indicated by the arrow is on a logarithmic scale, with the left end of the arrow marking 10. -6 The timescale is in seconds; the scale to the right of the arrow indicates 10. 3 Seconds. Hereinafter, it will be labeled as Time = Log Scale 1E-6 to 1E+3[s].

[0144] Figure 10 In this context, selWL and uselWL represent the select word line and non-select word line, respectively; Ch represents the channel region; SGS represents the select gate line; BL represents the bit line; and CELSRC represents the source line. Furthermore, as mentioned above, the select gate line SGD used to drive the memory cell transistor MT that is to be written to or read from is called selSGD, and the select gate line SGD other than selSGD is called uselSGD.

[0145] In the three-dimensional memory cell array 20, the channel region of the memory cell transistor MT is not directly connected to the substrate (i.e., the p-well region 30), but is connected to the bit line BL and the substrate via select gate transistors ST1 and ST2, respectively. Therefore, when the select gate transistors ST1 and ST2 are turned off, the charge in the channel region cannot simply move to the bit line BL and the substrate, but escapes slowly as the leakage current of the select gate transistors ST1 and ST2.

[0146] In this embodiment, the phenomenon of voltage rise in word line WL due to capacitive coupling between the channel region of memory cell transistor MT (or the channel region of NAND string NS) and word line WL is called WL creep.

[0147] For example, as a data read operation, there is a verification process following the programming operation (programming verification). At a certain moment during the programming verification, for example, the voltage (Ch) of the channel region is the ground voltage VSS (0 V), the select word line WL is the verification voltage Pvfy (dashed line), the non-select word line is the voltage VREAD (solid line), the select gate line SGD of the select string is selSGD, the select gate line SGS is the voltage VSG, and the select gate line SGD of the non-select string is uselSGD (here, the voltage VSS). Additionally, a specific voltage is applied to the bit line BL, and the source line CELSRC is the ground voltage VSS. At time t0, when the read operation ends, each voltage is discharged to VSS or a potential near it. After resetting in a manner that the write state of the memory cell remains unchanged, the clock select signal BLKSEL is reset to level L and disconnected from the SSGD0 / 1 / 2 / 3, CG0-63, and SSGS lines. On the other hand, BLKSELn is restored to level H, and USGD and USGS are connected to the select gate lines of block BLK respectively. Furthermore, since WL is an unbiased switch when BLKSEL is reset to L, it becomes floating. After these specific actions are completed, the signal R / Bn changes from L level to H level, restoring the ready state.

[0148] At this time, through the capacitive coupling between word line WL and the channel region of the NAND string NS, the potential of the channel region drops to a negative value (time t1). Afterwards, the charge in the channel region gradually escapes to the substrate and / or bit line BL due to leakage current, and the potential of the channel region recovers to the ground voltage VSS (0 V). When the potential of the channel region recovers to the ground voltage VSS, the word line WL, which is capacitively coupled to the channel region, rises to a creep voltage. The voltage of the word line WL after creeping gradually decreases due to the junction leakage current of the transistor switch SWn2 that drives the word line WL. That is, after transitioning from the ready state to the busy state (signal R / Bn changes from L level to H level) and the line decoder 26 enters the stop state, WL creeps. Furthermore, the maximum value of the creep voltage Vmax is Vcr_Read (>Vcr_Prog)V.

[0149] The state of the memory cell transistor MT when the word line WL is not creeping is called the 1st (first) read state, and the state of the memory cell transistor MT when the word line WL creeps is called the 2nd (second) read state. Furthermore, the WL creeping occurs not only during programming verification but also during normal data reads.

[0150] In 3D NAND flash memory, channels are generally formed within polysilicon to allow cell current to flow. These channels contain numerous trap levels, and the visible cell threshold varies depending on the degree to which electrons are embedded in these trap levels. When reading from a state that has been idle for a long time, the word line WL is completely discharged to 0V, and the proportion of electrons embedded in the trap levels directly below the gate insulating film 36 decreases, resulting in less current obstruction and a slightly lower visible cell threshold. Conversely, once readout occurs, electrons are embedded in these trap levels at a certain ratio, obstructing current, thus resulting in a higher visible cell threshold. Designating the former state as the 1st read state and the latter as the 2nd read state, the difference in cell threshold is observed to be approximately tens of mV, which, especially in TLC or QLC products, increases the number of readout errors. Therefore, for stable data readout, either the 1st or 2nd read state is required. Considering the relatively long time required to transition from the 2nd read state to the 1st read state after write and readout operations, the 2nd read state is preferred.

[0151] Therefore, consider the following method: maintaining the 2nd read state through a refresh read operation, wherein the refresh read operation is performed by applying a read voltage pulse (hereinafter referred to as the all-string read pulse) that periodically applies a voltage pulse (hereinafter referred to as the all-string read pulse) to the word lines WL of all strings of all blocks to turn on the memory cell transistor MT. In the above (write operation 1), since the read operation, i.e., verification, is performed in the last loop of the write operation, the 2nd read state can be maintained for a specific time after the write operation, so there is no need to use the refresh read operation of the all-string read pulse.

[0152] In addition, although it is stated that all string reading actions apply all string reading pulses to the word lines WL of all strings in the block, as long as the 2nd reading state can be maintained, all string reading pulses can also be applied to a portion of the word lines WL of all strings.

[0153] (Write action 2)

[0154] To shorten write time (tPROG), the verification method in the final loop of the write operation is sometimes omitted. Figure 11 The waveform diagrams represent other examples of write operations, with time taken in the horizontal direction and voltage taken in the vertical direction. Figure 11 The example omits the validation of the final loop in the write action. Furthermore, Figure 12 This is a waveform diagram used to illustrate the WL creep at this point. Additionally, Figure 12 The horizontal scale is Time = Log Scale 1E-6 to 1E+2 [s] (Time = logarithmic scale 1E-6 to 1E+2 [s]).

[0155] According to Figure 11 and Figure 9 The comparison clarifies that in the final loop (the nth loop), programming actions are performed, but verification actions are omitted. In this case, Figure 12 During the H level of the signal R / Bn (ready period), WL creep also occurs. However, because the number of cells written is smaller in the final cycle, a relatively large number of channels become floating based on the programming voltage. Figure 12 Before t0, the solid line Ch (Inhibit) shows that the voltage in a very small number of channel regions becomes the ground voltage VSS (0 V). Figure 12 The dashed line Ch(Prog) before t0. Therefore, when the word line WL discharges from the programming voltage to the ground voltage VSS, the number of channels with a negative channel voltage is smaller, and as a result, the voltage of WL creeping up is also smaller.

[0156] In other words, after the final programming pulse of the programming cycle is applied, and the write operation ends, the WL creep fluctuation is small immediately after the final programming pulse is applied, making it easy to return to the 1st read state. Therefore, considering the application of the final programming voltage, pulses that apply, for example, voltage VREAD to all word lines WL of the block (i.e., all word string read pulses) are used to set it to the 2nd read state.

[0157] (All string reading actions)

[0158] Figure 13 It is a waveform diagram that takes time in the horizontal direction and voltage in the vertical direction, representing other examples of write operations. It shows an example of all string read operations performed as the first voltage application operation at the end of the programming loop.

[0159] According to Figure 11 and Figure 13 The comparison makes it clear, Figure 13 In this example, the verification operation is omitted in the final loop (the nth loop). After the programming operation, a voltage, for example, VREAD, is applied to both selWL and uselWL. Furthermore, in this case, selSGD, uselSGD, and the select gate line SGS are set to the voltage (thick line) that turns on the select gate transistors ST1 and ST2, and the control signal BLC is set to a specific voltage (thick line), thereby supplying ground voltage VSS to the bit line BL. Additionally, CELSRC is set to ground voltage VSS. Furthermore, the control signals HLL and XXL are at level L, and the control signals BLS and node / LAT are at level H. Transistors 50, 55, and 56 are off, while transistors 52, 53, and 54 are on. Thus, in the final loop, after the programming operation, all string read operations are performed, the write operation ends, and a transition to the 2nd read state occurs.

[0160] Additionally, if the select gate transistor ST2 is turned on, the ground voltage VSS can be supplied from the source line CELSRC to the bit line BL. Therefore, it is not necessary to turn on the select gate transistor ST1. In this case, as shown by the thin lines, selSGD, uselSGD, and the control signal BLC can also be the ground voltage VSS.

[0161] In other words, in all string read operations, there is no selection of word line WL, and no application of voltages such as VREAD to all word lines WL of all NAND strings NS. Furthermore, all string read operations do not require sensing by the sensing amplifier unit group 28, nor do they require voltage changes to bit line BL, making the operation relatively simple. As per... Figure 9 and Figure 13 The comparison clearly shows that the time required for all string reading operations is shorter than the time required for programming verification.

[0162] However, Figure 13 In the example shown, although it is not the time required for programmatic verification, it is similar to... Figure 11 Compared to the write operation, the write time tPROG also increases the time required for all string read operations.

[0163] (Control of the control circuit)

[0164] Therefore, in this embodiment, during the write operation, the control circuit 24 determines, according to each select word line to which a programming voltage is applied, whether to omit all string read operations that provide read pulses to all string strings before the end of the write operation performed by that word line. In other words, during the write operation performed by each word line, i.e., each unit group CU, it determines whether to perform or omit all string read operations before the end of the write operation of each unit group CU. If all string read operations are omitted, the time tPROG is shortened accordingly. That is, in this embodiment, according to each select word line WL to which a programming voltage is supplied during the write operation, it determines whether to perform all string read operations after the programming operation using the select word line WL. Thus, in this embodiment, for the write operation of a block BLK, select word lines that perform all string read operations and select word lines that do not perform them are designed, thereby shortening the average write time tPROG.

[0165] In the following description, the specific word line WL used for programming operations after applying programming voltage VPGM and then performing all string read operations will be referred to as the object word line WL for all string read operations. The specific word line WL used for programming operations after applying programming voltage VPGM and then not performing all string read operations will be referred to as the non-object word line WL for all string read operations. In this embodiment, the control circuit 24 determines which word line WL is the object word line and which is the non-object word line for all string read operations in order to effectively generate the 2nd read state while suppressing the write time tPROG.

[0166] Figure 14 and Figure 15 This is a waveform diagram that uses time in the horizontal direction and voltage in the vertical direction to illustrate the method used to determine whether a word line WL is the target word line or a non-target word line WL for all string reading operations. Additionally... Figure 14 and Figure 15 The horizontal scale is Time = Log Scale 1E-6 to 1E+3 [s] (Time = logarithmic scale 1E-6 to 1E+3 [s]).

[0167] Figure 14 Separating the cell write level from the WL creep amount indicates that after writing all memory cell transistors MT within the block to the same level, all word string read operations are performed, followed by the WL creep amount during the ready period of signal R / Bn.

[0168] Read(All-Erased) represents the WL creepage for all word read operations when all memory cell transistors MT within the block are at Er level, and Read(All-“A”Programmed) represents the WL creepage for all word read operations when all memory cell transistors MT within the block are at A level. Similarly, Read(All-“D”Programmed) and Read(All-“G”Programmed) represent the WL creepage for all word read operations when all memory cell transistors MT within the block are at D level and G level, respectively.

[0169] According to Figure 14 It is clear that when writing at a higher threshold voltage level, the higher the voltage of the WL creep operation for all string read operations.

[0170] Figure 15 This represents the relationship between the WL creep voltage and the ready period (H level) of the signal R / Bn after all word string read operations during the block write process. Additionally, the case where the total number of word lines WL is 64 is shown. Read(All-Erased) indicates the change in WL creep voltage after all word string read operations when all cells in a block are at Er level (erasure state). Furthermore, Read(WL0-15 All-“G”, Other=Erased) indicates the change in WL creep voltage after all word string read operations when all memory cell transistors MT connected to word lines WL numbers 0-15 record G level data, and other memory cell transistors MT are at Er level. Generally, an erasure operation is performed before data writing, and programming voltages for the write operation are applied sequentially from word line WL number 0 (smallest number) to larger word line WL numbers. Read(WL0-15 All-“G”, Other=Erased) represents the change in WL creep voltage after all word string read operations in a certain block, after writing the G level to all memory cell transistors MT connected to the 16 word lines WL.

[0171] Similarly, Read(WL0-31 All-“G”, Other=Erased) represents the change in WL creep voltage after all word string read operations following a G-level write to all memory cell transistors MT connected to the 32 word lines WL in a certain block. Read(WL0-47 All-“G”, Other=Erased) represents the change in WL creep voltage after all word string read operations following a G-level write to all memory cell transistors MT connected to the 48 word lines WL in a certain block. Read(WL0-63 All-“G”, Other=Erased) represents the change in WL creep voltage after all word string read operations following a G-level write to all memory cell transistors MT connected to the 64 word lines WL in a certain block.

[0172] Furthermore, the dashed waveform After WL63 String3 Final Program Pulse (All-“G”) indicates that the final loop of the block write operation only involves the change in the WL creep voltage after the programming operation. Knowing that the creep voltage is small when the write operation ends immediately after the programming operation, it is easy to transition to the 1st read state.

[0173] According to Figure 15 It is clear that the more word lines (WL) for which programming voltage is applied during a write operation, the greater the change in WL creep voltage after all subsequent string read operations. Conversely, when fewer word lines (WL) for which programming voltage is applied during a write operation, the change in WL creep voltage after all subsequent string read operations is relatively small. In other words, during a write operation, when fewer word lines (WL) for which programming voltage is applied, the WL creep fluctuation is smaller, and even after applying the programming pulse and performing all string read operations, the transition to the 1st read state is relatively short, resulting in a smaller effect from all string read operations. Therefore, it is considered that all string read operations can be omitted.

[0174] Generally, the data levels recorded in each memory cell transistor MT of the memory cell array 20 are random and rarely adjusted. Figure 14 The writing method shown is quite difficult to implement by controlling all string reading actions according to each level.

[0175] Therefore, based on Figure 15 Based on this understanding, during the write operation, when the number of word lines WL with applied programming voltage is small, the control circuit 24 omits all word string read operations to shorten the write time tPROG. Furthermore, during subsequent programming operations using word lines WL, all word string read operations are performed before the write operation ends, resulting in a transition to the 2nd read state.

[0176] When a certain number of word lines WL with applied programming voltage are reached, all word string read operations are performed. It is preferable that the configuration can be changed according to the characteristics of the device. Therefore, it is preferable that information indicating all word string read operations are performed when a certain number of word lines WL with applied programming voltage are reached (hereinafter referred to as all word string read operation information) is recorded and stored, for example, in block BLKX of memory cell array 20, and that the recorded all word string read operation information can be appropriately changed. Furthermore, block BLKX is a region that stores information related to the operation of non-volatile memory 2.

[0177] The control circuit 24 can also, after power is applied, read all string reading action information from block BLKX of the memory cell array 20, store it in register 24a, and control all string reading actions based on the information. Alternatively, the register storing all string reading action information can also be located in the logic control circuit 22.

[0178] (effect)

[0179] Next, refer to Figure 16 The diagrams illustrate the operation of the implementation method configured as described above. Figure 16 This indicates the period during which all string reading operations were stopped (or performed).

[0180] Figure 16 This example shows a block BLK consisting of four string units Str0, Str1, Str2, and Str3, and a NAND string NS consisting of 16 memory cell transistors MT (16 word lines WL). However, the number of string units in the block BLK and the number of word lines WL in the NAND string NS are not limited to these examples.

[0181] Figure 16 The numbers in the boxes of columns Str0 to Str3 indicate the writing order of each unit group (CU) connected to a word line WL within a single string unit. In other words, a word line WL consists of 4 unit groups (CU) for each string unit. Figure 16 In the example, the word line WL numbering changes from the word line WL configured on the select gate line SGS side to the word line WL configured on the select gate line SGD side, becoming WL0, WL1, WL2, ..., WL15. Furthermore, when observing the order of data writing to the cell group CU in units of word lines WL, Figure 16 In the example on the left, as shown by the arrow, the word lines WL are numbered WL0, WL1, WL2, ..., WL15 in sequence. Figure 16In the example on the right, as indicated by the arrows, the word lines WL are numbered WL15, WL14, WL13, ..., WL0. That is, the order in which data is written to the unit group CU, when viewed in units of word lines WL, can be either sequential from the select gate line SGS side or sequential from the select gate line SGD side. The method of naming the word lines WL whose numbers increase from 0 according to this writing order is called the logical word line number LWL. In other words, when word lines WL are represented by logical word line numbers LWL, writing is always performed in order from the smallest number towards the largest number.

[0182] In this embodiment, when power is connected, the control circuit 24 reads all string read operation information from block BLKX of the memory cell array 20 and stores it in register 24a. During write operations, the control circuit 24 controls all string read operations based on the all string read operation information.

[0183] For example, all string read action information consists of the "0", "1", "2", ... information in specific F_ASTRREAD_BORDER 0: LWL0-(disable), 1: LWL4-, 2: LWL8-, 3: LWL12-. For instance, all string read action information "0" indicates that the WL for omitting all string read actions is not set, meaning that all string read actions are performed on all word line WLs. Furthermore, all string read action information "1" indicates that all string read actions are omitted during logical word line numbers LWL0-3, and are performed during logical word line numbers LWL4-15. Figure 16 The thick box on the left indicates that, in the case described, all string reading actions are omitted (WL).

[0184] In this case, the control circuit 24 performs a write operation on the unit group CU to which the programming voltage is applied by the logic word line number LWL0-3, without performing all word string read operations, that is... Figure 11 The write operation is shown. Furthermore, in this case, the control circuit 24 performs all string read operations on the cell group CUs to which the programming voltage is applied by logic word line numbers LWL4-15 before the write operation ends. Figure 13 The write action shown.

[0185] In addition, for example, the string reading action information "2" means that all string reading actions are omitted during logic word line numbers LWL0-7, and all string reading actions are performed during logic word line numbers LWL8-15. Figure 16 The thick box on the right indicates that, in the aforementioned case, all string reading actions are omitted (WL).

[0186] In other words, in the aforementioned case, the control circuit 24 performs a write operation on the unit group CU to which the programming voltage is applied by the logic word line number LWL0-7, without performing all string read operations. Figure 11 The write operation is shown. Furthermore, in this case, the control circuit 24 performs all string read operations on the cell group CUs to which programming voltages are applied by logic word lines LWL8-15 before the write operation ends. Figure 13 The write action shown.

[0187] Thus, during a write operation, the target word line WL and the non-target word line WL are determined to be the word lines for which all string reads are performed before the write operation of each unit group CU ends. During the write operation of the non-target word line WL, all string read operations are omitted. As a result, the write time tPROG can be shortened. Furthermore, it is believed that by performing all string reads before the write operation of the word line WL that is the target of all string reads ends, sufficient WL creep is generated, thus effectively maintaining the 2nd read state.

[0188] Thus, in the first embodiment, since all string reading operations are omitted before the writing operation using a portion of the word line WL is completed, the writing time tPROG can be shortened.

[0189] Generally, memory cell transistors (MTs) can be configured as SLC (Single-Level Cell) capable of storing 1 bit (2-value) data, MLC (Multi-Level Cell) capable of storing 2 bits (4-value) data, TLC capable of storing 3 bits (8-value) data, or QLC (Quad-Level Cell) capable of storing 4 bits (16-value) data. In particular, it is assumed that when the memory cell transistor MT is a TLC or QLC or higher, the control of all string read operations in this embodiment is effective.

[0190] Furthermore, the description illustrates an example where, in the final loop of the write operation, the verification operation is omitted, and a full string read operation using all string read pulses is performed before the write operation ends. However, when the non-volatile memory 2 is in standby mode without being given instructions, a refresh read operation can also be performed while changing the block BLK at regular intervals and giving all string read pulses.

[0191] Figure 17 and Figure 18 It is a waveform diagram showing the waveforms of each part at this time. Figure 17 This illustrates the write operation for the word line WL of all string read objects with relatively large logical word line numbers LWL that have already been written. Figure 18This illustrates the write action of non-object word line WL for all word string reads with a relatively small logical word line number LWL that has already been written. Figure 17 In the example, before the write operation that omits the verification action in the final loop ends, all string read operations are performed. After all string read operations, all string read operations are repeated at regular intervals during the L level of the signal R / Bn (busy period). On the other hand, for blocks where writing has not reached a specific word line WL, such as Figure 18 As shown, omitting periodic refresh and read operations reduces power consumption.

[0192] The logical word line number that becomes the boundary of all string read operations and is not the object can be the same or different before the write operation ends and during refresh during standby.

[0193] Furthermore, the intervals between refresh and read operations can be multiple. For example, if the write operation is completed up to logic word line numbers LWL0-3, no refresh or read operation is performed. If the write operation is completed up to logic word line numbers LWL4-7, a refresh or read operation is performed at regular intervals t1. If the write operation is completed up to logic word line numbers LWL8-15, a refresh or read operation is performed at regular intervals t2. For example, the regular interval t1 can also be shorter than t2.

[0194] also, Figure 17 The diagram illustrates an example of the L-level period (busy period) of the signal R / Bn corresponding to the duration of all string read operations in a single operation. This is an example when the number of blocks targeted for refresh read operations is small. When the number of blocks targeted for refresh read operations is large, in order to keep the amount of current flowing in a single operation below a certain level, consider the case where multiple blocks are simultaneously and slowly charged and discharged, or where refresh read operations are performed on different blocks multiple times.

[0195] In the former case, the total string reading action, which is a refresh reading action, takes longer than the total string reading action before the write action ends.

[0196] In the latter case, the L level period of the R / Bn signal requires a longer time than all string read operations of one BLK value. In other words, when volatile memory 2 is in standby mode, refresh read operations can also be performed multiple times during the L level period of the R / Bn signal.

[0197] In order to perform these actions separately from the block BLK, it is necessary to pre-store in the register 24a of the control circuit the information of which logic word line number LWL each BLK is writing to, which increases the chip cost. However, if all BLKs are set to the same control, then the aforementioned storage circuit is not necessary.

[0198] (The actions of all string reading control circuits)

[0199] Figure 19 This is a flowchart illustrating an example of the specific actions involved in reading all the strings in the control circuit 24.

[0200] For example, word lines that will be the target of all string read operations can be pre-defined based on the cell evaluation before shipment from the factory. Based on this setting, all string read operation information can be pre-registered in block BLKX of the memory cell array 20.

[0201] After being powered on, the non-volatile memory 2 receives the instruction FFh to initialize the chip's internal structure. The control circuit 24 then executes the initialization command FFh according to the instruction. Figure 19 In step S1, ROM information containing all string read operation information is read from block BLKX and stored in various registers. For example, all string read operations are stored in register 24a. When control circuit 24 receives a write instruction and address from memory controller 3 (S2), the write operation begins. Consequently, signal R / Bn becomes busy (S3).

[0202] Figure 20 It is used to explain Figure 19 A diagram of the address received in S2. Figure 20 The address input to the input terminals DQ0-DQ7 of the non-volatile memory 2, respectively, is shown. The column address is input via loops 1 and 2 of specific loops 1-6. "Don't Care" indicates a non-fixed bit. In loop 3, the string cell address is input via input terminals DQ0 and DQ1. The word line address is input via input terminals DQ2-DQ7 of loop 3 and input terminal DQ0 of loop 4. In this specification, the combined address of the string cell address and the word line address is referred to as the page address. Furthermore, in loops 4-6, the plane address, block address, and chip address are extracted into the non-volatile memory 2. The input address is stored in the address register of register 23.

[0203] During the write operation, control circuit 24 determines whether the write sequence ends after applying a programming pulse to the select word line WL, or after performing a programming verification action (S4) following the programming action. In other words, in the final loop of the write operation, control circuit 24 determines whether to perform only the programming action on the select word line WL, or to perform both the programming action and the programming verification action (S4). If the write sequence ends after the programming verification action, control circuit 24 terminates the write operation in S7. As a result, signal R / Bn becomes ready (S7).

[0204] On the other hand, when the writing sequence ends after the programming pulse is applied, the control circuit 24 determines in the next S5 whether the page address to be written corresponds to the object word line WL of all string reading operations.

[0205] Control circuit 24 reads the word line address stored in address register 23, controls the write operation, and performs the determination in S5. That is, control circuit 24 determines whether the address of the selected word line WL to which the programming voltage VPGM is applied is the target word line WL for all string read operations specified by the all string read operation information. If the address of the selected word line WL is not the target word line WL for all string read operations, control circuit 24 ends the write operation in S7. Furthermore, if the address of the selected word line WL is the target word line WL for all string read operations, control circuit 24 executes all string read operations (S6).

[0206] Thus, NAND flash memory typically performs write operations within a block in the order of logical word line numbers (LWL). Therefore, based on the page address or word line address received along with the write instruction, the number of completed write operations (WL) can be determined, and it can be decided whether to perform all word string read operations.

[0207] (Cache programming)

[0208] However, the write operation includes the following actions: the basic programming action of sequentially writing data into memory for each individual page; and the action of continuously and efficiently programming multiple pages by performing programming actions while simultaneously inputting data for the next page to be written (hereinafter referred to as cache programming action).

[0209] Figure 21 It is a sequence diagram that represents the basic programming actions performed on each individual page. Figure 22 It is a timing diagram representing cache programming actions. Figure 21 and Figure 22 The diagram shows the instruction latch start signal CLE, chip start signal CEN, write start signal WEN, address latch start signal ALE, read start signal REn, ready / busy signal R / Bn, and signals DQx (e.g., DQ0~DQ7).

[0210] The input / output circuit 21 is controlled by the logic control circuit 22 and communicates with the memory controller 3 via a bus to transmit and receive signals DQ (e.g., DQ0~DQ7). When the input / output circuit 21 is given the signal DQ, it receives the signal DQ as data synchronously with the write start signal WEN. Furthermore, corresponding to the read start signal REn given to the logic control circuit 22, the input / output circuit 21 sends the data read from the memory cell array 23 as the signal DQ to the memory controller 3.

[0211] like Figure 21 As shown, at time t0, when the instruction latch start signal CLE becomes active, the input / output circuit 21 extracts the instruction transmitted as signal DQ based on the signal supplied from the logic control circuit 22 and stores it in the instruction register of register 23. Furthermore, at time t1, when the signal ALE becomes active, the input / output circuit 21 extracts the address transmitted as signal DQ based on the signal supplied from the logic control circuit 22 and stores it in the address register of register 23. Additionally... Figure 21 The diagram shows the addresses of four loops, but it can also be seen as follows: Figure 20 As shown, the address has 6 cycles, but other cycle numbers are also possible. Input / output circuit 21, following the instruction and address, synchronously receives data (Data(Din)) after time t2 with the write start signal WEN. At time t3, the instruction (10h) is received by the instruction latch start signal CLE. The reception of this series of signals DQ occurs during the R / Bn ready period.

[0212] When the R / Bn signal changes to L level (busy state), a data write operation is initiated. The write operation is performed in page (cell group) units. Figure 21 In the example, during the time interval t2~t3, one page of data (Data) is transmitted, and this one page of data is written during the L level of the signal R / Bn. After the writing is completed and the signal R / Bn changes to the H level, a... Figure 10 , Figure 12 , Figure 14 and Figure 15 The WL creep pattern is shown.

[0213] Thus, in the basic programming operation of programming each single page according to the 10h instruction, before the end of the write operation, all string reading operations are performed or omitted based on all string reading operation information. Furthermore, R / Bn changes to L after inputting 10h, maintains the L level until all string reading operations are performed or omitted, and then returns to H.

[0214] On the other hand, in cache programming operations, such as Figure 22As shown, at time tN0, when the instruction latch start signal CLE becomes active, the input / output circuit 21 extracts the instruction transmitted as signal DQ based on the signal supplied from the logic control circuit 22 and stores it in the instruction register of register 23. Furthermore, at time tN1, when the signal ALE becomes active, the input / output circuit 21 extracts the address (Add) transmitted as signal DQ based on the signal supplied from the logic control circuit 22 and stores it in the address register of register 23. For example, the latter half of the address (Add) is the page address (PN) of page PN. Following the instruction and address, at time tN2, the input / output circuit 21 synchronously receives the data written to page PN (hereinafter referred to as data DN) with the write start signal WEn.

[0215] The data DN repeats as follows: data is cached from input / output circuit 21 to data latch circuit XDL in data register 29 via register 23, then the write data to XDL is transferred to ADL / BDL / CDL, thereby releasing XDL again to allow input data. At time tN3, when the instruction (15h) is received by the instruction latch start signal CLE, the programming of the cached data begins. The reception of this series of signals DQ occurs during the ready period of signals R / Bn.

[0216] Furthermore, at times t(N+1)1~t(N+1)2, the page address (P(N+1)) is received, and at times t(N+1)2~t(N+1)3, the data D(N+1) written to the page address (P(N+1)) is received. Similarly, at times t(N+P)1~t(N+P)2, the page address (P(N+P)) is received, and at times t(N+P)2~t(N+P)3, the data D(N+P) written to the page address (P(N+P)) is received.

[0217] Data DN received between times tN2 and tN3 is transmitted from the data latch circuit XDL to the corresponding data latch circuit (ADL, BDL, or CDL) within the sense amplifier unit SAU during the busy period of signal R / Bn, via an instruction received after time tN3 (15h). When the transmission is complete, the data latch circuit XDL becomes empty, and signal R / Bn transitions from a busy state to a ready state. When signal R / Bn becomes ready, non-volatile memory 2 can receive the instruction, address, or data (N+1) for the next write operation from memory controller 3. Typically, a write operation involving multiple cycles is performed in parallel with the reception of the next data D (N+1), and the cycles include at least the programming operation of data DN. Similarly, the write operation of data D (N+1) is performed in parallel with the reception of data D (N+2). An instruction (10h) received after time t(N+P)3 indicates that data D (N+P) has begun programming the data of the last page of the cache programming operation. The write operation is performed on data D(N+P) after the write operation of data D(N+P-1), and the programming of data D(N+P) ends before time tEP, at which point the signal R / Bn becomes ready. Additionally, information such as write operation success / failure, from the non-volatile memory 2 is output via the read status instruction 70h.

[0218] In the cache programming operation performed on each consecutive page, the write operation ends at the end of the consecutive page. In pages within a consecutive page, because the time between writing to the next page is short, the period without applying bias voltage to the word line is extremely short, so all string read operations are omitted. In the operation performed on each consecutive page, before the end of the write operation for each consecutive page (one quarter before time tEP), all string read operations are performed based on the information from all string read operations, or all string read operations are omitted.

[0219] Furthermore, since all string pulses are applied in block units during all string read operations, in the case of cache programming operations that write to consecutive pages, it is sufficient to perform all string read operations once per block.

[0220] Next, for the example of writing to the cache programming operation, refer to... Figures 23 to 27 The diagram below provides an explanation. Figures 23 to 27 The signal R / Bn is shown, and above the signal R / Bn are examples of input for instructions, data, and addresses. Below the signal R / Bn are examples of page data writing and all string reading operations. Figures 23 to 27 In this context, ProgN represents a write to page N, and ProgM represents a write to page M.

[0221] Figures 23 to 25The example illustrates writing two pages of data programmed via cache programming into the same block BLK. Furthermore, Figures 23 to 27 This is an example of transmitting page data by dividing it into three parts: Lower, Middle, and Upper. Figures 23 to 27 In the code, 01h, 02h, and 03h represent the Lower, Middle, and Upper pages, respectively; 80h represents the write command; add(N) and add(M) represent addresses; Din represents data; 1Ah, 10h, and 15h represent commands; and R represents the execution of all string reading actions.

[0222] Figure 23 The example illustrates data for page N, input in the order of instructions within the slash boxes for the Lower, Middle, and Upper pages; and data for page M, input in the order of instructions without the slash boxes for the Lower, Middle, and Upper pages. The data for page N is cached in the data latch circuit XDL, and during the period shown in ProgN, it is transferred to any one of the data latch circuits ADL, BDL, and CDL and written. During the programming ProgN, the following actions are repeated: data for the Lower, Middle, and Upper pages of page M is cached in the data latch circuit XDL, sequentially transferred to ADL / BDL / CDL which are released sequentially as each write level completes, thereby releasing XDL again to allow data input.

[0223] Figure 23 In this code, `add(N)` and `add(M)` share the same address of block BLK, and the data for page N and page M are written to the same block BLK. At the end of the programming process `ProgN` for page N, the data for page M has been cached and scheduled for programming. Furthermore, the block BLK for writing data to page N is the same as the block BLK for writing data to page M. Therefore, at the end of the programming process `ProgN` for page N, all string reading operations are omitted.

[0224] Because instruction 10h was used to program the final page data of the cache programming action, all string reading actions are performed when the programming of page M's data ProgM ends.

[0225] Thus, in the cache programming of the 15h instruction, even if the timing of all string read operations is based on all string read operation information, the page data to be programmed next is cached and programmed in advance. Furthermore, if the address of the page data to be programmed next is the same address within the same block BLK as the address of the page data written in the previous moment, all string read operations are omitted. In addition, R / Bn becomes L after inputting 15h, but is controlled to return to H at the point when data register 29 is released (when data DN is transferred from data register 29 to sense amplifier unit group 28). This allows for parallel data input and writing to memory units, improving system performance.

[0226] Figure 24 In the example, page M is a page preceding the last page in the cache programming (an intermediate page). The example shown illustrates that, even when programming for the next page to be written to page M is not scheduled, all string read operations are not omitted, even when programming ProgM ends. For example... Figure 24 As shown, during the programming of page N's data using ProgN, because the data of page M is cached and programming is scheduled, all string reading operations are omitted before the programming of page N's data using ProgN ends. However, according to instruction 15h, during the programming of page M's data using ProgM, the data of the next page of page M's data is not cached, and no programming is scheduled. Therefore, all string reading operations are performed before the programming of page M's data using ProgM ends.

[0227] Figure 25 The example illustrates how, by specifying the data address of the Lower page of page M, it can be determined that the address of the data written to page M is within the same block BLK as the address of the data of page N before the data of page M was written. In this case, when programming the data of page N using ProgN, even if all the data of the next page M is not cached, all string reading operations before the end of programming ProgN are omitted. Furthermore, the programming of the data of page M is performed according to instruction 15h after all the data of page N is cached. Since no data for the next page is reserved during programming ProgM, all string reading operations are performed before the end of programming ProgM.

[0228] Figure 26 and Figure 27 The example illustrates writing two pages of data programmed via cache programming to different block BLKs. That is, Figure 26 and Figure 27In this context, add(N) and add(M) have different block BLK addresses, and the data of page N and the data of page M are also written to different block BLKs.

[0229] According to Figure 26 and Figure 24 The comparison makes it clear, Figure 26 The timing of the write command or input page data N, M in the example is... Figure 24 same. Figure 26 In the example, the block address add(N) for writing data to page N is different from the block address add(M) for writing data to page M. In this case, as... Figure 26 As shown, all string reading operations are performed before the ProgN programming ends. Other operations are similar to... Figure 24 same.

[0230] In addition, as according to Figure 27 and Figure 25 The comparison makes it clear, Figure 27 The timing of the write command or input page data N, M in the example is... Figure 25 same. Figure 27 In the example, the block address add(N) for writing N pages of data is different from the block address add(M) for writing M pages of data. In this case, as... Figure 27 As shown, all string reading operations are performed before the ProgN programming ends. Other operations are similar to... Figure 25 same.

[0231] Thus, all string read operations are performed in blocks. Therefore, when writing within a single block, all string read operations only need to be performed once per block. Therefore, in cache programming, within the same block, all string read operations before the end of page data programming are omitted, and all string read operations are performed before the end of the final page data programming. This reduces the write time (tPROG).

[0232] (Second Implementation)

[0233] Figures 28 to 31 It concerns the second implementation method, and Figure 28 and Figure 31 This is a flowchart used to illustrate the second embodiment. Figure 29 and Figure 30 Through with Figures 23 to 27 The same method of description is used to illustrate the explanatory diagrams of the second embodiment. Figure 28 and Figure 31 In Chinese, the same symbol is used to mark the same sequence, and repeated explanations are omitted.

[0234] In the first embodiment, an example is described in which the control circuit 24 controls all string reading operations based on pre-registered string reading operation information in the non-volatile memory 2. In this embodiment, the non-volatile memory 2 can receive control-related instructions from the memory controller 3 for all string reading operations and perform control of all string reading operations.

[0235] Figure 28 In step S11, all string reading operations are set (parameter setting). This parameter setting is performed, for example, before the non-volatile memory 2 is shipped from the factory. For instance, at the time of factory shipment, the F_ASTRREAD_PROGEN_TLC parameter (hereinafter referred to as the all string reading operation execution parameter) may be set as a parameter to determine whether all string reading operations can be performed. When the all string reading operation execution parameter is "1", the control circuit 24 performs all string reading operations essentially based on the all string reading operation information; when it is "0", it essentially does not perform any string reading operations.

[0236] The user, having received the parameter settings for all string reading operations from the non-volatile memory 2, can output instructions from the memory controller 3 corresponding to the desired control related to all string reading operations.

[0237] For example, as instructions that can be supplied from memory controller 3, consider the all-string read skip instruction and the all-string read start instruction. The all-string read skip instruction is used to omit all string read operations, and the all-string read start instruction is used to execute all string read operations. For example, the common execution control instruction XXh can also be used as these all-string read skip instructions and all-string read start instructions.

[0238] For example, the memory controller 3 can give the non-volatile memory 2 the instruction sequence shown in (1) and (2) below. Furthermore, the meaning of these instruction sequences is the same as described above. Figures 23 to 27 Similarly, it specifies that the data of a certain Upper page will be programmed to a certain address. The instruction sequence of (2) is the instruction sequence of (1) with the execution control instruction XXh appended to it. That is to say, the memory controller 3 can control all string reading operations by appending the execution control instruction XXh to the instruction sequence required for programming.

[0239] 03h-80h-add-Din-10 / 15h……(1)

[0240] XXh-03h-80h-Add-Din-10 / 15h……(2)

[0241] Figure 29 and Figure 30An example is shown when the execution parameter for all string reading operations is "1". That is, in this case, control circuit 24 essentially performs all string reading operations. Control circuit 24 determines whether an execution control instruction XXh, which is a skip instruction for all string readings, has been input from memory controller 3 (S13). In the case of data input in (1), since no execution control instruction XXh was input, control circuit 24 performs all string reading operations in S17. Conversely, in the case of data input in (2), since the execution control instruction XXh, which is a skip instruction for all string readings, was input, control circuit 24 performs programming that omits all string reading operations in S18.

[0242] Figure 29 In the process, for the data of page N input during the period prior to programming ProgN, an execution control instruction XXh is appended as a skip instruction for all string readings. Therefore, control circuit 24 determines "yes" (YES) in S13 and omits all string reading operations at the end of programming ProgN (S18). Furthermore, for data input during the period prior to programming ProgN, an execution control instruction XXh is appended as a skip instruction for all string readings. Figure 29 The data input to page M during programming ProgN was not accompanied by the execution control instruction XXh, which is a skip instruction for all string readings. Therefore, control circuit 24 determines it to be NO in S13, thereby executing all string reading operations at the end of programming ProgN (S17).

[0243] Figure 30 In the process, for the N-page data input during the period prior to programming ProgN, no execution control instruction XXh, which serves as a skip instruction for all string readings, is attached. Therefore, control circuit 24 performs all string reading operations at the end of programming ProgN by determining no in S13 (S17). Furthermore, for the N-page data input during the period prior to programming ProgN, no execution control instruction XXh is attached as a skip instruction for all string readings. Figure 30 The M-page data input before the programming ProgM is appended as an execution control instruction XXh, which skips all string reading instructions. Therefore, the control circuit 24 omits all string reading actions at the end of programming ProgN by determining that it is true in S13 (S18).

[0244] Figure 31 This is an example where the execution parameter for all string reading actions is "0", and the control circuit 24 essentially omits all string reading actions. In this case, such as... Figure 31As shown, the instruction to start reading all strings is input as the execution control instruction XXh. If the execution control instruction XXh, which is the instruction to start reading all strings, is input (determined to be yes in S19), all string reading actions at the end of programming are executed (S17). Furthermore, if the execution control instruction XXh, which is the instruction to start reading all strings, is not input (determined to be no in S19), all string reading actions at the end of programming are omitted (S18).

[0245] Thus, in this embodiment, all string reading operations of the non-volatile memory 2 can be controlled by the execution control instruction XXh from the memory controller 3. For example, sometimes the memory controller 3 performs a verification read to confirm whether programming can be performed correctly after programming. In such cases, since the second read state can be maintained through the read after programming, it is preferable to omit all string reading operations. Furthermore, for example, there may be cases where the memory controller 3 outputs an instruction explicitly instructing all string reading operations. When using such an instruction, it is preferable to omit all string reading operations. In this embodiment, in such cases, all string reading operations can also be controlled by the memory controller 3.

[0246] (Third Implementation)

[0247] Figure 32 and Figure 33 This is a flowchart used to illustrate the third embodiment. Figure 32 and Figure 33 In, for the same order or with Figure 28 and Figure 31 The same symbols are used for items in the same order, and repeated descriptions are omitted. This embodiment combines the controls from the first and second embodiments. Furthermore, Figure 32 This example assumes that the execution parameter for all string reading actions is "1". The control circuit 24 basically executes all string reading actions. Figure 33 This is an example of being able to control all string reading actions regardless of the execution parameters of all string reading actions.

[0248] Figure 32 and Figure 33 In the example, before the non-volatile memory 2 is shipped from the factory, in S11, all string reading operations are set (parameter setting). In the third embodiment, in the parameter setting, all string reading operation information is written to block BLKX, and all string reading operation execution parameters are set as parameters to determine whether all string reading operations can be executed based on all string reading operation information, etc.

[0249] Figure 32In this example, the user receiving the non-volatile memory 2 controls the parameter settings for all string read operations and can output instructions from the memory controller 3 corresponding to the desired control for all string read operations. That is to say, Figure 32 In the example, memory controller 3 outputs a skip instruction for all string reads as the execution control instruction XXh.

[0250] Figure 32 In the example, all string reading actions are executed with the parameter "1", meaning that control circuit 24 essentially performs all string reading actions. Figure 32 In S13, it is determined whether to input the execution control instruction XXh, which is a skip instruction for reading all strings.

[0251] In the case of data input in (1), since no execution control instruction XXh was input (determined as NO in S13), the control circuit 24 determines in the following S14 whether programming is performed using a specific word line WL specified by the all-string read operation information, such as a word line WL with a smaller logic word line number. If programming is not performed using a specific word line WL (determined as NO in S14), the control circuit 24 determines in the following S15 whether programming has been reserved in cache programming. If programming is not reserved in cache programming (determined as NO in S15), the control circuit 24 performs all-string read operations (S17).

[0252] On the other hand, in the case of data input in (2), an execution control instruction XXh is added. Therefore, the control circuit 24 determines that it is true in S13, and omits all string reading operations at the end of programming (S18).

[0253] In addition, even if no execution control instruction XXh is input, if programming using a specific word line WL is used (determined to be yes in S14), and if it is a reserved program in cache programming, and the block BLK address of the program before writing the reserved program is the same as the block BLK address of the program written to the reserved program (determined to be yes in S16), all string reading operations are omitted (S18).

[0254] Figure 33In the example, in S12, control circuit 24 determines whether the execution parameter for all string reading actions is "1" (all string reading = ON (with all string reading)) (determined as yes in S12) or "0" (determined as no in S12). If the determination is yes in S12, control circuit 24 determines in S13 whether the execution control instruction XXh, which serves as a skip instruction for all string reading, has been input. If the determination is no in S12, control circuit 24 determines in S19 whether the execution control instruction XXh, which serves as a start instruction for all string reading, has been input. Other sequences are the same as... Figure 32 same.

[0255] Thus, in this embodiment, since the effects of the first and second embodiments can be achieved simultaneously, all string reading operations can be controlled through the memory controller 3 and the non-volatile memory 2.

[0256] This invention is not limited to the described embodiments, and various changes can be made during the implementation phase without departing from its spirit. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted through appropriate combinations of the disclosed constituent elements. For example, if the problem described in the "Problem to be Solved by the Invention" section can be solved and the effects described in the "Effects of the Invention" section can be obtained even if several constituent elements are deleted from all the constituent elements shown in the embodiments, then the structure with the deleted constituent elements can also be extracted as an invention.

[0257] [Additional Notes]

[0258] [Note 1]

[0259] A semiconductor memory device includes: a plurality of memory strings, each comprising a plurality of memory cell transistors connected in series and connected in parallel with each other;

[0260] Multiple word lines are connected to the gates of the respective memory cell transistors;

[0261] A block comprising the plurality of memory strings commonly connected by the plurality of word lines; and

[0262] Control circuit; and

[0263] The plurality of character lines includes a first character line and a second character line that is different from the first character line.

[0264] The plurality of memory cell transistors include: a first memory cell transistor connected to the first word line, and a second memory cell transistor connected to the second word line;

[0265] The control circuit controls the following actions: a first write operation performed on the first memory cell transistor; and a second write operation performed on the second memory cell transistor, following the first write operation.

[0266] During the specific period before the first write operation ends and a command is input, the ready / busy signal remains in the ready state.

[0267] During a specific period before the second write operation ends and an instruction is input, the ready / busy signal changes from the ready state to the busy state.

[0268] [Note 2]

[0269] A semiconductor memory device includes: a plurality of memory strings, each comprising a plurality of memory cell transistors connected in series and connected in parallel with each other;

[0270] Multiple word lines are connected to the gates of the respective memory cell transistors;

[0271] A block comprising the plurality of memory strings commonly connected by the plurality of word lines; and

[0272] Control circuit; and

[0273] The plurality of character lines includes a first character line and a second character line that is different from the first character line.

[0274] The plurality of memory cell transistors include: a first memory cell transistor connected to the first word line, and a second memory cell transistor connected to the second word line;

[0275] The control circuit controls the following actions: a first write operation performed on the first memory cell transistor; and a second write operation performed on the second memory cell transistor, following the first write operation.

[0276] The first and second write operations consist of multiple loops containing at least programming operations.

[0277] The programming action is performed in the final loop of the first write operation, without performing the first voltage application action that applies a specific voltage to the first and second word lines.

[0278] The final loop within the second write operation performs the programming operation and the first voltage application operation.

[0279] [Note 3]

[0280] According to the semiconductor memory device described in Appendix 2, wherein after the first write operation is completed, during a specific period when no instruction is input, the control circuit applies a ground voltage to the first and second word lines, or sets the first and second word lines to a floating state.

[0281] After the second write operation is completed, during the specific period, a ground voltage is applied to the first and second word lines, or after the first and second word lines are set to a floating state, a second voltage application operation is performed to apply a specific voltage to the first and second word lines.

[0282] [Note 4]

[0283] According to the semiconductor memory device described in Appendix 3, the second voltage application action is performed multiple times during the specific period.

[0284] [Note 5]

[0285] The semiconductor memory device according to Appendix 17 further comprises: a plurality of bit lines respectively connected to the plurality of memory strings; and

[0286] The first transistor is connected to one of the plurality of bit lines; and

[0287] The first and second write operations consist of multiple loops containing at least programming operations.

[0288] In the final loop of the first write operation, a first voltage is applied to the gate of the first transistor.

[0289] In the cycle preceding the last cycle within the second write operation, a first voltage is applied to the gate of the first transistor. After applying the first voltage, a second voltage lower than the first voltage is applied.

[0290] In the final loop of the second write operation, the first voltage is applied to the gate of the first transistor, and after applying the first voltage, a third voltage lower than the first voltage is applied.

[0291] The time for applying the second voltage is longer than the time for applying the third voltage.

[0292] [Note 6]

[0293] According to the semiconductor memory device described in Appendix 5, the third voltage is equal to or less than the second voltage.

[0294] [Symbol Explanation]

[0295] 1 Memory System

[0296] 2 Non-volatile memory

[0297] 3 Memory Controller

[0298] 4 main unit

[0299] 10 Host I / F Circuits

[0300] 11 processor

[0301] 12 RAM

[0302] 13 Buffer Memory

[0303] 14 Memory I / F Circuits

[0304] 15ECC circuit

[0305] 20 memory cell array

[0306] 21 Input / Output Circuit

[0307] 22 Logic Control Circuits

[0308] Register 23

[0309] 24 control circuits

[0310] 25 Voltage Generation Circuit

[0311] 25A cabling group

[0312] 26-line decoder

[0313] 27-column decoder

[0314] 28-unit sensor amplifier group

[0315] 29 Data Register

[0316] BL bit line

[0317] BLK block

[0318] CG signal line

[0319] CU unit group

[0320] MT memory cell transistor

[0321] NSNAND string

[0322] SGD, SGS Select Gate Line

[0323] ST1, ST2 select gate transistors

[0324] SU string unit.

Claims

1. A semiconductor memory device comprising: Multiple memory strings, each containing multiple memory cell transistors connected in series, are connected in parallel to each other; Multiple word lines are connected to the gates of the respective memory cell transistors; A block comprising the plurality of memory strings commonly connected by the plurality of word lines; and The control circuit controls the write operations for at least a portion of the plurality of memory cell transistors; and The semiconductor memory device receives a write command and an address, and performs data writing; The write operation is performed based on the received write command and address. If the address corresponds to a specific object word line, the control circuit applies a first voltage before the write operation ends. If the address does not correspond to a specific object word line, the control circuit will not apply the first voltage before the write operation ends. The first voltage application action applies a specific voltage to the plurality of word lines.

2. The semiconductor memory device of claim 1, wherein the address includes a page address. The control circuit determines whether to apply the first voltage before the write operation ends based on the page address.

3. The semiconductor memory device of claim 1, wherein the address includes a word line address. The control circuit determines whether to apply the first voltage before the write operation ends based on the word line address.

4. The semiconductor memory device of claim 1, wherein the value of the particular voltage is higher than the highest readout voltage.

5. The semiconductor memory device of claim 1, wherein the value of the specific voltage is substantially equal to the voltage at which the memory cell transistor is turned on during a read operation of the memory cell transistor.

6. The semiconductor memory device according to claim 1, further comprising: Bit lines, connected to one of the plurality of memory strings; and The sensing amplifier is connected to the bit line via the first transistor; and During the first voltage application operation, an off voltage is applied to the first transistor.

7. The semiconductor memory device according to claim 1, further comprising: Bit lines are connected to one of the plurality of memory strings; A sensing amplifier is connected to the bit line via a first transistor; A second transistor, included within the sensing amplifier, is connected on one side to the first transistor and on the other side to the first power supply voltage; and The third transistor, included within the sensing amplifier, is connected on one side to the first and second transistors, and on the other side to a second power supply voltage lower than the first power supply voltage; and During the first voltage application operation, an on-voltage is applied to the first transistor, an off-voltage is applied to the second transistor, and an on-voltage is applied to the third transistor.

8. The semiconductor memory device of claim 1, wherein during the write operation, at least a portion of a write instruction and an address for the next write operation is received. The address includes block addresses. If the block address of the write operation is consistent with the block address of the next write operation, the control circuit omits the first voltage application operation before the write operation ends.

9. The semiconductor memory device of claim 1, wherein during the write operation, at least a portion of a write instruction and an address for the next write operation is received. The address includes block addresses. If the block address of the write operation is inconsistent with the block address of the next write operation, the control circuit performs a first voltage application operation before the write operation ends.

10. The semiconductor memory device of claim 1, wherein the specific object word line corresponds to a logic word line having a logic word line number, the logic word line number being greater than the corresponding logic word line number of the logic word line of the specific non-object word line in the block.

11. A semiconductor memory device comprising: Multiple memory strings, each containing multiple memory cell transistors connected in series, are connected in parallel to each other; Multiple word lines are connected to the gates of the respective memory cell transistors; A block comprising the plurality of memory strings commonly connected by the plurality of word lines; and Control circuit; and The plurality of character lines includes a first character line and a second character line that is different from the first character line. The plurality of memory cell transistors include: a first memory cell transistor connected to the first word line, and a second memory cell transistor connected to the second word line; The control circuit controls the following actions: a first write operation to the first memory cell transistor, and a second write operation to the second memory cell transistor, performed after the first write operation. The first and second write operations consist of multiple loops containing at least programming operations. The programming action is performed in the final loop within the first write action, without performing the verification action or the first voltage application action that applies a specific voltage to the first and second word lines. The final loop within the second write operation performs the programming action and the first voltage application action, but does not perform a verification action. During a first specific period following the first write operation without any input instruction, the control circuit applies a ground voltage to the first and second word lines, or sets the first and second word lines to a floating state. During a second specific period following the second write operation without inputting a command, the control circuit applies a ground voltage to the first and second word lines, or sets the first and second word lines to a floating state, and then performs a second voltage application operation to apply a specific voltage to the first and second word lines. The period of the first specific period is the same as the period of the second specific period.

12. The semiconductor memory device of claim 11, wherein the programming and verification operations are performed in a loop from the last to the first in the second write operation. The time required for the first voltage application action is shorter than the time required for the verification action.

13. The semiconductor memory device of claim 11, wherein the second voltage application action is performed multiple times during the second specific period.

14. The semiconductor memory device of claim 11, wherein the control circuit performs the first voltage application operation before the end of a series of write operations when the plurality of memory cell transistors are continuously written to.

15. A semiconductor memory device comprising: Multiple memory strings, each containing multiple memory cell transistors connected in series, are connected in parallel to each other; Multiple word lines are connected to the gates of the respective memory cell transistors; A block comprising the plurality of memory strings commonly connected by the plurality of word lines; and The control circuit controls the write operations for at least a portion of the plurality of memory cell transistors; and The semiconductor memory device receives control commands related to the application of the first voltage, write commands, and address, and performs data writing; The write operation is performed based on the received write command and address. The control circuit determines, based on the control command, whether to apply the first voltage before the write operation ends. The first voltage application action applies a specific voltage to the plurality of word lines. When the control circuit receives the control command, it omits the first voltage application action that was performed before the writing action ended.

16. The semiconductor memory device of claim 15, wherein the control circuit determines whether to perform a first voltage application operation based on the address when the control command is not received.

17. The semiconductor memory device of claim 15, wherein the control circuit omits the first voltage application operation performed before the end of the write operation if it does not receive the control command.

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