Semiconductor memory device and data erasing method

Abstract

Embodiments of the present application relate to a semiconductor memory device and a data erasing method. A semiconductor memory device of an embodiment includes a plurality of strings including, in order, a first selection transistor, a plurality of memory cell transistors, and a second selection transistor, a plurality of word lines respectively connected to the memory cell transistors of the same row of the plurality of strings, a bit line commonly connected to end portions of the plurality of strings, a source line commonly connected to other end portions of the plurality of strings, and a control circuit that performs an erasing operation of the plurality of memory cell transistors, and the control circuit, in the erasing operation, implements at least one of a first process of changing an application time of a first voltage applied to a gate of the first selection transistor and a second process of changing the first voltage applied to the gate of the first selection transistor for each of the plurality of strings.

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-153539 filed on September 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor storage device and a data erasure method. Background Technology

[0004] In recent years, due to the requirements of miniaturization and large capacity, three-dimensional structures have been gradually realized in semiconductor memory devices such as NAND (Not AND) memory. Furthermore, regarding this type of NAND memory, there are not only SLC (Single Level Cell) where the memory cell transistors are configured to store 1 bit (2 values) of data, but also MLC (Multi Level Cell) where the memory cell transistors are configured to store 2 bits (4 values) of data, TLC (Triple Level Cell) where the memory cell transistors are configured to store 3 bits (8 values) of data, or QLC (Quad Level Cell) where the memory cell transistors are configured to store 4 bits (16 values) of data.

[0005] Data erasure in this type of NAND memory is performed on a block-by-block basis. To homogenize the characteristics of NAND memory, improvements in erasure characteristics are required. Summary of the Invention

[0006] This embodiment provides a semiconductor storage device and a data erasure method that can improve erasure characteristics.

[0007] The semiconductor memory device of the embodiment includes: a plurality of strings, sequentially including a first selection transistor, a plurality of memory cell transistors, and a second selection transistor; a plurality of word lines, respectively connected to the memory cell transistors in the same row of the plurality of strings; bit lines, commonly connected to one end of the plurality of strings; source lines, commonly connected to the other end of the plurality of strings; and a control circuit for performing an erase operation on the plurality of memory cell transistors; wherein, during the erase operation, the control circuit performs at least one of the following processes for each of the plurality of strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor.

[0008] Based on the aforementioned configuration, a semiconductor storage device and a data erasure method that can improve erasure characteristics can be provided. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example configuration of a memory system in an implementation method.

[0010] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment.

[0011] Figure 3 This is a diagram showing the equivalent circuit of the block BLK of the NAND-type memory cell array 23 in the three-dimensional structure of the non-volatile memory 2 in this embodiment.

[0012] Figure 4 It is a cross-sectional view of a local area of ​​a three-dimensional NAND memory cell array.

[0013] Figure 5 This is an explanatory diagram illustrating the configuration of each NAND string in a block BLK.

[0014] Figure 6 It means Figure 2 A block diagram of an example of the sensing amplifier 24.

[0015] Figure 7 It means Figure 2 A block diagram of an example of the configuration of the line decoder 25.

[0016] Figure 8 It is a graph that shows the threshold distribution of a memory cell array by recording the threshold voltage on the horizontal axis and the number of transistors (cells) on the vertical axis.

[0017] Figure 9 This indicates that the memory cell array 23 is composed of Figure 5 The circuit diagram is composed of the circuits of each string.

[0018] Figure 10 This is an explanatory diagram used to illustrate the depth of the erase level and the method for determining it.

[0019] Figure 11 This is an explanatory diagram used to illustrate the depth of the erase level and the method for determining it.

[0020] Figure 12 This is a flowchart illustrating the erasure operation of the first embodiment.

[0021] Figure 13 It means Figure 12 A flowchart of an example of the steps for feature testing.

[0022] Figure 14 This is a waveform diagram showing the waveforms of each part during the erasure process in the first embodiment.

[0023] Figure 15 This is a circuit diagram illustrating the second embodiment.

[0024] Figure 16 This is a waveform diagram showing the waveforms of each part during the erasure process in the second embodiment.

[0025] Figure 17 This is a waveform diagram representing the third embodiment.

[0026] Figure 18 This is a waveform diagram representing the fourth embodiment. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0028] (First Embodiment) This embodiment improves the erasure characteristics by adjusting the application period of the erasure voltage required for erasing each string of transistors including a plurality of memory cells.

[0029] (The structure of a memory system) Figure 1 This is a block diagram illustrating an example configuration of a memory system according to an embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a mobile terminal.

[0030] The non-volatile memory 2 is a semiconductor storage device that stores data non-volatilely, such as a NAND flash memory. In this embodiment, it will be described as a NAND flash memory having a storage cell transistor capable of storing 3 bits per transistor, i.e., a 3-bit / cell (TLC) NAND flash memory, but it is not limited to this. The non-volatile memory 2 is three-dimensional.

[0031] The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0032] The host interface 13 outputs requests received from the host, write data, etc., to the internal bus 16. The host interface 13 also sends data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0033] The memory interface 15 controls the processes of writing data to and reading data from the non-volatile memory 2 based on the instructions of the processor 12.

[0034] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When processor 12 receives a request from the host via host interface 13, it performs control according to that request. For example, processor 12, based on a request from the host, instructs memory interface 15 to write data and perform parity checks to non-volatile memory 2. Additionally, processor 12, based on a request from the host, instructs memory interface 15 to read data and perform parity checks from non-volatile memory 2.

[0035] Processor 12 determines the storage area (hereinafter referred to as memory area) on non-volatile memory 2 for the data stored in RAM 11. Data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory area for data in page units, i.e., page data, where a page is the write unit. In this specification, data stored in one page of non-volatile memory 2 is defined as cell data. Cell data is encoded and stored as codewords in non-volatile memory 2, for example.

[0036] Furthermore, encoding is not mandatory. Memory controller 1 can also store cell data in non-volatile memory 2 without encoding, but... Figure 1 The following is an example of an encoding configuration. When the memory controller 1 does not perform encoding, the page data and the cell data are identical. Alternatively, a codeword can be generated based on a single cell data unit, or it can be generated based on the segmented data resulting from dividing the cell data. Furthermore, multiple cell data units can also be used to generate a single codeword.

[0037] Processor 12 determines the memory region of non-volatile memory 2 to be written to for each unit of data. A physical address is allocated to the memory region of non-volatile memory 2. Processor 12 manages the memory region to be written to for each unit of data using the physical address. Processor 12 specifies the physical address of the determined memory region and instructs memory interface 15 to write the data to non-volatile memory 2. Processor 12 manages the mapping between the logical address (the logical address managed by the host) and the physical address of the data. When processor 12 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 15 to read the data.

[0038] The ECC circuit 14 encodes the data stored in RAM 11 to generate codewords. Additionally, the ECC circuit 14 decodes the codewords read from the non-volatile memory 2. RAM 11 temporarily stores the data received from the host before storing it in the non-volatile memory 2, or temporarily stores the data read from the non-volatile memory 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0039] Figure 1 The diagram shows an example configuration of the memory controller 1, which includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. The ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0040] When a write request is received from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it into the ECC circuit 14. The ECC circuit 14 encodes the input data and assigns the codeword to the memory interface 15. The memory interface 15 writes the input codeword into the non-volatile memory 2.

[0041] When a read request is received from the host, the memory controller 1 operates as follows: The memory interface 15 assigns the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0042] (A rough outline of non-volatile memory) Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment.

[0043] The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, a register 26, a sequencer 27, a voltage generation circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0044] The input / output pad group 32 has multiple terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS in order to transmit and receive signals containing data between the input and output pad group 32 and the memory controller 1.

[0045] The logic control pad group 34, for transmitting and receiving various signals with the memory controller 1, has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protection signal / WP, and signal R / B. Furthermore, the " / " appended to the signal names indicates that it is active low.

[0046] The / CE signal is used to select and enable a specific memory chip when the non-volatile memory 2 contains multiple memory chips. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The / WE signal enables writing. The RE and / RE signals enable reading. The / WP signal disables writing and erasing. The R / B signal indicates whether the non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). The memory controller 1 can determine the status of the non-volatile memory 2 by receiving the R / B signal.

[0047] The power input terminal group 35 has multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss to supply various operating power sources to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage generally supplied externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0048] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0049] The logic control circuit 21 receives external control signals (e.g., chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP) from the memory controller 1 via the NAND bus. Additionally, the logic control circuit 21 sends a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0050] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the non-volatile memory 2. Register 26 may include, for example, SRAM.

[0051] The sequencer 27, which serves as the control circuit, has a register (not shown). The sequencer 27 receives instructions from the register 26 and controls the non-volatile memory 2 according to the sequence of those instructions.

[0052] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write operations, read operations, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0053] The row decoder 25 receives the row address from register 26 and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Furthermore, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0054] The sense amplifier 24 receives the column address from the register 26 and decodes the column address. The sense amplifier 24 has a sense amplifier component group 24A connected to each bit line, which selects any bit line based on the decoded column address. Furthermore, during data readout, the sense amplifier component group 24A senses and amplifies the data read from the memory cell transistor to the bit line. Additionally, during data writeout, the sense amplifier component group 24A writes the data to the bit line.

[0055] The sensing amplifier 24 has a data register 24B. When data is read out, the data register 24B temporarily stores the data detected by the sensing amplifier assembly 24A and serially transmits this data to the input / output circuit 22. Conversely, when data is written, the data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits this data to the sensing amplifier assembly 24A. The data register 24B may include SRAM or the like.

[0056] The memory cell array 23 has multiple blocks of transistors (BLKs). Each block of transistors has multiple memory cell transistors (memory cells). Multiple bit lines, multiple word lines, and source lines are arranged in the memory cell array 23 to control the voltage applied to the memory cell transistors.

[0057] (Block structure of a memory cell array) Figure 3 This is a diagram showing the equivalent circuit of the block BLK of the NAND-type memory cell array 23 in the three-dimensional structure of the non-volatile memory 2 in this embodiment. Figure 3 The image shows one block BLK, one of the multiple blocks constituting the memory cell array 23. The other blocks in the memory cell array also have the same characteristics. Figure 3 The same configuration applies. Furthermore, this implementation can also be applied to two-dimensional memory cell arrays.

[0058] As shown in the figure, the block BLK contains, for example, five string components (SU0 to SU4). Furthermore, the number of strings can be freely varied depending on the capacity and chip size. In describing this patent, five string components will be used as an example. Each string component SU contains multiple NAND strings NS. Here, each NAND string NS contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. Furthermore, the number of memory cell transistors MT in the NAND string NS is set to eight, but it can be more. Select gate transistors ST1 and ST2 are represented as one transistor in the circuit, but structurally they can be the same as the memory cell transistors. Additionally, multiple select gate transistors can be used for each of ST1 and ST2. Furthermore, dummy cell transistors can be provided between the memory cell transistors MT and the select gate transistors ST1 and ST2.

[0059] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end (bit line side) is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end (source line side) is connected to the select gate transistor ST2.

[0060] The gates of the select gate transistors ST1 of each string assembly SU0 to SU4 are respectively connected to select gate lines SGD0 to SGD4 (hereinafter referred to as select gate lines SGD). On the other hand, the gates of select gate transistors ST2 are connected to the same select gate line SGS among the multiple string assemblies SU located in the same block BLK.

[0061] The gates of memory cell transistors MT0 to MT7 located within the same block BLK are all connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 are commonly connected among multiple string components SU0 to SU4 within the same block BLK. Conversely, even within the same block BLK, the select gate line SGD is independent for each of the string components SU0 to SU4. The gates of memory cell transistors MTi located in the same row within the block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS is sometimes simply referred to as "string".

[0062] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST1, ST2, or other memory cell transistor MTs contained within the NAND string NS. Data on memory cell transistors MTs located within the same block BLK is erased all at once. Conversely, data is read and written simultaneously to multiple memory cell transistors MTs that share a single word line WL configured in one string assembly SU. Such a group of memory cell transistors MTs sharing a word line WL within one string assembly SU is called a memory cell group MG.

[0063] Write and read operations for memory cell group MG are performed on a page-by-page basis. For example, in the case of a TLC where each cell can store 3 bits (8 values) of data, one memory cell group MG can store 3 pages of data. The 3 bits that each memory cell transistor MT can store correspond to these 3 pages.

[0064] (Three-dimensional structure of a memory cell array) Figure 4 This is a cross-sectional view of a partial area of ​​a three-dimensional NAND flash memory array. (Example) Figure 4 As shown, multiple NAND strings NS are formed in the D1 direction on the p-well region. That is, multiple wiring layers 333 that function as select gate line SGS, multiple wiring layers 332 that function as word line WLi, and multiple wiring layers 331 that function as select gate line SGD are stacked on the p-well region.

[0065] Furthermore, a memory via 334 is formed, penetrating these wiring layers 333, 332, and 331 and reaching the p-type well region. A barrier insulating film 335, a charge storage film (charge storage region) 336, and a gate insulating film 337 are sequentially formed on the side of the memory via 334. A semiconductor pillar 338 is also embedded within the memory via 334. The semiconductor pillar 338, for example, comprises polysilicon and functions as a channel forming region when the memory cell transistor MT and the select gate transistors ST1 and ST2 contained in the NAND string NS are operated. That is, wiring layer 331, semiconductor pillar 338, and the films 335-337 between them function as select gate transistor ST1, wiring layer 332, semiconductor pillar 338, and the films 335-337 between them function as memory cell transistor MT, and wiring layer 333, each semiconductor pillar 338, and the films 335-337 between them function as select gate transistor ST2.

[0066] also, Figure 4 In this design, the memory hole 334 and the semiconductor pillar 338 are represented as cylindrical shapes with the same diameter, but in reality, they have a tapered shape in which the diameter tapers towards the p-type well region. Alternatively, depending on the manufacturing process, the memory hole 334 and the semiconductor pillar 338 may have a multi-stage tapered shape, where the diameter expands midway through the tapered shape and then tapers again towards the p-type well region.

[0067] In each NAND string NS, a select gate transistor ST2, multiple memory cell transistors MT, and a select gate transistor ST1 are sequentially formed on the p-type well region. A wiring layer, functioning as a bit line BL, is formed on the upper side (D3 direction) relative to the semiconductor pillar 338. A contact plug 339 connecting the semiconductor pillar 338 and the bit line BL is formed at the upper end of the semiconductor pillar 338.

[0068] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed on the surface of the p-type well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer that functions as a source line SELSRC is formed on the contact plug 340.

[0069] The above Figure 4 The configuration shown is in Figure 4 Multiple NAND strings are arranged in the depth direction (D2 direction) of the paper, and a string component SU is formed by a collection of multiple NAND strings arranged in a row in the depth direction.

[0070] (String structure) Figure 5 This is an explanatory diagram illustrating the configuration of each NAND string in a block BLK. Figure 5 The circular marker indicates the memory hole 334 that makes up the NAND string. The insulating layer ST will... Figure 5 The block shown is separated from the other blocks. Figure 5 The example shows a configuration within a single block BLK comprising five string components SU0 to SU4 separated by an insulating layer SHE. The insulating layer SHE extends to the wiring layer 331 constituting the select gate line SGD, thereby separating each string component SU0 to SU4 from the others.

[0071] Will Figure 5 The NAND strings contained in string component SU0 are called string String0, the NAND strings contained in string component SU1 are called string String1, the NAND strings contained in string component SU2 are called string String2, the NAND strings contained in string component SU3 are called string String3, and the NAND strings contained in string component SU4 are called string String4. Furthermore, strings String0 through 4 are referred to as string String.

[0072] A string assembly SU is configured with multiple memory holes 334 that constitute NAND strings. Each memory hole 334 in a string assembly is connected to bit lines BL0, BL1, ... via contact plugs 340. Each bit line BL0, BL1, ... is connected to five strings String0 to String4. Each string assembly SU has m NAND strings corresponding to bit lines BL0 to BL(m-1).

[0073] (Sensing amplifier) Figure 6 It means Figure 2 A block diagram of an example of the sensing amplifier 24.

[0074] The sense amplifier 24 includes a sense amplifier assembly group 24A and a data register 24B. The sense amplifier assembly group 24A includes sense amplifier assemblies SAU0 to SAU(m-1) corresponding to bit lines BL0 to BL(m-1) (hereinafter, representatively referred to as sense amplifier assemblies SAU). Each sense amplifier assembly SAU includes a sense amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier section SA and the data latch circuits SDL, ADL, BDL, and CDL are connected in a manner that enables data transmission between them.

[0075] The data latch circuits SDL, ADL, BDL, and CDL temporarily store data. During a write operation, the sense amplifier section SA controls the voltage of the bit line BL based on the data stored in the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations where the memory cell transistor MT stores more than 2 bits of data. For example, if the pages corresponding to each bit of 3 bits of data are designated as the lower page, middle page, and upper page, then the data latch circuit ADL is used to store the lower page, the data latch circuit BDL is used to store the middle page, and the data latch circuit CDL is used to store the upper page. The number of data latch circuits in the sense amplifier assembly SAU can be arbitrarily changed according to the number of bits stored by one memory cell transistor MT.

[0076] During the read operation, the sensing amplifier section SA senses the data that has been read onto the corresponding bit line BL and determines whether the data is "0" or "1". Conversely, during the write operation, the sensing amplifier section SA applies a voltage to the bit line BL based on the data to be written.

[0077] Data register 24B includes data latch circuits XDL, the number of which corresponds to the number of sense amplifier components SAU0 to SAU(m-1). The data latch circuits XDL are connected to input / output circuit 21. The data latch circuits XDL are used for data transmission between the sense amplifier 24 and external devices, temporarily storing write data sent from input / output circuit 21 and read data sent from sense amplifier components SAU. More specifically, data transmission between input / output circuit 22 and sense amplifier components SAU0 to SAU(m-1) is performed via the data latch circuits XDL (one page portion). Write data received by input / output circuit 21 is transmitted via the data latch circuits XDL to any one of the data latch circuits ADL, BDL, and CDL. Read data read by sense amplifier section SA is transmitted to input / output circuit 21 via the data latch circuits XDL.

[0078] (Line decoder) Figure 7 It means Figure 2 A block diagram of an example of the configuration of the line decoder 25.

[0079] The voltage generation circuit 28 includes multiple SG drivers (select gate line drivers) 28A that supply voltage to signal lines SGa to SGe respectively, and multiple CG drivers (word line drivers) 28B that supply voltage to signal lines CG0 to CG7 respectively. These signal lines SGa to SGe and CG0 to CG7 are branched by the line decoder 25 and connected to the wiring of each BLK. That is, signal lines SGa to SGd function as global drain-side select gate lines and are connected via the line decoder 25 to the select gate lines SGDa to SGDd (represented by select gate line SGD) in each BLK as local select gate lines. Furthermore, as described above, the select gate transistor ST1 can also be constructed from multiple select gate transistors. Figure 7 The example illustrates the following example, in which the select gate transistor ST1 includes four select gate transistors, and a gate voltage is applied to the gate of the four select gate transistors through select gate lines SGDa to SGDd.

[0080] Signal lines CG0 to CG7 function as global word lines and are connected via the row decoder 25 to the word lines WL0 to WL7, which are local word lines, in each BLK block. Signal line SGe functions as a global source-side select gate line and is connected via the row decoder 25 to the select gate line SGS, which is a local select gate line, in each BLK block.

[0081] The voltage generation circuit 28, controlled by the sequencer 27, generates various voltages. SG drivers 28A and CG drivers 28B supply the generated voltages to the corresponding signal lines SGa to SGe and signal lines CG0 to CG7, respectively. Each SG driver 28A generates a gate voltage supplied to the select gate lines SGD and SGS. The gate voltage generated by the SG driver 28A is supplied to the gates of the select gate transistors ST1 and ST2. Additionally, each CG driver 28B selects and supplies voltages such as VCGRV, VREAD, and VCG_ER to the corresponding word line WL according to the operation object (row address) in the read operation.

[0082] The line decoder 25 has multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B respectively configured corresponding to the multiple switch circuit groups 25A. Each switch circuit group 25A includes multiple transistors TR_SGa to TR_SGd that connect signal lines SGa to SGd to select gate lines SGDa to SGDd3 respectively, multiple transistors TR_CG0 to TR_CG7 that connect signal lines CG0 to CG7 to word lines WL0 to WL7 respectively, and a transistor TR_SGe that connects signal line SGe to select gate line SGS. Transistors TR_SGa to TR_SGe and transistors TR_CG0 to TR_CG7 are high-voltage transistors.

[0083] When each block decoder 25B is specified by the row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SGa to TR_SGe and transistors TR_CG0 to TR_CG7. As a result, in the switching circuit group 25A that supplies the block selection signal BLKSEL from the block decoder 25B specified by the row address, transistors TR_SGa to TR_SGe and transistors TR_CG0 to TR_CG7 are turned on and conducted. Therefore, the voltage supplied from the power generation circuit 28 to the signal lines SGa to SGe and signal lines CG0 to CG7 is supplied to the selection gate lines SGDa to SGDd, SGS, and word lines WL0 to WL7 contained in the block BLK to be operated.

[0084] (Threshold Distribution) When writing multi-valued data to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to the value corresponding to the data value. If a programming voltage VPGM and a bit line voltage VBL are applied to the memory cell transistor MT, electrons are injected into the charge storage film 336, and the threshold voltage rises. The threshold voltage of the memory cell transistor MT can be increased by increasing the programming voltage VPGM, thereby increasing the amount of electron injection. However, due to the variations in the memory cell transistor MT, even when the same programming voltage VPGM is applied, the amount of electron injection is different for each memory cell transistor MT. The temporarily injected electrons are retained until the erase operation is performed. Therefore, the programming voltage VPGM is gradually increased, and programming and verification operations are performed multiple times (loop) to avoid exceeding the range of threshold voltages that can be allowed as the threshold voltage set for each memory cell transistor MT (hereinafter referred to as the target area).

[0085] Furthermore, after the programming operation, a verification operation is performed. This verification operation involves reading data to determine whether the threshold voltage of the memory cell transistor has reached the target region. By repeating the above combination of programming and verification operations, the threshold voltage of the memory cell transistor is raised to the target region. Memory cell transistors that are determined by the verification operation to have reached the target region's threshold voltage, i.e., exceeding the target level's minimum value, are then disabled from writing.

[0086] Figure 8 It is a graph that shows the threshold distribution of a memory cell array by recording the threshold voltage on the horizontal axis and the number of transistors (cells) on the vertical axis. Figure 8The diagram illustrates an example of the threshold distribution for a 3-bit / cell non-volatile memory 2. In the non-volatile memory 2, the threshold voltage of the memory cell transistor MT is set based on the individual data values ​​of the multi-valued data stored in the memory cell transistor MT. Since the injection of charge into the charge storage film (charge storage region) 336 is probabilistic, therefore, as... Figure 8 As shown, the threshold voltages of the transistors MT in each memory cell are also statistically distributed.

[0087] Figure 8 The threshold distribution is illustrated using eight mountain-shaped regions: DEr, DA, DB, DC, ..., DG. The range of threshold voltage in each region corresponds to the target region. Figure 8 In the example, by setting the threshold voltage of the memory cell transistor MT in any of the eight target regions, the memory cell transistor MT can store eight values ​​of data (3 bits of data).

[0088] In this embodiment, the threshold voltage Vth is become Figure 8 The target region below the threshold voltage VrA is called the erase level (Er level). The target region with a threshold voltage greater than VrA but below VrB is called the A level; the target region with a threshold voltage greater than VrB but below VrC is called the B level; and the target region with a threshold voltage greater than VrC but below VrD is called the C level. Similarly, as follows... Figure 8 As shown, the D level to the G level are set according to the various voltages.

[0089] In other words, the level indicates which target region corresponds to the data value stored in the transistor MT of each memory cell. In the case of 3 bits and 8 values, the target region is divided into 8 levels: Er, A to G. Furthermore, the threshold distributions corresponding to each Er, A, B, ..., F, G level are respectively called distributions DEr, DA, DB, ..., DF, DG. Voltages VrA to VrG are reference voltages that form the boundaries of each target region. Additionally, during verification, voltages VrA to VrG can be applied as verification levels (voltages) to the word line WL and read out. The threshold voltage corresponding to the level is determined by whether the target memory cell transistor MT is turned off.

[0090] (Readout Operation) Reading data from the multi-valued memory cell transistors is performed through the following steps: the line decoder 25 applies a readout voltage to the word line (hereinafter referred to as the select word line) WL of the memory cell transistor MT to which the readout target is located, and the sense amplifier 24 senses the data that has been read out to the bit line BL, determining whether the readout data is "0" or "1". Furthermore, to turn on the memory cell transistors connected to word lines other than the select word line (hereinafter referred to as the non-select word line) WL, the line decoder 25 applies a sufficiently high voltage VREAD to the non-select word line WL to turn on each memory cell transistor.

[0091] During the readout operation, the sensing amplifier 24 fixes the bit line BL to a fixed voltage (e.g., 0.5V) and charges the sensing node SEN (not shown) inside the sensing amplifier section SA to a predetermined precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the sensing amplifier 24 electrically connects the sensing node SEN to the bit line BL. As a result, current flows from the sensing node SEN to the bit line BL, and the voltage of the sensing node SEN gradually decreases.

[0092] The voltage at the sensing node SEN varies depending on the threshold voltage of the memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage of the memory cell transistor is lower than the read voltage, the transistor is on, a larger cell current flows to it, and the voltage at the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage of the memory cell transistor is higher than the read voltage, it is off, a smaller cell current flows to it, or no current flows at all, and the voltage at the sensing node SEN decreases more slowly.

[0093] The write state of the memory cell transistor is determined by utilizing the difference in the rate at which the voltage of the sensing node SEN decreases, and the result is stored in the data latch circuit. For example, at the first time point after a predetermined first period has elapsed from the start of discharge that causes the charge of the sensing node SEN to begin discharging, it is determined whether the voltage of the sensing node SEN is low (hereinafter, "L") or high (hereinafter, "H"). For example, when the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is fully turned on, and a large cell current flows to the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases rapidly, and the voltage drop is relatively large; at the first time point, the sensing node SEN becomes "L".

[0094] Furthermore, when the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, and the cell current flowing to the memory cell transistor is very small or no cell current flows to the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At time point 1, the sensing node SEN remains "H".

[0095] In this way, while applying a readout voltage to the select word line via the line decoder 25, the state of the sensing node SEN is monitored by the sensing amplifier 24 to determine whether the threshold voltage of the memory cell transistor is higher or lower than the readout voltage. Therefore, by applying the voltage between each level as the readout voltage to the select word line WL, the level of each memory cell transistor can be determined, and the data assigned to each level can be read out.

[0096] (The topic of erasure) Figure 9 This indicates that the memory cell array 23 is composed of Figure 5 The circuit diagram formed by the circuits of each string. For example... Figure 9 As shown, each string String0 to String4 is constructed by connecting the select gate transistor ST1, multiple memory cell transistors MT, and the select gate transistor ST2 in series between the bit line BL and the source line CELSRC. Furthermore, Figure 9 An example is shown where a dummy memory cell transistor WLD1 is provided between the select gate transistor ST1 and the plurality of memory cell transistors MT, and a dummy memory cell transistor WLD2 is provided between the select gate transistor ST2 and the plurality of memory cell transistors MT.

[0097] The drains of the select gate transistors ST1 (strings String0 through String4) are all connected to the bit line BL and are subject to a specified bit line voltage. Additionally, the sources of the select gate transistors ST2 (strings String0 through String4) are all connected to the source line SELSRC.

[0098] During erasure, a high-voltage erase voltage Vera is applied to the source line SELSRC and the bit line BL. The potential difference with SGD / SGS is used to fill the holes (holes) generated by GIDL (Gate-Induced Drain Leakage) into the memory holes. As a result, the charge stored in the charge storage film of the memory cell transistor MT recombines with the holes and eliminates electrons, thereby restoring the threshold voltage to the Er level (erasure level).

[0099] Furthermore, in three-dimensional non-volatile memory devices, the pursuit of larger capacities necessitates a reduction in the diameter of the memory holes constituting the memory cells and the distance between them. This miniaturization easily introduces deviations during the word line formation process, causing significant and non-negligible variations in the operational characteristics of each string during erasure and programming. In particular, large deviations in the erase level can adversely affect the programming characteristics of the memory cells, resulting in write time deviations or variations in the amplitude of erase and programming stress, making it difficult to maintain uniform reliability across all memory cells.

[0100] (Improvement of Erase Characteristics for Each String) Therefore, in this embodiment, the erase characteristics of each string, i.e., the erase characteristics of each string component SU, are detected. Based on the detected erase characteristics, the timing of the application of the control voltage to the select gate line SGD used to turn on the select gate transistor ST1 is controlled for each string (each string component). Thus, a uniform erase level can be obtained in each string. In this embodiment, the erase characteristics are determined by the level of the erase level obtained during a normal erase operation (hereinafter referred to as the depth of the erase level). Furthermore, a lower erase level (a larger difference from level A) is considered to indicate a deeper erase level, and a higher erase level (a smaller difference from level A) is considered to indicate a shallower erase level.

[0101] Figure 10 and Figure 11 This is an explanatory diagram used to illustrate the depth of the erase level and the method for determining it. Figure 10 and Figure 11 Utilization and Figure 8 The same notation is used to represent the threshold distribution of the erase level of the storage cell array for each string. Figure 10 and Figure 11 This shows the erase level obtained when a normal erase operation is successful. All strings from String0 to String4 are below [level value missing]. Figure 8 The voltage VrA has a threshold distribution at the voltage level.

[0102] like Figure 10 and Figure 11 As shown, the depth of the erase level varies for each string. Figure 10 and Figure 11 In the example, the erase levels of strings String0 and String4 are the deepest, the erase level of string String2 is the shallowest, and strings String1 and String3 are the intermediate depths of the erase levels.

[0103] After a normal erase operation, sequencer 27 detects the depth of the erase level for each string. For example, in Figure 10In the example, sequencer 27 can also set a predetermined decision level (hereinafter referred to as the high-level decision level) on a level side higher than the peak of the threshold distribution where the number of units reaches its peak, and detect the number of units (bits) with a level higher than this high-level decision level, making a decision according to the principle that the fewer the number of units, the deeper the erase level, and the more the number of units, the shallower the erase level. Additionally, in Figure 11 In the example, the sequencer 27 can also set a predetermined judgment level (hereinafter referred to as the low level side judgment level) on the side of the threshold distribution where the number of units reaches the peak value, and detect the number of units (number of bits) whose level is lower than the low level side judgment level. The judgment is made according to the principle that the more units there are, the deeper the erase level is and the fewer units there are, the shallower the erase level is.

[0104] The sequencer 27 records the result of determining the erase level depth as erase level depth information in the management area of ​​the memory cell array 23. The sequencer 27 can record the number of cells of each string obtained through the determination as erase level depth information in the management area of ​​the memory cell array 23, or it can record the order of the erase level depth of each string as erase level depth information in the management area of ​​the memory cell array 23.

[0105] To determine the erase level depth information, sequencer 27 first sets a high-level side determination level or a low-level side determination level (hereinafter, when it is not necessary to distinguish between them, they are referred to as determination levels). To detect the number of cells with levels higher or lower than the determination level, sequencer 27 performs a readout operation by sequentially applying the determination level voltage to each word line WL and using the sensing amplifier 24 to determine the conduction state of each memory cell. In this case, to shorten the detection time required to detect the erase level depth, a predetermined number of memory cells can be determined instead of all memory cells within each string. Furthermore, assuming that the characteristics of each string are similarly generated in any memory cell transistor, a representative memory cell can be selected from each string, and several determination level voltages can be applied to the target word line WL for readout. Thus, the range of threshold voltages for the selected memory cell is detected, and the erase level depth in each string is determined based on the detected range of threshold voltages.

[0106] In this embodiment, based on the erase level depth information, the generation of the gate voltage during erasure is controlled by the SG driver 28A in the voltage generation circuit 28. That is, the SG driver 28A causes the gate voltage supplied to the select gate transistor ST1 of the string determined to have a shallower erase level by the erase level depth information to rise earlier, and the gate voltage supplied to the select gate transistor ST1 of the string determined to have a deeper erase level to rise later. For example, when the erase level depths from shallowest to deepest are string 2, string1, string3, string0, and string4, during erasure, the SG driver 28A is controlled such that the gate voltages supplied to the select gate transistors ST1 of string 2, string1, string3, string0, and string4 rise sequentially.

[0107] (Function) Next, refer to Figures 12 to 14 The operation of an implementation method configured in this way will be explained. Figure 12 This is a flowchart illustrating the erasing operation of the first embodiment. Figure 13 It means Figure 12 A flowchart of an example of the steps for characteristic testing in [the context of the test]. Figure 14 This is a waveform diagram showing the waveforms of each part during the erasure process in the first embodiment.

[0108] Figure 12 Step S1 illustrates the characteristic test performed before product shipment. In this characteristic test, the erase level depth is pre-calculated for each string and recorded as erase level depth information in the management area of ​​the storage cell array 23.

[0109] Figure 13 This illustrates an example of the specific steps involved in depth detection of the erase level during a particular test. Figure 13In step S21, the device is evaluated for pass / fail. If it fails (NO determination in S22), the device is treated as a defective product (S23). If it passes (NO determination in S22), in steps S24 to S26, the erase characteristics are determined and the erase settings for each string are configured. That is, firstly, the block is erased through a normal erase operation (S24). Next, the erase level depth of each string is determined using the method described above (S25). For example, based on the determination level, the number of units (bits) exceeding the determination level is counted, and the erase level depth is determined by the count value. Then, the erase level depth information for each string is set for the SG driver 28A in the voltage generation circuit 28.

[0110] For example, when the depth of the erase level determined in step S25 is string String2, string1, string3, string0, string4 in order from shallow to deep, the SG driver 28A is set so that the gate voltage supplied to the gate selection transistor ST1 of string String2, the gate selection transistor ST1 of string1, the gate selection transistor ST1 of string3, the gate selection transistor ST1 of string0, and the gate selection transistor ST1 of string4 increases in sequence.

[0111] The erase level depth information is recorded as device information in the management area of ​​the memory cell array 23 (S27).

[0112] Furthermore, the deviation in the erase characteristics of each string regarding the erase level depth is caused by the manufacturing process and may correspond to the three-dimensional structure of the memory cell array. For example, it is believed that there is a tendency for strings closer to the insulating layer ST to have a deeper erase level, and strings farther away from the insulating layer ST to have a shallower erase level. Therefore, it is not necessary to determine the erase level depth through characteristic testing, and this step can be omitted. Figure 13 In steps S24 to S26, the erase level depth information corresponding to the configuration of the string is recorded in the management area of ​​the storage cell array 23.

[0113] In actual use, when the power is turned on (S2), the sequencer 27 reads the device information from the management area of ​​the memory cell array 23 and sets the erase level depth information contained in the device information into the register (S3). The sequencer 27 performs erase, write, and read operations according to the input instructions (S4).

[0114] Now, let's assume an erase operation is indicated. In this case, the sequencer 27 controls the erase operation based on the erase level depth information. Hereinafter, the erase operation in this case will be referred to as a string-based erase operation. In a string-based erase operation, the sequencer 27 gives an instruction to the SG driver 28A of the voltage generation circuit 28 as follows: after the gate voltage rises based on the erase level depth information, it is applied to the select gate line SGD.

[0115] Figure 14 The waveforms of each part of the erase operation, displayed as a series, are shown. Figure 14 As shown, the sequencer 27 controls the voltage generation circuit 28. In the erase operation on a string-by-string basis, it first applies the erase voltage Vera to the source line CELSRC and the bit line BL. Next, the sequencer 27 applies a gate voltage to the select gate line SGS through the SG driver 28A to turn on the select gate transistor ST2, and sequentially applies a gate voltage to the select gate line SGD of each string to turn on the select gate transistor ST1. Figure 14 This example illustrates erase levels of depth from shallowest to deepest as strings String2, String1, String3, String0, and String4. In this case, as shown... Figure 14 As shown, the SG driver 28A first applies the gate voltage that turns on the select gate transistor ST1 of string String2 to the select gate line SGD2 (refer to...). Figure 9 Next, SG driver 28A applies the gate voltage that turns on the select gate transistor ST1 of String1 to the select gate line SGD1. Then, in the same manner, SG driver 28A supplies the gate voltage that turns on the select gate transistor ST1 of String3, the gate voltage that turns on the select gate transistor ST1 of String0, and the gate voltage that turns on the select gate transistor ST1 of String4 to the select gate lines SGD3, SGD0, and SGD4 in that order.

[0116] The result is that in string String2, which is the first string to be supplied with the gate voltage to turn on the select gate transistor ST1, the erase voltage Vera is applied to the memory cell transistors MT first. Therefore, the erase level of the memory cell transistors MT in string String2 tends to be deeper. Similarly, the select gate transistors ST1 of strings String1, String3, String0, and String4 are turned on sequentially, and the erase voltage Vera is applied sequentially to the memory cell transistors MT in each string. This causes the erase level to tend to deepen in the order of strings String2, String1, String3, String0, and String4. As a result, regardless of the characteristics of the erase level depth in each string, the erase level depth in each string tends to become more uniform through string-by-string erasure operations.

[0117] Therefore, it is possible to suppress the deviation in the write time of subsequent storage cells and maintain the reliability characteristics of the storage cells uniformly.

[0118] Furthermore, the erasure characteristics may change during actual use. Therefore, the sequencer 27 can also re-evaluate the erasure characteristics (the depth of the erasure level) at a predetermined timing, such as every predetermined number (e.g., several times) of string-based erasure actions (S5 monitors the depth of the erasure level). In addition, the number of string-based erasure actions for re-evaluating the erasure characteristics can be appropriately set.

[0119] In step S5, sequencer 27 determines whether the timing for evaluating erase characteristics has arrived (S11). If it is not the timing for evaluating erase characteristics (S11 negative determination), sequencer 27 determines whether an instruction has been received (S6). If sequencer 27 receives an instruction (S6 yes determination), the process returns to step S4 to perform the action corresponding to the instruction. Alternatively, if sequencer 27 does not receive an instruction (S6 negative determination), it determines whether a power-off indication has been given in the power-off sequence (S7) (S15). If there is no power-off indication (S15 negative determination), the process returns to step S6, entering the instruction standby state.

[0120] When sequencer 27 determines that it is time to evaluate the erase characteristics (the determination in S11), in step S12, it evaluates the erase characteristics and updates the register. That is, in this case, sequencer 27 performs... Figure 13 Steps S24 to S26 are processed in the same way. That is, the sequencer 27 performs a normal erase operation, determines the erase level depth for each string, and updates the register using the erase level depth information based on the determination result.

[0121] In this way, even if the erasure characteristics change, the erasure level can be made uniform.

[0122] In addition, while preserving the initial erase level depth information obtained in the characteristic test, new erase level depth information obtained by re-evaluating the erase level depth can also be recorded.

[0123] When the power is turned off (S15 is the determination), the sequencer 27 records the erase level depth information stored in the register in the management area of ​​the memory cell array 23 (S16), and then turns off the power (S17).

[0124] In this embodiment, the depth of the erase level is determined and recorded as the erase characteristic of each string. Based on the recorded information, the application period of the erase voltage for each string is adjusted. This allows for the uniformization of the erase level depth, improving erase characteristics and thereby enhancing the reliability of the memory cell.

[0125] Furthermore, while the description provides an explanation of the rising sequence of the gate voltage supplied to the select gate line SGD of each string, the rising sequence of the gate voltage may also be set to correspond to the depth of the erase level of each string.

[0126] (Second Implementation) Figure 15 This is a circuit diagram illustrating the second embodiment. Figure 15 The circuit configuration of each string in the storage cell array 23 is shown. Figure 15 In the middle, to and Figure 9 Identical components are labeled with the same symbols and their descriptions are omitted. The configuration of the storage cell array 23 in this embodiment differs from that in the first embodiment, but other configurations are the same as in the first embodiment.

[0127] like Figure 15 As shown, in this embodiment, gate voltages SGS0 to SGS4 are supplied to the gates of the select gate transistors ST2 for strings String0 to String4, respectively. That is, the difference between this embodiment and the first embodiment is that each select gate transistor ST2 for each string can be controlled independently.

[0128] Next, refer to Figure 16 The operation of an implementation method configured in this way will be explained. Figure 16 This is a waveform diagram showing the waveforms of each part during the erasure process in the second embodiment.

[0129] This embodiment also adopts Figure 12 and Figure 13The process is as follows. The difference between this embodiment and the first embodiment is that, in the erase operation on a string-by-string basis, not only is gate transistor ST1 controlled for each string, but gate transistor ST2 is also controlled for each string.

[0130] like Figure 16 As shown, the sequencer 27 controls the voltage generation circuit 28. In the erase operation on a string-by-string basis, the sequencer 27 first applies the erase voltage Vera to the source line CELSRC and the bit line BL. Then, the sequencer 27 sequentially applies the gate voltage that turns on the select gate transistors ST1 and ST2 to the select gate lines SGD and SGS of each string. Figure 16 This example illustrates the erase levels from shallowest to deepest as strings String2, String1, String3, String0, and String4. In this case, as shown... Figure 16 As shown, the SG driver 28A first applies the gate voltage that turns on the select gate transistors ST1 and ST2 of string String2 to the select gate lines SGD2 and SGS2 (refer to...). Figure 15 Next, the SG driver 28A applies the gate voltage that turns on the select gate transistors ST1 and ST2 of String1 to the select gate lines SGD1 and SGS1. Then, in the same manner, the SG driver 28A supplies the gate voltage that turns on the select gate transistors ST1 and ST2 of String3, the gate voltage that turns on the select gate transistors ST1 and ST2 of String0, and the gate voltage that turns on the select gate transistors ST1 and ST2 of String4 to the select gate lines SGD3 and SGS3, SGD0 and SGS0, and SGD4 and SGS4, respectively, in that order.

[0131] The result is that in string String2, which is the first string supplied with the gate voltage to turn on the select gate transistors ST1 and ST2, the erase voltage Vera is applied first to multiple memory cell transistors MT. Therefore, the erase level of the memory cell transistors MT in String2 tends to be deeper. Subsequently, in the same manner, the select gate transistors ST1 and ST2 in strings String1, String3, String0, and String4 are turned on sequentially, and the erase voltage Vera is applied sequentially to the memory cell transistors MT in each string. This causes the erase level to tend to deepen in the order of strings String2, String1, String3, String0, and String4. As a result, regardless of the characteristics of the erase level depth in each string, the erase level depth in each string tends to become more uniform through string-by-string erasure operations.

[0132] Furthermore, in this embodiment, not only the select gate transistor ST1, but also the select gate transistor ST2 is controlled to be turned on in the same order as the select gate transistor ST1, thus providing more reliable control over the depth of the erase level compared to the first embodiment.

[0133] Thus, in this embodiment, the same effect as in the first embodiment can be obtained. Furthermore, in this embodiment, there is the advantage of improved control over the depth of the erase level.

[0134] (Third Implementation) Figure 17 This is a waveform diagram representing the third embodiment. The configuration of this embodiment is the same as that of the first embodiment. However, the control of the erase operation, which is performed on a string-by-string basis, differs from that in the first embodiment.

[0135] In the first embodiment, an example was described in which the rise timing of the gate voltage supplied to the select gate line SGD of each string was different based on the depth information of the erase level. However, in this embodiment, an example is described in which the voltage level of the gate voltage supplied to the select gate line SGD of each string is different based on the depth information of the erase level.

[0136] This embodiment also adopts Figure 12 and Figure 13 The process is as follows. The difference between this embodiment and the first embodiment is that, in the erase operation on a string-by-string basis, the gate voltage applied to the select gate transistor ST1 is changed for each string.

[0137] like Figure 17 As shown, the sequencer 27 controls the voltage generation circuit 28 to first apply an erase voltage Vera to the source line CELSRC and the bit line BL during the string-by-string erase operation. Next, the sequencer 27 simultaneously applies gate voltages to the select gate lines SGD and SGS of each string, enabling the select gate transistors ST1 and ST2 to turn on. In this embodiment, the sequencer 27 controls the SG driver 28A of the voltage generation circuit 28 to supply a gate voltage based on the erase level depth information to the select gate line SGD of each string.

[0138] The conduction of the select gate transistor ST1 is controlled by the voltage difference between the gate voltage of the select gate line SGD and the voltage (erase voltage Vera) of the bit line BL, thereby changing the amount of holes generated in the channel. In other words, the larger the voltage difference between the select gate line SGD and the erase voltage Vera of the bit line BL, the more holes are generated, and the easier it is to achieve a deeper erase level. Therefore, for strings with shallower erase levels, the gate voltage supplied to the SGD of that string is lower, and for strings with deeper erase levels, the gate voltage supplied to the SGD of that string is higher.

[0139] Figure 17 This example illustrates the erase levels, from shallowest to deepest, as String2, String1, String3, String0, and String4. In this case, as... Figure 17 As shown, the SG driver 28A applies a minimum gate voltage to the select gate line SGD2 of the select gate transistor ST1 in string String2, which supplies the gate voltage to the select gate line. Additionally, the SG driver 28A applies a higher gate voltage to the select gate line SGD1 than the gate voltage applied to the select gate line SGD2, as the gate voltage that turns on the select gate transistor ST1 in string String1. When the gate voltages applied to the select gate lines SGD0 to SGD4 in the same manner are set to VSGD0 to VSGD4 respectively, the SG driver 28A supplies gate voltages with the relationship VSGD2 < VSGD1 < VSGD3 < VSGD0 < VSGD4 to the select gate lines SGD0, SGD1, SGD3, SGD0, and SGD4 respectively.

[0140] The result is that the number of holes in the channel increases in the order of strings String2, String1, String3, String0, and String4, and the erase level tends to increase in depth in this order. Therefore, regardless of the characteristics of the erase level depth of each string, the erase level depth across all strings can easily become uniform through string-by-string erase operations.

[0141] In this way, this embodiment can also achieve the same effect as the first embodiment.

[0142] (Fourth implementation) Figure 18 This is a waveform diagram representing the fourth embodiment. The configuration of this embodiment is the same as that of the second embodiment. However, the control of the erase operation, which is performed on a string-by-string basis, differs from that in the second embodiment.

[0143] In the second embodiment, an example was described in which the rise timing of the gate voltages supplied to the select gate lines SGD and SGS of each string was different based on the depth information of the erase level. However, in this embodiment, the example is that the voltage levels of the gate voltages supplied to the select gate lines SGD and SGS of each string are different based on the depth information of the erase level.

[0144] This embodiment also adopts Figure 12 and Figure 13 The process is as follows. The difference between this embodiment and the second embodiment is that, in the erase operation on a string-by-string basis, the gate voltage applied to the select gate transistors ST1 and ST2 is changed for each string.

[0145] like Figure 18 As shown, the sequencer 27 controls the voltage generation circuit 28 to first apply an erase voltage Vera to the source line CELSRC and the bit line BL during the string-by-string erase operation. Next, the sequencer 27 simultaneously applies gate voltages to the select gate lines SGD and SGS of each string, enabling the select gate transistors ST1 and ST2 to turn on. In this embodiment, the sequencer 27 controls the SG driver 28A of the voltage generation circuit 28 to supply gate voltages based on erase level depth information to the select gate lines SGD and SGS of each string.

[0146] The conduction of the select gate transistor ST1 is controlled based on the voltage difference between the select gate line SGD and the bit line BL (erase voltage Vera), thereby changing the amount of holes generated in the channel. Similarly, the conduction of the select gate transistor ST2 is controlled based on the voltage difference between the select gate line SGS and the source line CELSRC (erase voltage Vera), thus changing the amount of holes generated in the channel. In other words, the larger the voltage difference between the select gate line SGD and the bit line BL's erase voltage Vera, and the larger the voltage difference between the select gate line SGS and the source line CELSRC's erase voltage Vera, the greater the amount of holes generated, and the easier it is to achieve a deeper erase level. Therefore, for strings with shallower erase levels, the gate voltages supplied to SGD and SGS are lower; for strings with deeper erase levels, the gate voltages supplied to SGD and SGS are higher.

[0147] Figure 18 This example illustrates the erase levels, from shallowest to deepest, as String2, String1, String3, String0, and String4. In this case, as... Figure 18As shown, the SG driver 28A applies a minimum gate voltage to the select gate lines SGD2 and SGS2 of the select gate transistors ST1 and ST2 of string String2. Additionally, the SG driver 28A applies gate voltages to select gate lines SGD1 and SGS1 that are higher than the gate voltages applied to select gate lines SGD2 and SGS2, respectively, as gate voltages to turn on the select gate transistors ST1 and ST2 of string String1. When the gate voltages of the select gate lines SGD0 to SGD4 of strings String0 to String4 are set to VSGD0 to VSGD4 respectively, and the gate voltages of the select gate lines SGS0 to SGS4 of strings String0 to String4 are set to VSGS0 to VSGS4 respectively, the SG driver 28A supplies gate voltages with the relationship VSGD2 < VSGD1 < VSGD3 < VSGD0 < VSGD4 to the select gate lines SGD2, SGD1, SGD3, SGD0, and SGD4, and supplies gate voltages with the relationship VSGS2 < VSGS1 < VSGS3 < VSGS0 < VSGS4 to the select gate lines SGS2, SGS1, SGS3, SGS0, and SGS4.

[0148] The result is that the number of holes in the channel increases in the order of strings String2, String1, String3, String0, and String4, and the erase level tends to increase in depth in this order. Therefore, regardless of the characteristics of the erase level depth of each string, the erase level depth across all strings can easily become uniform through string-by-string erase operations.

[0149] Furthermore, in this embodiment, not only the select gate transistor ST1, but also the select gate transistor ST2 are applied with different gate voltages in the same order as the select gate transistor ST1, thus enabling more reliable control over the depth of the erase level compared to the third embodiment.

[0150] In this way, this embodiment can achieve the same effect as the third embodiment. Furthermore, compared with the third embodiment, this embodiment has the advantage of improved control over the depth of the erase level.

[0151] This invention is not limited to the described embodiments, and various changes can be made during the implementation phase without departing from its spirit. Furthermore, the embodiments encompass inventions at various stages, and various inventions can be proposed through appropriate combinations of the disclosed constituent elements. For example, even if several constituent elements are deleted from all the constituent elements shown in the embodiments, the problems described in the "Problems Solved by the Invention" section can be solved, and if the effects described in the "Effects of the Invention" section can be obtained, then the configuration after deleting those constituent elements can be proposed as an invention.

[0152] For example, the first to fourth embodiments can be combined to control the application time and voltage level of the gate voltage applied to the select gate transistors ST1 and ST2 based on the erase level depth information.

Claims

1. A semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The control circuit is: In the erasure operation, at least one of the following is performed for each of the plurality of strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the erasure operation, at least one of the following processes is performed for each of the plurality of strings: a third process that changes the application time of the second voltage applied to the gate of the second selection transistor and a fourth process that changes the voltage of the second voltage applied to the gate of the second selection transistor. In the third process, the control circuit, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, makes the application time of the second voltage applied to the gate of the second select transistor of the first string longer than the application time of the second voltage applied to the gate of the second select transistor of the second string.

2. A semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The control circuit is: In the erasure operation, at least one of the following is performed for each of the plurality of strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the erasure operation, at least one of the following processes is performed for each of the plurality of strings: a third process that changes the application time of the second voltage applied to the gate of the second selection transistor and a fourth process that changes the voltage of the second voltage applied to the gate of the second selection transistor. When the control circuit performs the fourth process, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, the second voltage applied to the gate of the second select transistor of the first string is higher than the second voltage applied to the gate of the second select transistor of the second string.

3. A semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The control circuit is: In the erasure operation, at least one of the following is performed for each of the plurality of strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the first process, the control circuit, for a first string containing memory cell transistors having a depth of a first erase level and a second string containing memory cell transistors having a depth of a second erase level deeper than the first erase level, makes the application time of the first voltage applied to the gate of the first select transistor in the first string longer than the application time of the first voltage applied to the gate of the first select transistor in the second string.

4. A semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The control circuit is: In the erasure operation, at least one of the following is performed for each of the plurality of strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. When the control circuit performs the second process, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, the first voltage applied to the gate of the first select transistor in the first string is higher than the first voltage applied to the gate of the first select transistor in the second string.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein The control circuit has: The determination unit determines the erase level depth for each string; and The Records Department records the judgment results.

6. The semiconductor memory device according to claim 5, wherein The depth of the erase level is determined based on the result of counting the number of memory cell transistors in the string that are above or below a specified threshold voltage.

7. A data erasure method, which is a data erasure method for a semiconductor memory device, the semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The data erasure method performs at least one of the following processes on each of the strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the erasure operation, at least one of the following processes is performed on each of the plurality of strings: a third process that changes the application time of the second voltage applied to the gate of the second selection transistor and a fourth process that changes the voltage of the second voltage applied to the gate of the second selection transistor. In the third process, the control circuit, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, makes the application time of the second voltage applied to the gate of the second select transistor of the first string longer than the application time of the second voltage applied to the gate of the second select transistor of the second string.

8. A data erasure method, which is a data erasure method for a semiconductor memory device, the semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The data erasure method performs at least one of the following processes on each of the strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the erasure operation, at least one of the following processes is performed on each of the plurality of strings: a third process that changes the application time of the second voltage applied to the gate of the second selection transistor and a fourth process that changes the voltage of the second voltage applied to the gate of the second selection transistor. When the control circuit performs the fourth process, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, the second voltage applied to the gate of the second select transistor of the first string is higher than the second voltage applied to the gate of the second select transistor of the second string.

9. A data erasure method, which is a data erasure method for a semiconductor memory device, the semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The data erasure method performs at least one of the following processes on each of the strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. In the first process, the control circuit, for a first string containing memory cell transistors having a depth of a first erase level and a second string containing memory cell transistors having a depth of a second erase level deeper than the first erase level, makes the application time of the first voltage applied to the gate of the first select transistor in the first string longer than the application time of the first voltage applied to the gate of the first select transistor in the second string.

10. A data erasure method, which is a data erasure method for a semiconductor memory device, the semiconductor memory device comprising: Multiple strings, sequentially comprising a first selection transistor, multiple memory cell transistors, and a second selection transistor; Multiple word lines are respectively connected to the memory cell transistors in the same row of the multiple strings; Bit lines are commonly connected to the ends of the plurality of strings; The source lines are commonly connected to the other end of the plurality of strings; and The control circuit performs the erase operation on the plurality of memory cell transistors; and The data erasure method performs at least one of the following processes on each of the strings: a first process that changes the application time of a first voltage applied to the gate of the first selection transistor and a second process that changes the voltage of the first voltage applied to the gate of the first selection transistor. When the control circuit performs the second process, for a first string of memory cell transistors containing a depth having a first erase level and a second string of memory cell transistors containing a depth having a second erase level deeper than the first erase level, the first voltage applied to the gate of the first select transistor in the first string is higher than the first voltage applied to the gate of the first select transistor in the second string.

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