A high-power device packaging method and a high-power device

Abstract

The application provides a high-power device packaging method and a high-power device. The pin of the bottom electrode is grown along a first preset track by additive manufacturing, and glue is filled and packaged to expose the pin of the bottom electrode, so that at least two first extension columns are generated. The first extension columns are connected by additive manufacturing on a preset plane to generate a bottom electrode extension surface, and a top electrode extension surface is arranged on one side of the preset plane by additive manufacturing. The interconnection between the high-power device electrode and the packaging substrate is formed by the bottom electrode extension column surface and the top extension surface, so that the direct force of thermal stress on the chip electrode is effectively reduced, the reliability of the device is greatly improved, and the service life of the device is prolonged. At the same time, since the chip electrode is directly grown by additive manufacturing, the welding thermal resistance is reduced, and the heat dissipation capacity of the chip is greatly improved.

Description

Technical Field

[0001] This application relates to the field of high-power device technology, and in particular to a high-power device packaging method and a high-power device. Background Technology

[0002] With the development of high-power semiconductor devices, especially IGBTs (Insulated Gate Bipolar Transistors) used in electric vehicles, the impact of thermal stress is increasing as device power grows, severely affecting the reliability of high-power devices. Current packaging methods involve tightly bonding the power chip to the packaging substrate using thermal welding.

[0003] For high-power semiconductor devices, the need to withstand continuous high currents makes heat generation a major technical challenge for designers. Currently, the tight bonding method using thermal welding is rigid interconnection. However, under the thermal shock generated by long-term high currents, reliability issues such as solder joint breakage and chip electrode layer tearing may occur. Summary of the Invention

[0004] In view of the aforementioned problems, this application is made to provide a high-power device packaging method and a high-power device that overcomes or at least partially solves the aforementioned problems, comprising:

[0005] A high-power device packaging method is used to package a chip, the chip including a bottom electrode surface and a top electrode disposed opposite to the bottom electrode surface; the high-power device packaging method includes:

[0006] The pins of the bottom electrode are grown along a first preset trajectory using additive manufacturing, and then encapsulated with glue to expose the pins of the bottom electrode, to obtain at least two first extension posts;

[0007] The first extension column is connected in a preset plane by additive manufacturing to generate a bottom electrode extension surface, and a top electrode extension surface is provided in the preset plane on one side by additive manufacturing.

[0008] By using additive manufacturing, the pins of the top electrode surface are grown along a second preset trajectory and connected to the extended surface of the top electrode to form a conductive circuit, thereby obtaining a high-power device.

[0009] Preferably, the step of growing the pins of the bottom electrode along a first preset trajectory using additive manufacturing and encapsulating them with adhesive to expose the pins of the bottom electrode to obtain at least two first extension posts includes:

[0010] The chip is encapsulated with potting resin to obtain a first encapsulating layer; wherein the height of the first encapsulating layer is lower than that of the bottom electrode;

[0011] The pins of the bottom electrode are grown along a first preset trajectory to obtain at least two first extension pillars;

[0012] The first extension post is encapsulated with adhesive until the pin of the bottom electrode is exposed, thus obtaining a second encapsulating adhesive layer; wherein the surface of the second encapsulating adhesive layer is the preset plane.

[0013] Preferably, the step of connecting the first extension posts on a preset plane using additive manufacturing to generate a bottom electrode extension surface, and then forming a top electrode extension surface on one side of the preset plane using additive manufacturing, includes:

[0014] On the surface of the second encapsulating adhesive layer, the top surfaces of all the first extension posts are connected in the second target area by additive manufacturing to obtain the bottom electrode extension surface;

[0015] A top electrode extension surface is formed on the surface of the second encapsulating adhesive layer in a third target area by additive manufacturing; wherein, the top electrode extension surface includes a first top electrode extension surface and a second top electrode extension surface disposed on one side of the first top electrode extension surface.

[0016] Preferably, the step of connecting the top surfaces of all the first extension posts in the second target area by additive manufacturing on the surface of the second encapsulating adhesive layer to obtain the bottom electrode extension surface includes:

[0017] A second initial transition layer is laid on the surface of the second encapsulating adhesive layer;

[0018] A photosensitive material is coated on the surface of the second initial transition layer, and then exposed and developed to expose the second target portion of the second initial transition layer.

[0019] The second target area is etched away to form a second transition layer;

[0020] Remove the photosensitive material;

[0021] The bottom electrode extension surface is obtained by growing and removing the second transition layer in the second target area using additive manufacturing.

[0022] Preferably, the step of forming a top electrode extension surface in the third target region on the surface of the second encapsulating adhesive layer by additive manufacturing includes:

[0023] A third initial transition layer is laid on the surface of the second encapsulating adhesive layer;

[0024] A photosensitive material is coated on the surface of the third initial transition layer, and then exposed and developed to expose the third target portion of the third initial transition layer.

[0025] The third target area is etched away to form a third transition layer;

[0026] Remove the photosensitive material;

[0027] The top electrode extension surface is obtained by growing the third target area and removing the third transition layer using additive manufacturing.

[0028] Preferably, the step of growing the pins of the top electrode surface along a second preset trajectory using additive manufacturing, and connecting and conducting them with the extended surface of the top electrode to obtain a high-power device, includes:

[0029] A longitudinally extending through hole is provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer;

[0030] The top electrode is extended along the surface of the first encapsulating adhesive layer and the through hole to the top electrode extension surface of the second encapsulating adhesive layer by additive manufacturing, thus obtaining a second extension post.

[0031] Preferably, the through-hole includes a first through-hole and a second through-hole, and the step of providing a longitudinally extending through-hole inside the first encapsulating adhesive layer and the second encapsulating adhesive layer includes:

[0032] A first through hole and a second through hole extending longitudinally are provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer; wherein, the first through hole is located in the region of the extended surface of the first top electrode, and the second through hole is located in the region of the extended surface of the second top electrode.

[0033] Preferably, the step of extending the top electrode along the surface of the first encapsulating adhesive layer and the through-hole to the top electrode extension surface of the second encapsulating adhesive layer by additive manufacturing to obtain the second extension post includes:

[0034] A vertical column is fabricated along the interior of the through hole using additive manufacturing.

[0035] A horizontal column is prepared along the surface of the first encapsulating adhesive layer by additive manufacturing; wherein the vertical column and the horizontal column are connected and conductive to obtain the second extended column.

[0036] Preferably, the horizontal column is a straight line; or, the horizontal column is a curve.

[0037] Preferably, the height of the first extension column is 50-150 micrometers.

[0038] Preferably, the bottom electrode extension surface includes at least one bottom electrode sub-extension surface.

[0039] To achieve this, the application also includes a high-power device prepared according to the high-power device packaging method described above, wherein the chip includes a bottom electrode surface and a top electrode disposed opposite to the bottom electrode surface, characterized in that it includes: a chip, an encapsulating adhesive layer, a first extension post, a bottom electrode extension surface, a top electrode extension surface, and a second extension post;

[0040] The bottom electrode of the chip is connected to the extended surface of the bottom electrode via a first extension post; the top electrode of the chip is connected to the extended surface of the top electrode via a second extension post.

[0041] The encapsulating adhesive layer encapsulates the chip and the first extension post, and the bottom electrode extension surface and the top electrode extension surface are disposed on the surface of the encapsulating adhesive layer; wherein, the encapsulating adhesive layer includes a first encapsulating adhesive layer and a second encapsulating adhesive layer.

[0042] This application has the following advantages:

[0043] In the embodiments of this application, the pins of the bottom electrode are grown along a first preset trajectory using additive manufacturing, with a height of approximately 50 to 150 micrometers. The pins are then encapsulated with resin to expose the bottom electrode pins, resulting in at least two first extension pillars. These first extension pillars are connected on a preset plane using additive manufacturing to form a bottom electrode extension surface. A top electrode extension surface is also formed on one side of the preset plane using additive manufacturing. The pins of the top electrode surface are grown along a second preset trajectory using additive manufacturing and connected to the top electrode extension surface for conductivity, resulting in a high-power device. The bottom electrode extension pillars and top extension surface enable a flexible interconnection between the high-power device electrodes and the packaging substrate, effectively reducing the direct thermal stress on the chip electrodes, significantly improving device reliability, and extending device lifespan. Simultaneously, the direct additive manufacturing of the chip electrodes reduces soldering thermal resistance, significantly improving the chip's heat dissipation capacity. Attached Figure Description

[0044] To more clearly illustrate the technical solution of this application, the drawings used in the description of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0045] Figure 1 This is a flowchart illustrating the steps of a high-power device packaging method according to an embodiment of this application;

[0046] Figure 2 This is a schematic diagram of the first extension post of a high-power device packaging method provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of the bottom electrode extension surface and the top electrode extension surface of a high-power device packaging method provided in an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of a high-power device package provided in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the internal structure of a high-power device packaging method provided in an embodiment of this application;

[0050] Figure 6 This is a schematic diagram of the internal structure of a high-power device packaging method provided in an embodiment of this application;

[0051] Figure 7 This is a schematic diagram of a high-power device package provided in an embodiment of this application;

[0052] The reference numerals in the accompanying drawings are as follows:

[0053] 1. Chip; 2. First extension post; 3. Bottom electrode extension surface; 4. Top electrode extension surface; 5. Second extension post; 51. Vertical post; 52. Horizontal post. Detailed Implementation

[0054] To make the objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0055] Reference Figure 1-7 This application illustrates a high-power device packaging method according to an embodiment of the present application, the high-power device packaging method comprising:

[0056] S110. The pins of the bottom electrode are grown along a first preset trajectory by additive manufacturing and encapsulated with glue to expose the pins of the bottom electrode to obtain at least two first extension posts 2.

[0057] S120. The first extension column 2 is connected on a preset plane by additive manufacturing to generate a bottom electrode extension surface 3, and a top electrode extension surface 4 is provided on the preset plane on one side by additive manufacturing.

[0058] S130. The pins of the top electrode surface are grown along the second preset trajectory by additive manufacturing and connected to the extended surface 4 of the top electrode to obtain a high-power device.

[0059] In the embodiments of this application, the pins of the bottom electrode are grown along a first preset trajectory using additive manufacturing, with a height of 50 micrometers to 150 micrometers. The pins are then encapsulated with resin to expose the bottom electrode, resulting in at least two first extension pillars 2. These first extension pillars 2 are connected on a preset plane using additive manufacturing to form a bottom electrode extension surface 3. A top electrode extension surface 4 is then formed on one side of the preset plane using additive manufacturing. The pins of the top electrode surface are grown along a second preset trajectory using additive manufacturing and connected to the top electrode extension surface 4 for conductivity, resulting in a high-power device. The bottom electrode extension pillars and top extension surface enable a flexible interconnection between the high-power device electrodes and the packaging substrate, effectively reducing the direct thermal stress on the chip electrodes, significantly improving device reliability, and extending device lifespan. Simultaneously, the direct additive manufacturing of the chip electrodes reduces soldering thermal resistance, significantly improving the chip's heat dissipation capacity.

[0060] The following will further describe a high-power device packaging method in this exemplary embodiment.

[0061] As described in step S110, the pins of the bottom electrode are grown along a first preset trajectory using additive manufacturing, and then encapsulated with glue to expose the pins of the bottom electrode, resulting in at least two first extension posts 2.

[0062] As described in the following steps, the chip 1 is potted and encapsulated to obtain a first encapsulating adhesive layer; wherein the height of the first encapsulating adhesive layer is lower than that of the bottom electrode; the pins of the bottom electrode are grown along a first preset trajectory to obtain at least two first extension pillars 2 with a height of 50 micrometers to 150 micrometers; the first extension pillars 2 are potted and encapsulated until the pins of the bottom electrode are exposed to obtain a second encapsulating adhesive layer; wherein the surface of the second encapsulating adhesive layer is the preset plane.

[0063] In one specific embodiment, the first extension column 2 can be 50 micrometers, or it can be 150 micrometers, 75 micrometers, 85 micrometers, etc.

[0064] In one specific embodiment, the chip 1 is placed on the first carrier tape, with the top electrode facing down and the bottom electrode facing up; wherein the top electrode consists of two circular electrodes, and the bottom electrode consists of square electrodes. The chip 1 is encapsulated with potting compound and then dried to obtain a first encapsulating layer; the height of the first encapsulating layer is lower than the bottom electrode, exposing the periphery and top surface of the bottom electrode; the encapsulating compound is dried at 60-160°C. The extension surface 3 of the bottom electrode and the extension surface 4 of the top electrode have the same thickness. The first and second encapsulating layers formed after curing have good insulation and sealing properties, providing protection and preventing the product from getting damp. The top electrode includes a first top electrode and a second top electrode.

[0065] In one specific embodiment, the specific steps for potting and encapsulating the first extension post 2 to expose the pin of the bottom electrode to obtain the second encapsulation layer are as follows: potting encapsulation adhesive on the surface of the first encapsulation layer and drying it to form the second encapsulation layer. The second encapsulation layer is at the same height as the top of the first extension post 2, and the second encapsulation layer is exposed above the top of the first extension post 2.

[0066] It should be noted that the encapsulating adhesive is made of one or more of epoxy resin, silicone, PI resin, PE resin and PT resin.

[0067] In one embodiment of the present invention, the specific process of "growing the pins of the bottom electrode along a first preset trajectory to obtain at least two first extension pillars 2" can be further explained in conjunction with the following description.

[0068] In one specific embodiment, the pins of the bottom electrode are grown along a first preset trajectory by additive manufacturing, the first preset trajectory being vertical, to obtain at least two first extension posts 2; the first extension posts 2 can be 5 rows and 6 columns, that is, 30 first extension posts 2.

[0069] In one specific embodiment, an initial transition layer is deposited on the surface of the bottom electrode; a photosensitive material is coated on the surface of the initial transition layer, and exposure and development are performed to expose a first target portion of the initial transition layer; wherein, the first target portion is the portion of the first extension post 2; the first target portion is etched away to form a transition layer; the photosensitive material is removed; the transition layer is grown and removed in the first target area by additive manufacturing to obtain at least two first extension posts 2. Specifically, the photosensitive material is coated on the surface of the first encapsulating adhesive layer, and exposure and development are performed, so that the photosensitive material that has undergone photopolymerization is cured to form a first photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the first target portion) is washed away. The photosensitive material includes one or more of the following: photoresist (including positive and negative photoresist), photosensitive polyimide resin, photosensitive sol-gel or mixtures or compositions thereof, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, which has good photosensitivity properties.

[0070] The first extension post 2 is fabricated on the surface of the first target region using additive manufacturing. Specifically, the first longitudinally extending extension post 2 is fabricated on the surface of the first target region using additive manufacturing, such that the top of the pin of the bottom electrode extends to the preset height. The photosensitive material is then removed. Specifically, the photosensitive material is removed using a remover.

[0071] It should be noted that additive manufacturing (AM), also known as 3D printing, is a manufacturing technology that uses digital model files as a basis and employs software and CNC systems to deposit specialized metallic, non-metallic, or medical / biological materials layer by layer through methods such as extrusion, sintering, melting, photopolymerization, and spraying to create physical objects. Specifically, the additive manufacturing methods involved in this application can be one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and electroless plating.

[0072] As described in step S120, the first extension column 2 is connected on a preset plane by additive manufacturing to generate a bottom electrode extension surface 3, and a top electrode extension surface 4 is provided on the preset plane on one side by additive manufacturing.

[0073] In one embodiment of the present invention, the specific process of step S120, "connecting the first extension column 2 on a preset plane by additive manufacturing to generate a bottom electrode extension surface 3, and setting a top electrode extension surface 4 on the preset plane by additive manufacturing on one side", can be further described in conjunction with the following description.

[0074] As described in the following steps, the top surfaces of all the first extension posts 2 are connected in the second target area by additive manufacturing on the surface of the second encapsulating adhesive layer to obtain the bottom electrode extension surface 3; the top electrode extension surface 4 is provided in the third target area by additive manufacturing on the surface of the second encapsulating adhesive layer; wherein, the top electrode extension surface 4 includes a first top electrode extension surface 4 and a second top electrode extension surface 4 disposed on one side of the first top electrode extension surface 4.

[0075] In one specific embodiment, a photosensitive material is coated on the surface of the second encapsulating adhesive layer, and then exposed and developed to expose the third target area of ​​the second encapsulating adhesive layer. Specifically, the photosensitive material is coated on the surface of the second encapsulating adhesive layer, and then exposed and developed, causing the photosensitive material that has undergone photopolymerization to solidify into a first photosensitive material layer, and the photosensitive material that has not undergone photopolymerization (i.e., the photosensitive material on the surface of the target area) to be washed away. The photosensitive material includes one or more of the following: photoresist (including positive and negative photoresist), photosensitive polyimide resin, photosensitive sol-gel or mixtures or compositions thereof, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, which has good photosensitivity properties.

[0076] In one embodiment of the present invention, the specific process of "connecting the top surfaces of all the first extension posts 2 in the second target area by additive manufacturing on the surface of the second encapsulating adhesive layer to obtain the bottom electrode extension surface 3" can be further described in conjunction with the following description.

[0077] As described in the following steps, a second initial transition layer is laid on the surface of the second encapsulating adhesive layer; a photosensitive material is coated on the surface of the second initial transition layer, and exposure and development are performed to expose the second target portion of the second initial transition layer; the second target portion is etched away to form the second transition layer; the photosensitive material is removed; the second transition layer is grown and removed in the second target area by additive manufacturing to obtain the bottom electrode extension surface 3.

[0078] In one specific embodiment, the bottom electrode extension surface 3 is square, connecting all the first extension posts 2 within the range, and the bottom electrode extension surface 3 covers the top of the first extension posts 2.

[0079] In one specific embodiment, the bottom electrode extension surface 3 includes the extension surface of each pair of first extension posts 2 corresponding to the first extension posts 2.

[0080] In one embodiment of the present invention, the specific process of "setting a top electrode extension surface 4 on the surface of the second encapsulating adhesive layer in the third target area by additive manufacturing" can be further described in conjunction with the following description.

[0081] As described in the following steps, a third initial transition layer is laid on the surface of the second encapsulating adhesive layer; a photosensitive material is coated on the surface of the third initial transition layer, and exposure and development are performed to expose the third target portion of the third initial transition layer; the third target portion is etched away to form the third transition layer; the photosensitive material is removed; the third initial transition layer is grown in the third target area by additive manufacturing and then removed to obtain the top electrode extension surface 4.

[0082] In one specific embodiment, the top electrode extension surface 4 includes a first top electrode extension surface 4 and a second top electrode extension surface 4. The first top electrode extension surface 4 is used to correspond to the first top electrode extension surface 4 of the top electrode, and the second top electrode extension surface 4 is used to correspond to the second top electrode extension surface 4 of the top electrode.

[0083] In one specific embodiment, the top electrode is extended and disposed on one side of the bottom electrode extension surface 3.

[0084] As described in step S130, the pins of the top electrode surface are grown along the second preset trajectory by additive manufacturing and connected to the extended surface 4 of the top electrode to obtain a high-power device.

[0085] As described in the following steps, a longitudinally extending through hole is provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer; the top electrode is extended along the surface of the first encapsulating adhesive layer and the through hole to the top electrode extension surface 4 of the second encapsulating adhesive layer by additive manufacturing, to obtain the second extension post 5.

[0086] In one embodiment of the present invention, the specific process of the step "the through hole includes a first through hole and a second through hole, wherein a longitudinally extending through hole is provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer" can be further described in conjunction with the following description.

[0087] As described in the following steps, a first through hole and a second through hole extending longitudinally are provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer; wherein, the first through hole is provided in the region of the first top electrode extension surface 4, and the second through hole is provided in the region of the second top electrode extension surface 4.

[0088] In one specific embodiment, the bottom electrode extension surface 3 and the top electrode extension surface 4 are flipped so that they are connected to the second carrier tape. The vias are etched off on the surface of the first encapsulating adhesive layer. The vias are located on the top electrode extension surface 4. The first via corresponds to the position of the first top electrode extension surface 4, that is, the first via is in the orthographic projection area of ​​the first top electrode extension surface 4. The second via corresponds to the position of the second top electrode extension surface 4, that is, the second via is in the orthographic projection area of ​​the second top electrode extension surface 4.

[0089] In one specific embodiment, etching removal involves coating a photosensitive material onto the surface of the first encapsulating adhesive layer, and then exposing and developing it to expose the through-hole portion; the through-hole portion is then etched away to remove the photosensitive material.

[0090] In one embodiment of the present invention, the specific process of "extending the top electrode along the surface of the first encapsulating adhesive layer and the through hole to the top electrode extension surface 4 of the second encapsulating adhesive layer by additive manufacturing to obtain the second extension post 5" can be further described in conjunction with the following description.

[0091] In one specific embodiment, the second extension column 5 includes a horizontal column 52 and a vertical column 51.

[0092] As described in the following steps, a vertical column 51 is fabricated along the interior of the through-hole using additive manufacturing; a horizontal column 52 is fabricated along the surface of the first encapsulating adhesive layer using additive manufacturing; wherein the vertical column 51 and the horizontal column 52 are connected and conductive to obtain the second extension column 5. The horizontal column 52 is a straight line; or; the horizontal column 52 is a curve. In a specific embodiment, the bottom electrode extension surface can be composed of several bottom electrode sub-extension surfaces to reduce the influence of thermal stress caused by thermal expansion and contraction; at the same time, the upper electrode is interconnected by curved lines, which can also reduce the force of thermal stress on the upper electrode; wherein the number of bottom electrode sub-extension surfaces can be 2, 4, 8, 18, etc.

[0093] In one specific embodiment, a vertical column 51 is grown in the through hole by additive manufacturing. The vertical column 51 is a vertical cylinder, and the exposed top of the vertical column 51 is connected to the top electrode extension surface 4 by a horizontal column 52.

[0094] In one specific embodiment, the vertical column 51 includes a first vertical column 51 and a second vertical column 51, and the horizontal column 52 includes a first horizontal column 52 and a second horizontal column 52. The first top electrode extension surface 4 is connected to the first vertical column 51 via the first horizontal column 52, and the first horizontal column 52 is connected to the first top electrode via the first vertical column 51. The second top electrode extension surface 4 is connected to the second vertical column 51 via the second horizontal column 52, and the second horizontal column 52 is connected to the second top electrode via the second vertical column 51.

[0095] In one specific embodiment, the horizontal post 52 is disposed on the surface of the first encapsulating adhesive layer, and can be either a straight line or a curve. Finally, the second carrier tape is removed.

[0096] In one specific embodiment:

[0097] 1. Arrange chips 1 in batches on carrier tape 1.

[0098] 2. Fill the encapsulating resin up to expose the bottom electrode of chip 1.

[0099] 3. Selectively grow metal pillars on the bottom electrode of chip 1

[0100] 4. Pour bottom filler adhesive until the metal column surface is exposed.

[0101] 5. Connect electrodes to the metal pillar or connect electrodes in sections.

[0102] 6. Flip it onto carrier tape 2.

[0103] 7. Drill through holes to the designed electrode positions.

[0104] 8. Metallize the through-hole and connect it to the electrode.

[0105] 9. Connect the metallized via to the electrode on chip 1.

[0106] 10. Fill and encapsulate with adhesive, then cut and shape.

[0107] 11. Remove the carrier belt and complete the second finished product.

[0108] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0109] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0110] The above provides a detailed description of a high-power device packaging method and a high-power device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for packaging high-power devices, used to package chips, characterized in that, The chip includes a bottom electrode surface and a top electrode surface disposed opposite to the bottom electrode surface; The high-power device packaging method includes: The chip is encapsulated with potting resin to obtain a first encapsulating layer; wherein the height of the first encapsulating layer is lower than that of the bottom electrode; The pins of the bottom electrode are grown along a first preset trajectory to obtain at least two first extension pillars; The first extension post is encapsulated with potting compound until the pin of the bottom electrode is exposed, thus obtaining a second encapsulating compound layer; wherein, the surface of the second encapsulating compound layer is a predetermined plane; On the surface of the second encapsulating adhesive layer, the top surfaces of all the first extension posts are connected in the second target area by additive manufacturing to obtain the bottom electrode extension surface; A top electrode extension surface is formed on the surface of the second encapsulating adhesive layer in a third target area by additive manufacturing; wherein, the top electrode extension surface includes a first top electrode extension surface and a second top electrode extension surface disposed on one side of the first top electrode extension surface; A longitudinally extending through hole is provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer; A vertical column is fabricated along the interior of the through hole using additive manufacturing. A horizontal column is fabricated along the surface of the first encapsulating adhesive layer using additive manufacturing; wherein the vertical column and the horizontal column are connected and conductive to form a second extension column, such that the top electrode extends along the surface of the first encapsulating adhesive layer and the through hole to the top electrode extension surface of the second encapsulating adhesive layer and is connected and conductive to obtain a high-power device.

2. The high-power device packaging method according to claim 1, characterized in that, The step of connecting the top surfaces of all the first extension posts in the second target area by additive manufacturing on the surface of the second encapsulating adhesive layer to obtain the bottom electrode extension surface includes: A second initial transition layer is laid on the surface of the second encapsulating adhesive layer; A photosensitive material is coated on the surface of the second initial transition layer, and then exposed and developed to expose the second target portion of the second initial transition layer. The second target area is etched away to form a second transition layer; Remove the photosensitive material; The bottom electrode extension surface is obtained by growing and removing the second transition layer in the second target area using additive manufacturing.

3. The high-power device packaging method according to claim 1, characterized in that, The step of forming a top electrode extension surface in the third target region on the surface of the second encapsulating adhesive layer by additive manufacturing includes: A third initial transition layer is laid on the surface of the second encapsulating adhesive layer; A photosensitive material is coated on the surface of the third initial transition layer, and then exposed and developed to expose the third target portion of the third initial transition layer. The third target area is etched away to form a third transition layer; Remove the photosensitive material; The top electrode extension surface is obtained by growing the third target area and removing the third transition layer using additive manufacturing.

4. The high-power device packaging method according to claim 1, characterized in that, The through-hole includes a first through-hole and a second through-hole, and the step of providing a longitudinally extending through-hole inside the first encapsulating adhesive layer and the second encapsulating adhesive layer includes: A first through hole and a second through hole extending longitudinally are provided inside the first encapsulating adhesive layer and the second encapsulating adhesive layer; wherein, the first through hole is located in the region of the extended surface of the first top electrode, and the second through hole is located in the region of the extended surface of the second top electrode.

5. The high-power device packaging method according to claim 1, characterized in that, The horizontal column is a straight line; or the horizontal column is a curve.

6. The high-power device packaging method according to claim 1, characterized in that, The height of the first extension column is 50-150 micrometers.

7. The high-power device packaging method according to claim 1, characterized in that, The bottom electrode extension surface includes at least one bottom electrode sub-extension surface.

8. A high-power device prepared by the high-power device packaging method according to any one of claims 1-7, wherein the chip includes a bottom electrode surface and a top electrode disposed opposite to the bottom electrode surface, characterized in that, include: Chip, encapsulating adhesive layer, first extension post, bottom electrode extension surface, top electrode extension surface, and second extension post; The bottom electrode of the chip is connected to the extended surface of the bottom electrode via a first extension post; the top electrode of the chip is connected to the extended surface of the top electrode via a second extension post. The encapsulating adhesive layer encapsulates the chip and the first extension post, and the bottom electrode extension surface and the top electrode extension surface are disposed on the surface of the encapsulating adhesive layer; wherein, the encapsulating adhesive layer includes a first encapsulating adhesive layer and a second encapsulating adhesive layer.

Images