Semiconductor device

Abstract

The semiconductor device of the embodiment includes an element region including a transistor, a first diode, and a first contact portion; a terminal region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the terminal region, and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The terminal region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region toward the terminal region is 2 times or more the thickness of the silicon carbide layer.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-154763 (filed on September 22, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods mainly involve semiconductor devices. Background Technology

[0004] Silicon carbide is anticipated as a material for next-generation semiconductor devices. Compared to silicon, silicon carbide possesses superior physical properties, including a band gap three times larger, a destructive electric field strength approximately ten times stronger, and thermal conductivity approximately three times greater. If these properties are effectively utilized, it could, for example, enable the realization of high-voltage, low-loss, and high-temperature-capable metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0005] Vertical MOSFETs using silicon carbide have a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is in the off state, return current can flow through by using the pn junction diode.

[0006] However, if a bipolar-operated PN junction diode carries a return current, stacking defects grow in the silicon carbide layer due to the recombination energy of charge carriers. When stacking defects grow in the silicon carbide layer, it causes an increase in the on-resistance of the MOSFET. This increased on-resistance leads to a decrease in the reliability of the MOSFET. For example, by incorporating a bipolar-operated Schottky barrier diode (SBD) as a built-in diode in the MOSFET, stacking defects in the silicon carbide layer can be suppressed.

[0007] Sometimes, a large surge voltage exceeding the steady-state voltage is instantaneously applied to a MOSFET. When a large surge voltage is applied, a large surge current flows, generating heat and damaging the MOSFET. The maximum allowable peak surge current value of a MOSFET is called its surge current withstand capability. In MOSFETs equipped with surge current deflection (SBD), from a reliability perspective, it is desirable to improve the surge current withstand capability. Summary of the Invention

[0008] The implementation provides a semiconductor device with improved surge current tolerance.

[0009] A semiconductor device according to an embodiment includes: a component region including a transistor, a first diode, and a first contact; a terminal region surrounding the component region and including a second contact; and an intermediate region disposed between the component region and the terminal region, which does not include the transistor, the first diode, the first contact, and the second contact. The component region includes: a first electrode; a second electrode; a gate electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface on the second electrode side. The silicon carbide layer includes: a first silicon carbide region of a first conductivity type, having a first region contacting the first surface and opposite the gate electrode, and a second region contacting the first surface and contacting the first electrode; a second silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, adjacent to the first region, opposite the gate electrode, and contacting the first electrode at a first interface; and a third silicon carbide region of a first conductivity type, disposed between the second silicon carbide region and the first surface, and electrically connected to the first electrode; and a gate electrode. An insulating layer is disposed between the gate electrode and the second silicon carbide region, between the gate electrode and the first region, and between the gate electrode and the third silicon carbide region. The terminal region includes: a first wiring layer electrically connected to the first electrode; a second electrode; and the silicon carbide layer, including the first silicon carbide region and a fourth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface and in contact with the first wiring layer at a second interface. The intermediate region includes the silicon carbide layer, the silicon carbide layer including the first silicon carbide region and a fifth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface. The transistor includes the gate electrode, the gate insulating layer, the first region, the second silicon carbide region, and the third silicon carbide region. The first diode includes the first electrode and the second region. The first contact portion includes the first interface, and the second contact portion includes the second interface. The width of the intermediate region in the direction from the element region toward the terminal region is more than twice the thickness of the silicon carbide layer. Attached Figure Description

[0010] Figure 1A , Figure 1B This is a schematic top view of the semiconductor device according to the first embodiment.

[0011] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0012] Figure 3 This is a schematic top view of the semiconductor device according to the first embodiment.

[0013] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0014] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0015] Figure 6 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0016] Figure 7 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0017] Figure 8 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0018] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0019] Figure 10A , Figure 10B This is a schematic top view of the semiconductor device according to the third embodiment.

[0020] Figure 11A , Figure 11B This is a schematic top view of the semiconductor device according to the third embodiment.

[0021] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0022] Figure 13 This is a schematic top view of the semiconductor device according to the third embodiment.

[0023] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0024] Figure 15 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0025] Figure 16 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the third embodiment.

[0026] Figure 17 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have already been described once will sometimes be appropriately omitted.

[0028] Additionally, in the following explanation, when there exists n + n, n － and p + p, p － In the case of markings, these markings indicate the relative levels of impurity concentration for each conductivity type. That is, n + This indicates that the concentration of n-type impurities is relatively higher than that of n. － This indicates that the concentration of n-type impurities is relatively lower than that of n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. － This indicates that the concentration of p-type impurities is relatively lower than that of p-type impurities. Additionally, sometimes n-type impurities are used... + type, n － The type is simply recorded as type n, and p is... + Type, p － The type is simply recorded as p-type.

[0029] Furthermore, unless otherwise specified in this specification, "impurity concentration" refers to the concentration after compensating for the concentration of impurities of the opposite conductivity type. That is, the n-type impurity concentration of an n-type silicon carbide region is the concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration. Similarly, the p-type impurity concentration of a p-type silicon carbide region is the concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration.

[0030] In addition, unless otherwise specified in this specification, "impurity concentration of silicon carbide region" refers to the maximum impurity concentration of the corresponding silicon carbide region.

[0031] Impurity concentration can be measured, for example, using time-of-flight secondary ion mass spectrometry (TOF-SIMS). Furthermore, the relative level of impurity concentration can be determined, for example, based on the carrier concentration obtained using scanning capacitance microscopy (SCM). Additionally, the depth, thickness, and spacing of impurity regions can be determined, for example, using TOF-SIMS. Moreover, the depth, thickness, width, and spacing of impurity regions can be determined, for example, from a composite image obtained using SCM and atomic force microscopy (AFM) images.

[0032] (First Implementation)

[0033] The semiconductor device according to the first embodiment includes: a component region including a transistor, a first diode and a first contact; a terminal region surrounding the component region and including a second contact; and an intermediate region disposed between the component region and the terminal region, which does not include the transistor, the first diode and the first contact and the second contact. The component region includes: a first electrode; a second electrode; a gate electrode; a silicon carbide layer disposed between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface on the second electrode side, the silicon carbide layer including: a first silicon carbide region of a first conductivity type, having a first region contacting the first surface and opposite to the gate electrode and a second region contacting the first surface and contacting the first electrode; a second silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, adjacent to the first region, opposite to the gate electrode, and contacting the first electrode at a first interface; and a third silicon carbide region of a first conductivity type, disposed between the second silicon carbide region and the first surface, electrically connected to the first electrode; and a gate insulating layer disposed between the gate electrode and the second silicon carbide region, between the gate electrode and the first region, and between the gate electrode and the third silicon carbide region. The terminal region includes: a first wiring layer electrically connected to a first electrode; a second electrode; and a silicon carbide layer including a first silicon carbide region and a fourth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and a first surface and in contact with the first wiring layer at a second interface. The intermediate region includes a silicon carbide layer including a first silicon carbide region and a fifth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface. The transistor includes a gate electrode, a gate insulating layer, a first region, a second silicon carbide region, and a third silicon carbide region; the first diode includes a first electrode and a second region; a first contact portion includes a first interface; a second contact portion includes a second interface; and the width of the intermediate region in the direction from the element region toward the terminal region is more than twice the thickness of the silicon carbide layer.

[0034] Figure 1A , Figure 1B This is a schematic top view of the semiconductor device according to the first embodiment. Figure 1A A layout pattern representing the component area, terminal area, and intermediate area. Figure 1B This represents the layout pattern of the first electrode, the first wiring layer, the interconnect layer, the gate pad electrode, and the second wiring layer.

[0035] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1A The AA' section is shown.

[0036] Figure 3 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 3 Is with Figure 2The corresponding top view. Figure 3 This indicates the layout pattern of the first side of the semiconductor layer. Figure 3 This indicates the state after the first electrode and the interlayer insulation layer have been removed.

[0037] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 yes Figure 1A The BB' section is shown.

[0038] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 5 yes Figure 1A The CC' section is shown.

[0039] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 is, for example, a double-implantation MOSFET (DIMOSFET) whose body and source regions are formed by ion implantation. Furthermore, the semiconductor device of the first embodiment includes an SBD as a built-in diode.

[0040] The following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a longitudinal n-channel MOSFET with electrons as charge carriers.

[0041] The MOSFET 100 includes a first element region 101a (element region), a second element region 101b, a termination region 102, and an intermediate region 103. The first element region 101a is an example of an element region. Hereinafter, the first element region 101a and the second element region 101b are sometimes collectively referred to as element region 101.

[0042] Component region 101 includes multiple MOSFET regions and multiple SBD regions. MOSFET regions include transistors Tr. SBD regions include first diodes D1. Component region 101 includes a first contact C1. Termination region 102 includes a second contact C2 and a second diode D2.

[0043] The MOSFET 100 comprises a silicon carbide layer 10, a first source electrode 12a (first electrode), a second source electrode 12b, a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, a source wiring layer 20 (first wiring layer), a first interconnect layer 22a (interconnect layer), a second interconnect layer 22b, a gate interconnect line 23, a gate electrode pad 24, a gate wiring layer 26 (second wiring layer), an interlayer insulating layer 28, and a field insulating layer 30. The source wiring layer 20 has a first portion 20a, a second portion 20b, a third portion 20c, and a fourth portion 20d. The gate wiring layer 26 has a first line 26a, a second line 26b, and a third line 26c.

[0044] The first source electrode 12a is an example of a first electrode. The drain electrode 14 is an example of a second electrode. The source wiring layer 20 is an example of a first wiring layer. The first interconnect layer 22a is an example of an interconnect layer. The gate wiring layer 26 is an example of a second wiring layer.

[0045] In the following description, the first source electrode 12a and the second source electrode 12b are sometimes collectively referred to as source electrode 12. Additionally, the first interconnect layer 22a and the second interconnect layer 22b are sometimes collectively referred to as interconnect layer 22.

[0046] The silicon carbide layer 10 contains n + Type 32, n drain region － Type 34 drift region (first silicon carbide region), p-type bulk region 36 (second silicon carbide region), n-type drift region 34 (first silicon carbide region), n-type bulk region 36 (second ... + The system comprises a source region 38 (third silicon carbide region) of type p, a resurf region 40 (fourth silicon carbide region) of type p, and a connection region 42 (fifth silicon carbide region) of type p. The drift region 34 includes a JFET region 34a (first region), a first JBS region 34b (second region), a second JBS region 34c (third region), and a lower region 34d. The bulk region 36 includes a low-concentration bulk region 36a and a high-concentration bulk region 36b. The resurf region 40 includes a low-concentration resurf region 40a and a high-concentration resurf region 40b.

[0047] Drift region 34 is an example of a first silicon carbide region. Body region 36 is an example of a second silicon carbide region. JFET region 34a is an example of a first region. First JBS region 34b is an example of a second region. Second JBS region 34c is an example of a third region. Source region 38 is an example of a third silicon carbide region. Surface field reduction region 40 is an example of a fourth silicon carbide region. Connector region 42 is an example of a fifth silicon carbide region.

[0048] like Figure 2As shown, component region 101 includes multiple MOSFET regions and multiple SBD regions. The MOSFET regions contain transistors Tr. The SBD regions contain first diodes D1. Component region 101 includes a first contact C1. For example, as... Figure 1A As shown, the component region 101 is divided into a first component region 101a and a second component region 101b.

[0049] The MOSFET region extends in the first direction. The MOSFET region is repeated in the second direction.

[0050] The SBD region extends in the first direction. The SBD region is repeated in the second direction. Two MOSFET regions are disposed between adjacent SBD regions in the second direction. In MOSFET100, the ratio of MOSFET region to SBD region is 2:1.

[0051] The ratio of the MOSFET region to the SBD region is not limited to 2:1. For example, it can also be 1:1, 3:1, or other ratios.

[0052] like Figure 1B and Figure 2 As shown, the device region 101 includes a silicon carbide layer 10, a first source electrode 12a (first electrode), a second source electrode 12b, a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 28.

[0053] A silicon carbide layer 10 is disposed between the source electrode 12 and the drain electrode 14 in the device region 101. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0054] The silicon carbide layer 10 has a first surface ( Figure 2 (P1) and the second side ( Figure 2 (P2 in the original text). Hereinafter, the first surface P1 will sometimes be referred to as the surface, and the second surface P2 as the back surface. The first surface P1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface P2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface P1 and the second surface P2 are opposite each other. In addition, hereafter, "depth" refers to the depth in the direction from the first surface toward the second surface.

[0055] The first surface is parallel to both the first and second directions. The second direction is perpendicular to the first direction.

[0056] The first surface P1 is, for example, a surface inclined at a degree greater than or equal to 0 degrees and less than or equal to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at a degree greater than or equal to 0 degrees and less than or equal to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0057] The thickness of silicon carbide layer 10 ( Figure 2 The t in the example is 5μm or more and 150μm or less.

[0058] like Figure 2 As shown, the silicon carbide layer 10 of the component region 101 contains n + Type 32, n drain region － Type 34 drift region (first silicon carbide region), p-type bulk region 36 (second silicon carbide region), n-type drift region 34 (first silicon carbide region), n-type bulk region 36 (second ... + The source region 38 (third silicon carbide region) is of the type. The drift region 34 has a JFET region 34a (first region), a first JBS region 34b (second region), and a lower region 34d. The bulk region 36 has a low-concentration bulk region 36a and a high-concentration bulk region 36b.

[0059] n + A drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 32 may be, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0060] n － The drift region 34 is located between the drain region 32 and the first surface P1. + A drift region 34 is disposed between the source electrode 12 and the drain electrode 14. － A drift region 34 is disposed between the gate electrode 18 and the drain electrode 14.

[0061] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34, for example, contains nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 34 is lower than that in the drain region 32. The n-type impurity concentration in the drift region 34 is, for example, 4 × 10⁻⁶. 14 cm -3 Above and 1×10 17 cm -3 The thickness of the drift region 34 is, for example, 5 μm or more and 150 μm or less.

[0062] n － The drift region 34 has a JFET region 34a, a first JBS region 34b, and a lower region 34d.

[0063] JFET region 34a is disposed between lower region 34d and first surface P1. JFET region 34a is in contact with first surface P1. JFET region 34a is disposed between two adjacent individual regions 36.

[0064] JFET region 34a extends in a first direction. JFET region 34a is opposite to gate electrode 18 across gate insulating layer 16.

[0065] JFET region 34a functions as a current path for MOSFET 100. The n-type impurity concentration in JFET region 34a is, for example, higher than that in the lower region 34d. The n-type impurity concentration in JFET region 34a is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0066] The first JBS region 34b is located between the lower region 34d and the first surface P1. The first JBS region 34b is in contact with the first surface P1. The first JBS region 34b is located between two adjacent individual regions 36.

[0067] The first JBS region 34b extends in the first direction. The first JBS region 34b is in contact with the source electrode 12.

[0068] The first diode D1 is an SBD. The n-type impurity concentration in the first JBS region 34b is, for example, higher than the n-type impurity concentration in the lower region 34d. The n-type impurity concentration in the first JBS region 34b is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0069] A p-type body region 36 is disposed between the drift region 34 and the first surface P1. The body region 36 extends in a first direction. The body region 36 functions as the channel region of the MOSFET 100. The body region 36 also functions as the channel region of the transistor Tr.

[0070] The depth of the volume region 36 is, for example, greater than 0.5 μm and less than 1.0 μm.

[0071] Body region 36 is electrically connected to source electrode 12. Body region 36 is fixed to the potential of source electrode 12.

[0072] A portion of body region 36 contacts the first surface P1. A portion of body region 36 is opposite to the gate electrode 18. A portion of body region 36 forms the channel region of MOSFET 100. Gate insulating layer 16 is sandwiched between a portion of body region 36 and gate electrode 18.

[0073] Body region 36 is adjacent to JFET region 34a. Body region 36 is in contact with JFET region 34a.

[0074] The body region 36 has a low-concentration body region 36a and a high-concentration body region 36b. The high-concentration body region 36b is disposed between the low-concentration body region 36a and the source electrode 12. The high-concentration body region 36b is in contact with the source electrode 12.

[0075] Body region 36, for example, contains aluminum (Al) as a p-type impurity. The concentration of p-type impurities in low-concentration body region 36a is lower than that in high-concentration body region 36b. The concentration of p-type impurities in low-concentration body region 36a is, for example, 5 × 10⁻⁶. 17 cm -3 Above and 5×10 19 cm -3 The concentration of p-type impurities in the high-concentration region 36b is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0076] Body region 36 is electrically connected to source electrode 12. Body region 36 is electrically connected to source electrode 12 via first contact portion C1. The contact between body region 36 and source electrode 12 is, for example, an ohmic contact. Body region 36 is fixed to the potential of source electrode 12.

[0077] n + The source region 38 is disposed between the bulk region 36 and the first surface P1. The source region 38 extends in the first direction.

[0078] Source region 38 may contain phosphorus (P) or nitrogen (N) as an n-type impurity, for example. The concentration of n-type impurities in source region 38 is higher than that in drift region 34.

[0079] The n-type impurity concentration in source region 38 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 The depth of the source region 38 is shallower than the depth of the bulk region 36. The depth of the source region 38 is, for example, 0.05 μm or more and 0.2 μm or less.

[0080] Source region 38 is in contact with source electrode 12. Source region 38 is electrically connected to source electrode 12. Source region 38 is electrically connected to source electrode 12 through contact portion C1. The contact between source region 38 and source electrode 12 is, for example, an ohmic contact. Source region 38 is fixed to the potential of source electrode 12.

[0081] A gate electrode 18 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. A plurality of gate electrodes 18 are arranged parallel to each other in a second direction. The gate electrode 18 has a stripe shape.

[0082] Gate electrode 18 is a conductive layer. Gate electrode 18 is, for example, polysilicon containing p-type or n-type impurities.

[0083] Gate electrode 18 is opposite to body region 36. Gate electrode 18 is opposite to JFET region 34a.

[0084] A gate insulating layer 16 is disposed between the gate electrode 18 and the body region 36. A gate insulating layer 16 is disposed between the gate electrode 18 and the JFET region 34a. A gate insulating layer 16 is disposed between the gate electrode 18 and the source region 38.

[0085] The gate insulating layer 16 is, for example, silicon oxide. The gate insulating layer 16 can be made of, for example, a high-k insulating material (a high dielectric constant insulating material).

[0086] An interlayer insulating layer 28 is disposed on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 28 is, for example, silicon oxide.

[0087] The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the source region 38. The source electrode 12 is at the first interface ( Figure 2 The source electrode 12 contacts the bulk region 36 at point K1 in the first interface. Figure 2 At interface K1, the source electrode 12 is in contact with the high-concentration bulk region 36b. The source electrode 12 is in contact with the source region 38 at the first interface K1. The source electrode 12 is in contact with the first JBS region 34b.

[0088] The source electrode 12, for example, has a silicide layer 12x and a metal layer 12y. The silicide layer 12x is disposed between the silicon carbide layer 10 and the metal layer 12y. The silicide layer 12x extends in a first direction.

[0089] The silicide layer 12x is in contact with the source region 38. The silicide layer 12x is in contact with the bulk region 36. The silicide layer 12x is in contact with the high-concentration bulk region 36b.

[0090] The source electrode 12 functions as the anode of the first diode D1.

[0091] The silicide layer 12x of the source electrode 12 contains silicide. The silicide layer 12x is, for example, a nickel silicide or a titanium silicide.

[0092] The contact between the source electrode 12 and the source region 38 is made ohmic by providing a silicide layer 12x. The contact between the source electrode 12 and the bulk region 36 is made ohmic by providing a silicide layer 12x. The contact between the source electrode 12 and the high-concentration bulk region 36b is made ohmic by providing a silicide layer 12x.

[0093] The metal layer 12y of the source electrode 12 contains metal. The metal layer 12y is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0094] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0095] The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 may contain at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0096] like Figure 2 As shown, transistor Tr includes a gate electrode 18, a gate insulating layer 16, a JFET region 34a, a body region 36, a source region 38, a source electrode 12, and a drain electrode 14. When MOSFET 100 is in the ON state, current flows from the source electrode 14 to the source electrode 12 through transistor Tr.

[0097] like Figure 2 As shown, the first diode D1 includes a source electrode 12, a first JBS region 34b, and a drain electrode 14. When a forward bias voltage is applied to the first diode D1, current flows from the source electrode 12 to the drain electrode 14.

[0098] like Figure 2 As shown, the first contact portion C1 includes a source electrode 12, a first interface K1, and a bulk region 36. The first contact portion C1 includes a high-concentration bulk region 36b. The first contact portion C1 includes a source region 38.

[0099] Through the first contact portion C1, the potential of the body region 36 is fixed to the potential of the source electrode 12. By setting the first contact portion C1, the potential of the body region 36 is stabilized, and the operation of the MOSFET 100 is stable.

[0100] like Figure 1A As shown, the termination region 102 surrounds the element region 101. The termination region 102 includes a second contact C2 and a second diode D2. The termination region 102 has the following function: when the MOSFET 100 is in the off state, it reduces the intensity of the electric field applied to the termination portion of the pn junction of the element region 101, thereby improving the insulation breakdown voltage of the MOSFET 100.

[0101] like Figure 1B , Figure 4 and Figure 5 As shown, the terminal region 102 includes a silicon carbide layer 10, a source wiring layer 20, a drain electrode 14 (second electrode), an interlayer insulating layer 28, and a field insulating layer 30.

[0102] The silicon carbide layer 10 of the terminal region 102 is disposed between the source wiring layer 20 and the drain electrode 14.

[0103] like Figure 4 As shown, the silicon carbide layer 10 of the terminal region 102 contains n + Type 32, n drain region + The system includes a p-type drift region 34 (first silicon carbide region) and a p-type reduced surface electric field region 40 (fourth silicon carbide region). The drift region 34 has a second JBS region 34c (third region) and a lower region 34d. The reduced surface electric field region 40 has a low-concentration reduced surface electric field region 40a and a high-concentration reduced surface electric field region 40b.

[0104] n + The drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity.

[0105] n － The drift region 34 is located between the drain region 32 and the first surface P1. － A drift region 34 is disposed between the source wiring layer 20 and the drain electrode 14.

[0106] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34 may contain nitrogen (N) as an n-type impurity.

[0107] n － The drift region 34 of the type has a second JBS region 34c and a lower region 34d.

[0108] The second JBS region 34c is disposed between the lower region 34d and the first surface P1. The second JBS region 34c is in contact with the first surface P1. The second JBS region 34c is disposed between two adjacent reduced surface electric field regions 40. The second JBS region 34c is in contact with the source wiring layer 20.

[0109] The second diode D2 is an SBD. The n-type impurity concentration in the second JBS region 34c is, for example, higher than the n-type impurity concentration in the lower region 34d. The n-type impurity concentration in the second JBS region 34c is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0110] A p-type surface electric field reduction region 40 is disposed between the drift region 34 and the first surface P1. The depth of the surface electric field reduction region 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0111] The reduced surface electric field region 40 is electrically connected to the source wiring layer 20. The reduced surface electric field region 40 is electrically connected to the source wiring layer 20 via a first contact portion C1. The contact between the reduced surface electric field region 40 and the source wiring layer 20 is, for example, an ohmic contact. The reduced surface electric field region 40 is fixed to the potential of the source wiring layer 20.

[0112] The surface electric field reduction region 40 has a low-concentration surface electric field reduction region 40a and a high-concentration surface electric field reduction region 40b. The high-concentration surface electric field reduction region 40b is disposed between the low-concentration surface electric field reduction region 40a and the source wiring layer 20. The high-concentration surface electric field reduction region 40b is in contact with the source wiring layer 20.

[0113] The surface electric field reduction region 40 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the low-concentration surface electric field reduction region 40a is lower than that in the high-concentration surface electric field reduction region 40b. For example, the p-type impurity concentration in the low-concentration surface electric field reduction region 40a is 5 × 10⁻⁶. 17 cm -3 Above and 5×10 19 cm -3 The following describes the concentration of p-type impurities in the high-concentration region 40b that reduces the surface electric field, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0114] An interlayer insulating layer 28 is disposed on the field insulating layer 30. The interlayer insulating layer 28 is, for example, silicon oxide.

[0115] A field insulating layer 30 is disposed on the silicon carbide layer 10. The field insulating layer 30 is, for example, silicon oxide.

[0116] like Figure 1B As shown, the source wiring layer 20 surrounds the source electrode 12. The source wiring layer 20 is electrically connected to the source electrode 12.

[0117] The source wiring layer 20 has a first portion 20a, a second portion 20b, a third portion 20c, and a fourth portion 20d. The first portion 20a extends in a second direction. The second portion 20b extends in a second direction. The source electrode 12 is sandwiched between the first portion 20a and the second portion 20b. The third portion 20c extends in a first direction. The fourth portion 20d extends in a first direction. The source electrode 12 is sandwiched between the third portion 20c and the fourth portion 20d.

[0118] The source wiring layer 20 is in contact with the silicon carbide layer 10. The source wiring layer 20 is located at the second interface ( Figure 4 At point K2, it contacts the surface electric field reduction region 40. The source wiring layer 20 is in contact with the second interface ( Figure 4 At point K2, there is contact with the high-concentration region 40b that reduces the surface electric field.

[0119] The source wiring layer 20 has, for example, a silicide layer 20x and a metal layer 20y. The silicide layer 20x is disposed between the silicon carbide layer 10 and the metal layer 20y.

[0120] The silicide layer 20x is in contact with the surface electric field reduction region 40. The silicide layer 20x is in contact with the high-concentration surface electric field reduction region 40b.

[0121] The source wiring layer 20 functions as the anode of the second diode D2.

[0122] The silicide layer 20x of the source wiring layer 20 contains silicide. The silicide layer 20x is, for example, a nickel silicide or a titanium silicide.

[0123] The contact between the source wiring layer 20 and the surface electric field reduction region 40 is made into an ohmic contact by providing a silicide layer 20x. The contact between the source wiring layer 20 and the high-concentration surface electric field reduction region 40b is made into an ohmic contact by providing a silicide layer 20x.

[0124] The metal layer 20y of the source wiring layer 20 contains metal. The metal layer 20y is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0125] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0126] like Figure 4 and Figure 5 As shown, the second diode D2 includes a source wiring layer 20, a second JBS region 34c, and a drain electrode 14. When a forward bias voltage is applied to the second diode D2, current flows from the source wiring layer 20 to the drain electrode 14.

[0127] like Figure 4 and Figure 5As shown, the second contact portion C2 includes a source wiring layer 20, a second interface K2, and a surface electric field reduction region 40. The second contact portion C2 includes a high-concentration surface electric field reduction region 40b.

[0128] Through the second contact portion C2, the potential of the reduced surface electric field region 40 is fixed to the potential of the source wiring layer 20. By providing the second contact portion C2, for example, the insulation breakdown withstand voltage of the MOSFET 100 is stabilized.

[0129] like Figure 1A As shown, the intermediate region 103 is disposed between the component region 101 and the terminal region 102. The intermediate region 103 surrounds the component region 101. The terminal region 102 surrounds the intermediate region 103.

[0130] The intermediate region 103 does not include transistor Tr, first diode D1, second diode D2, first contact C1, and second contact C2.

[0131] like Figure 1B , Figure 4 and Figure 5 As shown, the intermediate region 103 includes a silicon carbide layer 10, a first interconnect layer 22a (interconnection layer), a second interconnect layer 22b, a gate interconnect line 23, a gate electrode pad 24, a gate wiring layer 26, a drain electrode 14 (second electrode), an interlayer insulating layer 28, and a field insulating layer 30.

[0132] The silicon carbide layer 10 of the intermediate region 103 is disposed between the connection layer 22 and the drain electrode 14, between the gate wiring layer 26 and the drain electrode 14, and between the gate electrode pad 24 and the drain electrode 14.

[0133] like Figure 4 As shown, the silicon carbide layer 10 in the intermediate region 103 contains n + Type 32, n drain region － The drift region 34 (first silicon carbide region) of the p-type and the connection region 42 (fifth silicon carbide region) of the p-type.

[0134] n + The drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity.

[0135] n － The drift region 34 is located between the drain region 32 and the first surface P1. － A drift region 34 is disposed between the connecting layer 22 and the drain electrode 14.

[0136] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34 may contain nitrogen (N) as an n-type impurity.

[0137] n － The drift region 34 of the type has a lower region 34d.

[0138] The p-shaped connection region 42 is disposed between the drift region 34 and the first surface P1. The depth of the connection region 42 is, for example, more than 0.5 μm and less than 1.0 μm.

[0139] A connection region 42 is disposed between the body region 36 and the surface electric field reduction region 40. The connection region 42, for example, is in contact with the body region 36. The connection region 42, for example, is in contact with the surface electric field reduction region 40. The connection region 42, the body region 36, and the surface electric field reduction region 40 are, for example, continuous. The connection region 42, the body region 36, and the surface electric field reduction region 40 are, for example, formed simultaneously using the same manufacturing process.

[0140] Connection region 42 is electrically connected to source electrode 12, for example, via body region 36. Connection region 42 is electrically connected to source wiring layer 20, for example, via surface electric field reduction region 40.

[0141] Connection region 42 is fixed, for example, to the potential of source electrode 12. Connection region 42 is fixed, for example, to the potential of source wiring layer 20.

[0142] The connecting region 42 may contain aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the connecting region 42 may be, for example, 5 × 10⁻⁶. 17 cm -3 Above and 5×10 19 cm -3 the following.

[0143] An interlayer insulating layer 28 is disposed on the field insulating layer 30. The interlayer insulating layer 28 is, for example, silicon oxide.

[0144] A field insulating layer 30 is disposed on the silicon carbide layer 10. The field insulating layer 30 is, for example, silicon oxide.

[0145] A connection layer 22 is disposed on the first surface P1 side of the silicon carbide layer 10. The connection layer 22 is disposed between the source electrode 12 and the source wiring layer 20. The connection layer 22 is in contact with the source electrode 12. The connection layer 22 is in contact with the source wiring layer 20. The connection layer 22 is electrically connected to both the source electrode 12 and the source wiring layer 20.

[0146] For example, the first connection layer 22a is disposed between the first source electrode 12a and the fourth portion 20d of the source wiring layer 20. The first connection layer 22a is disposed in a second direction of the first source electrode 12a.

[0147] For example, the second connection layer 22b is disposed between the second source electrode 12b and the fourth portion 20d of the source wiring layer 20. The second connection layer 22b is disposed in a second direction of the second source electrode 12b.

[0148] The connecting layer 22 contains metal. The connecting layer 22 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0149] Gate electrode pad 24 is disposed on the first surface P1 side of silicon carbide layer 10. Gate electrode pad 24 contains metal. Gate electrode pad 24 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0150] The gate wiring layer 26 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate wiring layer 26 is connected to the gate electrode pad 24. The gate wiring layer 26 is electrically connected to the gate electrode pad 24.

[0151] The gate wiring layer 26 has a first line 26a, a second line 26b, and a third line 26c. A portion of the first line 26a extends in a second direction. A portion of the second line 26b extends in a second direction. The third line 26c extends in a second direction.

[0152] The first line 26a is disposed between the first portion 20a of the source wiring layer 20 and the first source electrode 12a. The second line 26b is disposed between the second portion 20b of the source wiring layer 20 and the second source electrode 12b. The third line 26c is disposed between the first source electrode 12a and the second source electrode 12b.

[0153] The gate electrode 18, located in the component region 101, is electrically connected to the gate electrode pad 24 via the gate connection line 23 and the gate wiring layer 26.

[0154] The gate wiring layer 26 contains metal. The gate wiring layer 26 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0155] For example, the source electrode 12, source wiring layer 20, interconnect layer 22, gate electrode pad 24, and gate wiring layer 26 may contain the same material. For example, the source electrode 12, source wiring layer 20, interconnect layer 22, gate electrode pad 24, and gate wiring layer 26 may contain titanium and aluminum. For example, the source electrode 12, source wiring layer 20, interconnect layer 22, gate electrode pad 24, and gate wiring layer 26 may be formed simultaneously using the same manufacturing process.

[0156] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0157] The width of the intermediate region 103 in the second direction from the component region 101 toward the terminal region 102 is more than twice the thickness of the silicon carbide layer 10. The width of the intermediate region 103 is, for example, the distance in the second direction between the first contact portion C1 and the second contact portion C2.

[0158] For example, the first width in a second direction from the component region 101 of the intermediate region 103, including the connection layer 22, toward the terminal region 102 ( Figure 4 w1 in the figure represents the thickness of silicon carbide layer 10. Figure 4 More than twice the value of t in the text. Additionally, for example, the second width (in the first direction from the element region 101 of the intermediate region 103, including the first line 26a of the gate wiring layer 26, toward the terminal region 102) is... Figure 5 w2 in the figure represents the thickness of silicon carbide layer 10. Figure 5 More than twice the value of t in the text.

[0159] For example, the first width w1 is greater than the second width w2. For example, the first width w1 is more than 1.2 times the second width w2.

[0160] Next, the function and effect of the MOSFET 100 in the first embodiment will be explained.

[0161] Figure 6 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment. In the MOSFET 100, a pn junction diode and an SBD are connected in parallel with the transistor as a built-in diode between the source electrode 12 and the drain electrode 14 in the element region 101. The body region 36 is the anode side of the pn junction diode, and the drift region 34 is the cathode side of the pn junction diode. In addition, the source electrode 12 is the anode of the SBD, and the drain electrode 14 is the cathode of the SBD.

[0162] For example, consider the case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, sometimes due to the induced current caused by the inductive load, a positive voltage is applied to the source electrode 12 relative to the drain electrode 14. In this case, forward current flows through the built-in diode. This state is also known as the reverse conduction state.

[0163] Assuming the MOSFET lacks a Switched Buffer (SBD), forward current flows through the pn junction diode. The pn junction diode operates bipolarly. If a bipolar-operated pn junction diode carries back current, stacking defects will grow in the silicon carbide layer due to carrier recombination energy. When stacking defects grow in the silicon carbide layer, it increases the MOSFET's on-resistance. This increased on-resistance leads to a decrease in MOSFET reliability.

[0164] The MOSFET100 features a forward bias diode (SBD). The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows through the SBD before the pn junction diode.

[0165] The forward voltage (Vf) of an SBD is, for example, above 1.0V and below 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, above 2.0V and below 3.0V.

[0166] The SBD operates unipolarly. Therefore, even with forward current flow, stacking defects will not grow in the silicon carbide layer 10 due to carrier recombination energy. Thus, the increase in the on-resistance of the MOSFET 100 is suppressed. Therefore, the reliability of the MOSFET 100 is improved.

[0167] A large surge voltage, with the source electrode 12 being positive, may be momentarily applied between the source electrode 12 and the drain electrode 14 of the MOSFET 100. When a large surge voltage is applied, a large surge current flows through the MOSFET 100, which may sometimes damage the MOSFET 100.

[0168] The maximum allowable peak surge current of a MOSFET is called its surge current withstand capability. In MOSFETs with SBD (Surge Difference) configuration, improving surge current withstand capability is desirable from a reliability perspective.

[0169] When a surge voltage is applied to MOSFET 100, a forward voltage is applied to the pn junction between drift region 34 and body region 36 in device region 101. When the voltage applied to the pn junction exceeds the forward voltage (Vf) of the pn junction diode, hole injection begins from the first contact C1 into drift region 34. Holes are injected from the first contact C1 into drift region 34 via body region 36.

[0170] When hole injection begins from the first contact C1 into the drift region 34, conductivity modulation occurs, causing the drift region 34 to become low-resistance. If the drift region 34 becomes low-resistance, a large forward current flows between the source electrode 12 and the drain electrode 14. In other words, a large surge current flows between the source electrode 12 and the drain electrode 14 through the bipolar operation of the pn junction diode.

[0171] A large surge current flows between the source electrode 12 and the drain electrode 14, causing the element region 101 to heat up. If thermal damage to the element region 101 occurs due to this heating, the MOSFET 100 will be damaged.

[0172] Figure 7 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 7This is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is a MOSFET900. Figure 7 It is the same as the first embodiment. Figure 4 The corresponding diagram.

[0173] The width of the comparative example MOSFET 900 in the direction from the device region 101 of the intermediate region 103 toward the terminal region 102 is ( Figure 7 The thickness of the silicon carbide layer 10 is less than the thickness of the wx in the middle. Figure 7 This differs from the MOSFET 100 of the first embodiment in that the t) is twice that of the MOSFET 100 in the first embodiment.

[0174] When a surge voltage is applied to the MOSFET900 of the comparative example, thermal damage sometimes occurs not in the device region 101, but in the termination region 102. Due to the thermal damage occurring in the termination region 102, the maximum permissible peak current value of the MOSFET900 decreases, and the surge current withstand capability deteriorates.

[0175] When a surge voltage is applied to the MOSFET 900 of the comparative example, a high voltage is applied between the source electrode 12 and the drain electrode 14 in the device region 101. On the other hand, a high voltage is applied between the source wiring layer 20 and the drain electrode 14 in the termination region 102.

[0176] When the surge voltage exceeds the forward voltage (Vf) of the pn junction diode in component region 101, hole injection begins from the first contact C1 into the drift region 34 of component region 101. Conversely, when the surge voltage exceeds the forward voltage (Vf) of the pn junction diode in terminal region 102, hole injection begins from the second contact C2 into the drift region 34 of terminal region 102.

[0177] Holes injected from the first contact portion C1 propagate as a diffusion current in the drift region 34 at a slope of 45 degrees relative to the first surface P1. Similarly, holes injected from the second contact portion C2 propagate as a diffusion current in the drift region 34 at a slope of 45 degrees relative to the first surface P1.

[0178] When the width wx of the intermediate region 103 is less than twice the thickness t of the silicon carbide layer 10, the diffusion current flowing from the first contact C1 and the diffusion current flowing from the second contact C2 intersect at the bottom of the silicon carbide layer 10. Twice the thickness t of the silicon carbide layer 10, i.e., 2t, is equivalent to 2t × tan45°.

[0179] In the region where the diffusion current flowing from the first contact C1 intersects with the diffusion current flowing from the second contact C2, conductivity modulation is enhanced, and the drift region 34 becomes even lower in resistance. If the drift region 34 becomes lower in resistance, the surge current flowing through the terminal region 102 increases. It is believed that by increasing the surge current flowing through the terminal region 102, heating of the terminal region 102 is promoted, and thermal damage in the terminal region 102 is more likely to occur.

[0180] Figure 8 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 8 Is with Figure 4 The corresponding diagram.

[0181] In the MOSFET 100 of the first embodiment, the width of the intermediate region 103 in the second direction from the element region 101 toward the terminal region 102 is more than twice the thickness of the silicon carbide layer 10. For example, as Figure 8 As shown, the first width (in the second direction from the component region 101 of the intermediate region 103, including the connecting layer 22, toward the terminal region 102) Figure 8 w1 in the figure represents the thickness of silicon carbide layer 10. Figure 8 More than twice the value of t in the text. Additionally, for example, the second width (in the first direction from the element region 101 of the intermediate region 103, including the first line 26a of the gate wiring layer 26, toward the terminal region 102) is... Figure 5 w2 in the figure represents the thickness of silicon carbide layer 10. Figure 5 More than twice the value of t in the text.

[0182] Since the width of the intermediate region 103 is more than twice the thickness of the silicon carbide layer 10, the diffusion current flowing from the first contact C1 and the diffusion current flowing from the second contact C2 do not cross at the bottom of the silicon carbide layer 10. Because the diffusion currents do not cross at the bottom of the silicon carbide layer 10, conductivity modulation is not promoted. Further low resistance reduction in the drift region 34 does not occur, and the surge current flowing in the termination region 102 is suppressed. Therefore, heat generation in the termination region 102 is suppressed, and thermal damage in the termination region 102 is suppressed. Therefore, compared to the MOSFET 900 of the comparative example, the surge current tolerance of the MOSFET 100 is improved.

[0183] From the viewpoint of improving the surge current withstand capability of MOSFET 100, the width of the intermediate region 103 in the second direction from the element region 101 toward the terminal region 102 is preferably 2.5 times or more the thickness of the silicon carbide layer 10, and more preferably 3 times or more.

[0184] From the viewpoint of improving the surge current withstand capability of MOSFET100, the first width of the middle region 103 in the second direction ( Figure 4 The width w1 in the middle region 103 is preferably greater than the second width in the first direction. Figure 5 (w2 in the text). In other words, the first width w1 of the intermediate region 103 in the direction perpendicular to the first direction in which the gate electrode 18 extends is preferably greater than the second width w2 of the intermediate region 103 in the direction parallel to the first direction in which the gate electrode 18 extends.

[0185] In a direction perpendicular to the first direction in which the gate electrode 18 extends, the first contact portion C1 of the gate electrode 18 closest to the intermediate region 103 faces the intermediate region 103. In a direction parallel to the first direction in which the gate electrode 18 extends, the first contact portion C1 at the end of the gate electrode 18 in the first direction faces the intermediate region 103. The first contact portion C1 at the end of the gate electrode 18 in the first direction exists only in the portion of the gate electrode 18 at the end in the first direction that faces the intermediate region 103. In other words, in a direction parallel to the first direction in which the gate electrode 18 extends, the first contact portion C1 facing the intermediate region 103 is spaced out by the arrangement spacing of the gate electrodes 18.

[0186] Therefore, in the direction perpendicular to the first direction in which the gate electrode 18 extends, the density of the first contact portion C1 opposite the intermediate region 103 is higher than in the direction parallel to the first direction in which the gate electrode 18 extends. Consequently, the diffusion current flowing from the first contact portion C1 is greater in the intermediate region 103 in the direction perpendicular to the first direction in which the gate electrode 18 extends than in the intermediate region 103 in the direction parallel to the first direction in which the gate electrode 18 extends. Therefore, in the direction perpendicular to the first direction in which the gate electrode 18 extends, conductivity modulation is promoted compared to the direction parallel to the first direction in which the gate electrode 18 extends, and the heating of the terminal region 102 is promoted.

[0187] By making the first width w1 of the intermediate region 103 in the direction perpendicular to the first direction in which the gate electrode 18 extends greater than the second width w2 of the intermediate region 103 in the direction parallel to the first direction in which the gate electrode 18 extends, heat generation in the terminal region 102 in the direction perpendicular to the first direction in which the gate electrode 18 extends is suppressed, and thermal damage in the terminal region 102 is suppressed. Therefore, the surge current tolerance of the MOSFET 100 is improved.

[0188] From the viewpoint of improving the surge current withstand capability of MOSFET100, the first width of the middle region 103 in the second direction ( Figure 4 The w1 in the middle region 103 is preferably the second width in the first direction. Figure 5The amount of w2) is more than 1.2 times, and more preferably more than 1.5 times.

[0189] If the width of the intermediate region 103 increases, the occupancy of the element region 101 of the MOSFET 100 decreases. If the occupancy of the element region 101 of the MOSFET 100 decreases, the on-state current of the MOSFET 100 decreases.

[0190] From the viewpoint of increasing the on-current of MOSFET 100, the width of the intermediate region 103 in the direction from element region 101 toward terminal region 102 is preferably 10 times or less than the thickness of silicon carbide layer 10, more preferably 5 times or less. For example, the second width in the first direction from element region 101 toward terminal region 102, including the first line 26a of gate wiring layer 26 (…). Figure 5 The thickness of the silicon carbide layer 10 is preferably w2). Figure 5 The width of the component region 101 (including the connecting layer 22) in the second direction toward the terminal region 102 is less than 10 times, more preferably less than 5 times. Additionally, for example, the width of the component region 101 in the second direction toward the terminal region 102 in the second direction is... Figure 4 The thickness of the silicon carbide layer 10 is preferably w1). Figure 4 The value of t in the figure is less than 10 times, more preferably less than 5 times.

[0191] The terminal region 102 preferably includes a second diode D2. By providing the second diode D2 in the terminal region 102, the initial voltage for hole injection from the second contact C2 into the drift region 34 increases. This increase in the initial voltage for hole injection from the second contact C2 into the drift region 34 suppresses conductivity modulation in the drift region 34 of the terminal region 102. Therefore, heat generation in the terminal region 102 is suppressed, and thermal damage in the terminal region 102 is prevented.

[0192] The source electrode 12, source wiring layer 20, interconnect layer 22, gate electrode pad 24, and gate wiring layer 26 preferably contain the same material. The source electrode 12, source wiring layer 20, interconnect layer 22, gate electrode pad 24, and gate wiring layer 26 can be formed simultaneously using the same manufacturing process. Therefore, the manufacturing cost of the MOSFET 100 can be reduced.

[0193] According to the first embodiment, a MOSFET with suppressed thermal damage and improved surge current tolerance in the terminal region is realized.

[0194] (Second Implementation)

[0195] The semiconductor device of the second embodiment differs from that of the first embodiment in that the terminal region does not include a second diode. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0196] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 9 It is the same as the first embodiment. Figure 4 The corresponding diagram.

[0197] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is, for example, a DIMOSFET whose body region and source region are formed by ion implantation. Furthermore, the semiconductor device of the second embodiment includes an SBD as a built-in diode.

[0198] like Figure 9 As shown, the terminal region 102 of MOSFET200 does not contain a second diode.

[0199] According to the second embodiment, similar to the first embodiment, a MOSFET in which thermal damage in the terminal region is suppressed and surge current tolerance is improved is realized.

[0200] (Third Implementation)

[0201] The semiconductor device according to the third embodiment includes: a component region including a transistor, a first diode, and a first contact portion; a termination region surrounding the component region and including a second contact portion; and an intermediate region disposed between the component region and the termination region, which does not include a transistor, a first diode, a first contact portion, and a second contact portion. The component region includes: a first electrode; a second electrode; a gate electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface on the second electrode side. The silicon carbide layer includes: a first silicon carbide region of a first conductivity type, having a first region contacting the first surface and opposite to the gate electrode, and a second region contacting the first surface and contacting the first electrode; a second silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, adjacent to the first region, opposite to the gate electrode, and contacting the first electrode at a first interface; and a third silicon carbide region of a first conductivity type, disposed between the second and third surfaces, adjacent to the first region, opposite to the gate electrode, and contacting the first electrode at a first interface; and a third silicon carbide region of a first conductivity type, disposed between the second and third surfaces. The device comprises: a silicon carbide region electrically connected to a first electrode and a first surface; a gate insulating layer disposed between a gate electrode and a second silicon carbide region and between a gate electrode and a first region; a terminal region comprising: a first electrode; a second electrode; and a silicon carbide layer comprising a first silicon carbide region and a fourth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface and in contact with the first electrode at a second interface; an intermediate region comprising: a first electrode; a second electrode; and a silicon carbide layer comprising a first silicon carbide region and a fifth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface; a transistor comprising a gate electrode, a gate insulating layer, a first region, a second silicon carbide region and a third silicon carbide region; a first diode comprising a first electrode and a second region; a first contact portion comprising a first interface; a second contact portion comprising a second interface; and the width of the intermediate region in the direction from the device region toward the terminal region being more than twice the thickness of the silicon carbide layer.

[0202] Figure 10A , Figure 10B This is a schematic top view of the semiconductor device according to the third embodiment. Figure 10A A layout pattern representing the component area, terminal area, and intermediate area. Figure 10B This indicates the layout pattern of the first electrode and the gate pad electrode.

[0203] Figure 11A , Figure 11B This is a schematic top view of the semiconductor device according to the third embodiment. Figure 11A A layout pattern representing the component area, terminal area, and intermediate area. Figure 11B This indicates the layout pattern of the gate electrode, gate wiring layer, and gate pad electrode.

[0204] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 12 yes Figure 10A , Figure 10B , Figure 11A , Figure 11B The AA' section is shown.

[0205] Figure 13 This is a schematic top view of the semiconductor device according to the third embodiment. Figure 13 Is with Figure 12 The corresponding top view. Figure 13 This indicates the layout pattern of the first side of the semiconductor layer. Figure 13 This indicates the state after the first electrode and the interlayer insulation layer have been removed.

[0206] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 14 yes Figure 10A , Figure 10B , Figure 11A , Figure 11B The BB' section is shown.

[0207] Figure 15 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 15 yes Figure 10A , Figure 10B , Figure 11A , Figure 11B The CC' section is shown.

[0208] The semiconductor device of the third embodiment is a planar gate type vertical MOSFET 300 using silicon carbide. The MOSFET 300 is, for example, a DIMOSFET whose body region and source region are formed by ion implantation. Furthermore, the semiconductor device of the third embodiment includes an SBD as a built-in diode.

[0209] The following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. The MOSFET400 is a longitudinal n-channel MOSFET with electrons as charge carriers.

[0210] The MOSFET 300 has a device region 101, a termination region 102 and an intermediate region 103.

[0211] Component region 101 includes multiple MOSFET regions and multiple SBD regions. MOSFET regions include transistors Tr. SBD regions include first diodes D1. Component region 101 includes a first contact C1. Termination region 102 includes a second contact C2 and a second diode D2.

[0212] The MOSFET300 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14, a gate insulating layer 16, a gate electrode 18, a gate electrode pad 24, a gate wiring layer 25, an interlayer insulating layer 28, and a field insulating layer 30.

[0213] Source electrode 12 is an example of the first electrode. Drain electrode 14 is an example of the second electrode.

[0214] The silicon carbide layer 10 contains n + Type 32, n drain region － Type 34 drift region (first silicon carbide region), p-type bulk region 36 (second silicon carbide region), n-type drift region 34 (first silicon carbide region), n-type bulk region 36 (second ... + The system comprises a source region 38 (third silicon carbide region) of type p, a surface-field-reducing region 40 (fourth silicon carbide region) of type p, and a connection region 42 (fifth silicon carbide region) of type p. The drift region 34 includes a JFET region 34a (first region), a first JBS region 34b (second region), a second JBS region 34c (third region), and a lower region 34d. The bulk region 36 includes a low-concentration bulk region 36a and a high-concentration bulk region 36b. The surface-field-reducing region 40 includes a low-concentration surface-field-reducing region 40a and a high-concentration surface-field-reducing region 40b.

[0215] Drift region 34 is an example of a first silicon carbide region. Body region 36 is an example of a second silicon carbide region. JFET region 34a is an example of a first region. First JBS region 34b is an example of a second region. Second JBS region 34c is an example of a third region. Source region 38 is an example of a third silicon carbide region. Surface field reduction region 40 is an example of a fourth silicon carbide region. Connector region 42 is an example of a fifth silicon carbide region.

[0216] like Figure 12 As shown, component region 101 includes multiple MOSFET regions and multiple SBD regions. The MOSFET regions contain transistors Tr. The SBD regions contain first diodes D1.

[0217] The MOSFET region extends in the first direction. The MOSFET region is repeated in the second direction.

[0218] The SBD region extends in the first direction. The SBD region is repeated in the second direction. Two MOSFET regions are disposed between adjacent SBD regions in the second direction. In MOSFET300, the ratio of MOSFET region to SBD region is 2:1.

[0219] The ratio of the MOSFET region to the SBD region is not limited to 2:1. For example, it can also be 1:1, 3:1, or other ratios.

[0220] like Figure 10B , Figure 11B and Figure 12 As shown, the device region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 28.

[0221] A silicon carbide layer 10 in the device region 101 is disposed between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0222] The silicon carbide layer 10 has a first surface ( Figure 12 (P1) and the second side ( Figure 12 (P2 in the original text). Hereinafter, the first surface P1 will sometimes be referred to as the surface, and the second surface P2 as the back surface. The first surface P1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface P2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface P1 and the second surface P2 are opposite each other. In addition, hereafter, "depth" refers to the depth in the direction from the first surface toward the second surface.

[0223] The first surface is parallel to both the first and second directions. The second direction is perpendicular to the first direction.

[0224] The first surface P1 is, for example, a surface inclined at a degree greater than or equal to 0 degrees and less than or equal to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at a degree greater than or equal to 0 degrees and less than or equal to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0225] The thickness of the silicon carbide layer 10 is, for example, 5 μm or more and 150 μm or less.

[0226] like Figure 12 As shown, the silicon carbide layer 10 of the component region 101 contains n + Type 32, n drain region － Type 34 drift region (first silicon carbide region), p-type bulk region 36 (second silicon carbide region), n-type drift region 34 (first silicon carbide region), n-type bulk region 36 (second ... + The source region 38 (third silicon carbide region) is of the type. The drift region 34 has a JFET region 34a (first region), a first JBS region 34b (second region), and a lower region 34d. The bulk region 36 has a low-concentration bulk region 36a and a high-concentration bulk region 36b.

[0227] n + A drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 32 may be, for example, 1 × 10⁻⁶.18 cm -3 Above and 1×10 21 cm -3 the following.

[0228] n － The drift region 34 is located between the drain region 32 and the first surface P1. － A drift region 34 is disposed between the source electrode 12 and the drain electrode 14. － A drift region 34 is disposed between the gate electrode 18 and the drain electrode 14.

[0229] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34, for example, contains nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 34 is lower than that in the drain region 32. The n-type impurity concentration in the drift region 34 is, for example, 4 × 10⁻⁶. 14 cm -3 Above and 1×10 17 cm -3 The thickness of the drift region 34 is, for example, 5 μm or more and 150 μm or less.

[0230] n － The drift region 34 has a JFET region 34a, a first JBS region 34b, and a lower region 34d.

[0231] JFET region 34a is disposed between lower region 34d and first surface P1. JFET region 34a is in contact with first surface P1. JFET region 34a is disposed between two adjacent individual regions 36.

[0232] JFET region 34a extends in a first direction. JFET region 34a is opposite to gate electrode 18 across gate insulating layer 16.

[0233] JFET region 34a functions as a current path for MOSFET 300. The n-type impurity concentration in JFET region 34a is, for example, higher than that in the lower region 34d. The n-type impurity concentration in JFET region 34a is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0234] The first JBS region 34b is located between the lower region 34d and the first surface P1. The first JBS region 34b is in contact with the first surface P1. The first JBS region 34b is located between two adjacent individual regions 36.

[0235] The first JBS region 34b extends in the first direction. The first JBS region 34b is in contact with the source electrode 12.

[0236] The first diode D1 is an SBD. The n-type impurity concentration in the first JBS region 34b is, for example, higher than the n-type impurity concentration in the lower region 34d. The n-type impurity concentration in the first JBS region 34b is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0237] A p-type body region 36 is disposed between the drift region 34 and the first surface P1. The body region 36 extends in a first direction. The body region 36 functions as the channel region of the MOSFET 300. The body region 36 also functions as the channel region of the transistor Tr.

[0238] The depth of the volume region 36 is, for example, greater than 0.5 μm and less than 1.0 μm.

[0239] Body region 36 is electrically connected to source electrode 12. Body region 36 is fixed to the potential of source electrode 12.

[0240] A portion of body region 36 contacts the first surface P1. A portion of body region 36 is opposite to the gate electrode 18. A portion of body region 36 forms the channel region of MOSFET 300. Gate insulating layer 16 is sandwiched between a portion of body region 36 and gate electrode 18.

[0241] Body region 36 is adjacent to JFET region 34a. Body region 36 is in contact with JFET region 34a.

[0242] The body region 36 has a low-concentration body region 36a and a high-concentration body region 36b. The high-concentration body region 36b is disposed between the low-concentration body region 36a and the source electrode 12. The high-concentration body region 36b is in contact with the source electrode 12.

[0243] Body region 36, for example, contains aluminum (Al) as a p-type impurity. The concentration of p-type impurities in low-concentration body region 36a is lower than that in high-concentration body region 36b. The concentration of p-type impurities in low-concentration body region 36a is, for example, 5 × 10⁻⁶. 17 cm -3 Above and 5×10 19 cm -3 The concentration of p-type impurities in the high-concentration region 36b is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0244] Body region 36 is electrically connected to source electrode 12. The contact between body region 36 and source electrode 12 is, for example, an ohmic contact. Body region 36 is fixed to the potential of source electrode 12.

[0245] n + The source region 38 is disposed between the bulk region 36 and the first surface P1. The source region 38 extends in the first direction.

[0246] Source region 38 may contain phosphorus (P) or nitrogen (N) as an n-type impurity, for example. The concentration of n-type impurities in source region 38 is higher than that in drift region 34.

[0247] The n-type impurity concentration in source region 38 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 The depth of the source region 38 is shallower than the depth of the bulk region 36. The depth of the source region 38 is, for example, 0.05 μm or more and 0.2 μm or less.

[0248] Source region 38 is in contact with source electrode 12. Source region 38 is electrically connected to source electrode 12. The contact between source region 38 and source electrode 12 is, for example, an ohmic contact. Source region 38 is fixed to the potential of source electrode 12.

[0249] A gate electrode 18 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. A plurality of gate electrodes 18 are arranged parallel to each other in a second direction. The gate electrode 18 has a stripe shape.

[0250] Gate electrode 18 is a conductive layer. Gate electrode 18 is, for example, polysilicon containing p-type or n-type impurities.

[0251] Gate electrode 18 is opposite to body region 36. Gate electrode 18 is opposite to JFET region 34a.

[0252] A gate insulating layer 16 is disposed between the gate electrode 18 and the body region 36. A gate insulating layer 16 is disposed between the gate electrode 18 and the JFET region 34a. A gate insulating layer 16 is disposed between the gate electrode 18 and the source region 38.

[0253] The gate insulating layer 16 is, for example, silicon oxide. The gate insulating layer 16 can be made of, for example, a high-k insulating material (a high dielectric constant insulating material).

[0254] An interlayer insulating layer 28 is disposed on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 28 is, for example, silicon oxide.

[0255] The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the source region 38. The source electrode 12 is at the first interface ( Figure 12 The source electrode 12 contacts the bulk region 36 at point K1 in the first interface. Figure 12 At interface K1, the source electrode 12 is in contact with the high-concentration bulk region 36b. The source electrode 12 is in contact with the source region 38 at the first interface K1. The source electrode 12 is in contact with the first JBS region 34b.

[0256] Source electrode 12 is in contact with silicon carbide layer 10. Source electrode 12 is in contact with source region 38. Source electrode 12 is in contact with bulk region 36. Source electrode 12 is in contact with high-concentration bulk region 36b. Source electrode 12 is in contact with first JBS region 34b.

[0257] The source electrode 12, for example, has a silicide layer 12x and a metal layer 12y. The silicide layer 12x is disposed between the silicon carbide layer 10 and the metal layer 12y. The silicide layer 12x extends in a first direction.

[0258] The silicide layer 12x is in contact with the source region 38. The silicide layer 12x is in contact with the bulk region 36. The silicide layer 12x is in contact with the high-concentration bulk region 36b.

[0259] The source electrode 12 functions as the anode of the first diode D1.

[0260] The silicide layer 12x of the source electrode 12 contains silicide. The silicide layer 12x is, for example, a nickel silicide or a titanium silicide.

[0261] The contact between the source electrode 12 and the source region 38 is made ohmic by providing a silicide layer 12x. The contact between the source electrode 12 and the bulk region 36 is made ohmic by providing a silicide layer 12x. The contact between the source electrode 12 and the high-concentration bulk region 36b is made ohmic by providing a silicide layer 12x.

[0262] The metal layer 12y of the source electrode 12 contains metal. The metal layer 12y is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0263] The metal layer 12y is in contact with the first JBS region 34b. The contact between the source electrode 12 and the first JBS region 34b is a Schottky contact.

[0264] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0265] The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 may contain at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0266] like Figure 12 As shown, transistor Tr includes a gate electrode 18, a gate insulating layer 16, a JFET region 34a, a body region 36, a source region 38, a source electrode 12, and a drain electrode 14. When MOSFET 300 is in the ON state, current flows from the source electrode 14 to the source electrode 12 through transistor Tr.

[0267] like Figure 12 As shown, the first diode D1 includes a source electrode 12, a first JBS region 34b, and a drain electrode 14. When a forward bias voltage is applied to the first diode D1, current flows from the source electrode 12 to the drain electrode 14.

[0268] like Figure 12 As shown, the first contact portion C1 includes a source electrode 12, a first interface K1, and a bulk region 36. The first contact portion C1 includes a high-concentration bulk region 36b. The first contact portion C1 includes a source region 38.

[0269] Through the first contact portion C1, the potential of the body region 36 is fixed to the potential of the source electrode 12. By setting the first contact portion C1, the potential of the body region 36 is stabilized, and the operation of the MOSFET 300 is stable.

[0270] like Figure 10A As shown, the termination region 102 surrounds the element region 101. The termination region 102 includes a second diode D2. The termination region 102 has the following function: when the MOSFET 300 is in the off state, it reduces the intensity of the electric field applied to the termination portion of the pn junction of the element region 101, thereby improving the insulation breakdown voltage of the MOSFET 300.

[0271] like Figure 10B , Figure 14 and Figure 15 As shown, the terminal region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), an interlayer insulating layer 28, and a field insulating layer 30.

[0272] The silicon carbide layer 10 of the terminal region 102 is disposed between the source electrode 12 and the drain electrode 14.

[0273] like Figure 14 and Figure 15 As shown, the silicon carbide layer 10 of the terminal region 102 contains n + Type 32, n drain region －The system includes a p-type drift region 34 (first silicon carbide region) and a p-type reduced surface electric field region 40 (fourth silicon carbide region). The drift region 34 has a second JBS region 34c (third region) and a lower region 34d. The reduced surface electric field region 40 has a low-concentration reduced surface electric field region 40a and a high-concentration reduced surface electric field region 40b.

[0274] n + The drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity.

[0275] n － The drift region 34 is located between the drain region 32 and the first surface P1. － A drift region 34 is disposed between the source electrode 12 and the drain electrode 14.

[0276] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34 may contain nitrogen (N) as an n-type impurity.

[0277] n － The drift region 34 of the type has a second JBS region 34c and a lower region 34d.

[0278] The second JBS region 34c is disposed between the lower region 34d and the first surface P1. The second JBS region 34c is in contact with the first surface P1. The second JBS region 34c is disposed between two adjacent reduced surface electric field regions 40. The second JBS region 34c is in contact with the source electrode 12.

[0279] The second diode D2 is an SBD. The n-type impurity concentration in the second JBS region 34c is, for example, higher than the n-type impurity concentration in the lower region 34d. The n-type impurity concentration in the second JBS region 34c is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 2×10 17 cm -3 the following.

[0280] A p-type surface electric field reduction region 40 is disposed between the drift region 34 and the first surface P1. The depth of the surface electric field reduction region 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0281] The reduced surface electric field region 40 is electrically connected to the source electrode 12. The contact between the reduced surface electric field region 40 and the source electrode 12 is, for example, an ohmic contact. The reduced surface electric field region 40 is fixed to the potential of the source electrode 12.

[0282] The surface electric field reduction region 40 has a low-concentration surface electric field reduction region 40a and a high-concentration surface electric field reduction region 40b. The high-concentration surface electric field reduction region 40b is disposed between the low-concentration surface electric field reduction region 40a and the source electrode 12. The high-concentration surface electric field reduction region 40b is in contact with the source electrode 12.

[0283] The surface electric field reduction region 40 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the low-concentration surface electric field reduction region 40a is lower than that in the high-concentration surface electric field reduction region 40b. For example, the p-type impurity concentration in the low-concentration surface electric field reduction region 40a is 5 × 10⁻⁶. 17 cm -3 Above and 5×10 19 cm -3 The following describes the concentration of p-type impurities in the high-concentration region 40b that reduces the surface electric field, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0284] An interlayer insulating layer 28 is disposed on the field insulating layer 30. The interlayer insulating layer 28 is, for example, silicon oxide.

[0285] A field insulating layer 30 is disposed on the silicon carbide layer 10. The field insulating layer 30 is, for example, silicon oxide.

[0286] The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is located at the second interface ( Figure 14 At point K2, it contacts the region 40 that reduces the surface electric field. The source electrode 12 is located at the second interface (…). Figure 14 At point K2, there is contact with the high-concentration region 40b that reduces the surface electric field.

[0287] The source electrode 12 has, for example, a silicide layer 12x and a metal layer 12y. The silicide layer 12x is disposed between the silicon carbide layer 10 and the metal layer 12y.

[0288] The silicide layer 12x is in contact with the surface electric field reduction region 40. The silicide layer 12x is in contact with the high-concentration surface electric field reduction region 40b.

[0289] The source electrode 12 functions as the anode of the second diode D2.

[0290] The silicide layer 12x of the source electrode 12 contains silicide. The silicide layer 12x is, for example, a nickel silicide or a titanium silicide.

[0291] The contact between the source electrode 12 and the reduced surface electric field region 40 is made into an ohmic contact by providing a silicide layer 12x. The contact between the source electrode 12 and the high-concentration reduced surface electric field region 40b is made into an ohmic contact by providing a silicide layer 12x.

[0292] The metal layer 12y of the source electrode 12 contains metal. The metal layer 12y is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0293] Metal layer 12y contacts the second JBS region 34c. The contact between source electrode 12 and the first JBS region 34b is a Schottky contact. The contact between metal layer 12y and the second JBS region 34c is a Schottky contact.

[0294] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0295] like Figure 14 and Figure 15 As shown, the second diode D2 includes a source electrode 12, a second JBS region 34c, and a drain electrode 14. When a forward bias voltage is applied to the second diode D2, current flows from the source electrode 12 to the drain electrode 14.

[0296] like Figure 14 and Figure 15 As shown, the second contact portion C2 includes a source electrode 12, a second interface K2, and a surface electric field reduction region 40. The second contact portion C2 includes a high-concentration surface electric field reduction region 40b.

[0297] Through the second contact portion C2, the potential of the reduced surface electric field region 40 is fixed to the potential of the source wiring layer 20. By providing the second contact portion C2, for example, the insulation breakdown voltage of the MOSFET 300 is stabilized.

[0298] like Figure 10A As shown, the intermediate region 103 is disposed between the component region 101 and the terminal region 102. The intermediate region 103 surrounds the component region 101. The terminal region 102 surrounds the intermediate region 103.

[0299] The intermediate region 103 does not include transistor Tr, first diode D1, second diode D2, first contact C1, and second contact C2.

[0300] like Figure 10B , Figure 11B , Figure 14 and Figure 15 As shown, the intermediate region 103 includes a silicon carbide layer 10, a source electrode 12, a gate electrode pad 24, a gate wiring layer 25, a drain electrode 14 (second electrode), an interlayer insulating layer 28, and a field insulating layer 30.

[0301] The silicon carbide layer 10 in the intermediate region 103 is disposed between the source electrode 12 and the drain electrode 14, and between the gate electrode pad 24 and the drain electrode 14.

[0302] like Figure 14 and Figure 15 As shown, the silicon carbide layer 10 in the intermediate region 103 contains n + Type 32, n drain region － The drift region 34 (first silicon carbide region) of the p-type and the connection region 42 (fifth silicon carbide region) of the p-type.

[0303] n + The drain region 32 is disposed on the back side of the silicon carbide layer 10. The drain region 32 may contain nitrogen (N) as an n-type impurity.

[0304] n － The drift region 34 is located between the drain region 32 and the first surface P1. － A drift region 34 is disposed between the source electrode 12 and the drain electrode 14.

[0305] n － A type-n drift region 34 is disposed on the drain region 32. The drift region 34 may contain nitrogen (N) as an n-type impurity.

[0306] n － The drift region 34 of the type has a lower region 34d.

[0307] The p-shaped connection region 42 is disposed between the drift region 34 and the first surface P1. The depth of the connection region 42 is, for example, more than 0.5 μm and less than 1.0 μm.

[0308] A connection region 42 is disposed between the body region 36 and the surface electric field reduction region 40. The connection region 42, for example, is in contact with the body region 36. The connection region 42, for example, is in contact with the surface electric field reduction region 40. The connection region 42, the body region 36, and the surface electric field reduction region 40 are, for example, continuous. The connection region 42, the body region 36, and the surface electric field reduction region 40 are, for example, formed simultaneously using the same manufacturing process.

[0309] Connection region 42 is electrically connected to source electrode 12, for example, via body region 36. Connection region 42 is electrically connected to source electrode 12, for example, via surface electric field reduction region 40. Connection region 42 is, for example, fixed to the potential of source electrode 12.

[0310] The connecting region 42 may contain aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the connecting region 42 may be, for example, 5 × 10⁻⁶. 17 cm -3Above and 5×10 19 cm -3 the following.

[0311] A gate wiring layer 25 is disposed between the source electrode 12 and the silicon carbide layer 10. The gate wiring layer 25 is electrically connected to the gate electrode pad 24. The gate wiring layer 25 is electrically connected to the gate electrode 18. For example, the gate wiring layer 25 is in contact with the gate electrode 18.

[0312] The gate wiring layer 25 includes a first gate line 25a extending in a second direction and a second gate line 25b extending in a second direction. The gate electrode 18 is sandwiched between the first gate line 25a and the second gate line 25b.

[0313] Gate wiring layer 25 is a conductive layer. Gate wiring layer 25 is, for example, polysilicon containing p-type or n-type impurities. Gate wiring layer 25 is, for example, a stacked structure of polysilicon containing p-type or n-type impurities and silicide.

[0314] The resistance per unit length of the gate wiring layer 25 in the second direction is, for example, lower than the resistance per unit length of the gate electrode 18 in the first direction. The unit length is, for example, any length between 1 μm and 100 μm.

[0315] For example, the resistance per unit length of the first gate line 25a in the second direction is lower than the resistance per unit length of the gate electrode 18 in the first direction. Additionally, for example, the resistance per unit length of the second gate line 25b in the second direction is lower than the resistance per unit length of the gate electrode 18 in the first direction.

[0316] For example, the width of the gate wiring layer 25 in the first direction is more than 20 times and less than 100 times the width of the gate electrode 18 in the second direction. For example, the width of the first gate line 25a in the first direction ( Figure 11B w1x) is the width of the gate electrode 18 in the second direction ( Figure 11B More than 20 times and less than 100 times that of w2). For example, the width of the second gate line 25b in the first direction ( Figure 11B w2x) is the width of the gate electrode 18 in the second direction ( Figure 11B More than 20 times and less than 100 times that of w2).

[0317] By setting the width of the gate wiring layer 25 in the first direction to be more than 20 times the width of the gate electrode 18 in the second direction, the resistance per unit length of the gate wiring layer 25 in the second direction becomes lower than the resistance per unit length of the gate electrode 18 in the first direction.

[0318] For example, the surface resistance of the gate wiring layer 25 is lower than the surface resistance of the gate electrode 18. For example, the surface resistance of the first gate line 25a is lower than the surface resistance of the gate electrode 18. In addition, for example, the surface resistance of the second gate line 25b is lower than the surface resistance of the gate electrode 18.

[0319] By making the surface resistance of the gate wiring layer 25 lower than that of the gate electrode 18, the resistance per unit length of the gate wiring layer 25 in the second direction is lower than the resistance per unit length of the gate electrode 18 in the first direction.

[0320] For example, gate wiring layer 25 is polysilicon containing n-type impurities, and gate electrode 18 is polysilicon containing p-type impurities. For example, first gate line 25a is polysilicon containing n-type impurities, and gate electrode 18 is polysilicon containing p-type impurities. Alternatively, for example, second gate line 25b is polysilicon containing n-type impurities, and gate electrode 18 is polysilicon containing p-type impurities.

[0321] n-type impurities are, for example, phosphorus (P) or arsenic (As). p-type impurities are, for example, boron (B).

[0322] The gate wiring layer 25 is polysilicon containing n-type impurities, and the gate electrode 18 is polysilicon containing p-type impurities. Therefore, it is easy to make the surface resistance of the gate wiring layer 25 lower than the surface resistance of the gate electrode 18. Consequently, it is easy to make the resistance per unit length of the gate wiring layer 25 in the second direction lower than the resistance per unit length of the gate electrode 18 in the first direction.

[0323] For example, gate wiring layer 25 is a stacked structure of polysilicon and silicide containing n-type or p-type impurities, and gate electrode 18 is a monolayer structure of polysilicon containing n-type or p-type impurities. For example, first gate line 25a is a stacked structure of polysilicon and silicide containing n-type or p-type impurities, and gate electrode 18 is a monolayer structure of polysilicon containing n-type or p-type impurities. Additionally, for example, second gate line 25b is a stacked structure of polysilicon and silicide containing n-type or p-type impurities, and gate electrode 18 is a monolayer structure of polysilicon containing n-type or p-type impurities.

[0324] By setting the gate wiring layer 25 to a stacked structure of polysilicon silicide containing n-type or p-type impurities, and setting the gate electrode 18 to a single-layer structure of polysilicon containing n-type or p-type impurities, it is easy to make the surface resistance of the gate wiring layer 25 lower than that of the gate electrode 18. Therefore, it is easy to make the resistance per unit length of the gate wiring layer 25 in the second direction lower than the resistance per unit length of the gate electrode 18 in the first direction.

[0325] An interlayer insulating layer 28 is disposed on the field insulating layer 30. The interlayer insulating layer 28 is, for example, silicon oxide.

[0326] A field insulating layer 30 is disposed on the silicon carbide layer 10. The field insulating layer 30 is, for example, silicon oxide.

[0327] Gate electrode pad 24 is disposed on the first surface P1 side of silicon carbide layer 10. Gate electrode pad 24 contains metal. Gate electrode pad 24 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0328] The gate electrode 18, located in the component region 101, is electrically connected to the gate electrode pad 24 via the gate wiring layer 25.

[0329] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 32.

[0330] The width of the intermediate region 103 in the second direction from the component region 101 toward the terminal region 102 is more than twice the thickness of the silicon carbide layer 10. The width of the intermediate region 103 is, for example, the distance in the second direction between the first contact portion C1 and the second contact portion C2.

[0331] For example, the first width in the second direction from the component region 101 of the intermediate region 103 toward the terminal region 102 ( Figure 14 w1 in the figure represents the thickness of silicon carbide layer 10. Figure 14 More than twice the value of t in the text. Additionally, for example, the second width (in the first direction from the element region 101 of the intermediate region 103, including the first gate line 25a of the gate wiring layer 25, toward the terminal region 102) is... Figure 15 w2 in the figure represents the thickness of silicon carbide layer 10. Figure 15 More than twice the value of t in the text.

[0332] Next, the function and effect of the MOSFET 300 in the third embodiment will be explained.

[0333] The MOSFET300 features a forward bias diode (SBD). The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows through the SBD before the pn junction diode.

[0334] The forward voltage (Vf) of an SBD is, for example, above 1.0V and below 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, above 2.0V and below 3.0V.

[0335] The SBD operates in a unipolar manner. Therefore, even with forward current flow, stacking defects will not grow in the silicon carbide layer 10 due to carrier recombination energy. Consequently, the increase in the on-resistance of the MOSFET 300 is suppressed. Therefore, the reliability of the MOSFET 300 is improved.

[0336] A large surge voltage, with the source electrode 12 as the positive electrode, may be momentarily applied between the source electrode 12 and the drain electrode 14 of the MOSFET 300. If a large surge voltage is applied, a large surge current will flow through the MOSFET 300, potentially damaging the MOSFET 300.

[0337] The maximum allowable peak surge current of a MOSFET is called its surge current withstand capability. In MOSFETs with SBD (Surge Difference) configuration, improving surge current withstand capability is desirable from a reliability perspective.

[0338] When a surge voltage is applied to MOSFET 300, a forward voltage is applied to the pn junction between drift region 34 and body region 36 in device region 101. When the voltage applied to the pn junction exceeds the forward voltage (Vf) of the pn junction diode, hole injection begins from the first contact C1 into drift region 34. Holes are injected from the first contact C1 into drift region 34 via body region 36.

[0339] If hole injection begins from the first contact C1 into the drift region 34, conductivity modulation occurs, causing the drift region 34 to become low-resistance. If the drift region 34 becomes low-resistance, a large forward current flows between the source electrode 12 and the drain electrode 14. In other words, a large surge current flows between the source electrode 12 and the drain electrode 14 through the bipolar operation of the pn junction diode.

[0340] A large surge current flows between the source electrode 12 and the drain electrode 14, causing the element region 101 to heat up. If thermal damage to the element region 101 occurs due to this heating, the MOSFET 300 will be damaged.

[0341] Figure 16 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the third embodiment. Figure 16 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 16 Is with Figure 14 The corresponding diagram.

[0342] In the MOSFET 300 of the third embodiment, the width of the intermediate region 103 in the second direction from the element region 101 toward the terminal region 102 is more than twice the thickness of the silicon carbide layer 10. For example, the first width of the intermediate region 103 in the second direction from the element region 101 toward the terminal region 102 ( Figure 14 w1 in the figure represents the thickness of silicon carbide layer 10. Figure 14 More than twice the width of t in the first direction from the element region 101 toward the terminal region 102. Additionally, for example, the second width of the intermediate region 103, including the first gate line 25a of the gate wiring layer 25, in the first direction (...) Figure 15 w2 in the figure represents the thickness of silicon carbide layer 10. Figure 15 More than twice the value of t in the text.

[0343] Since the width of the intermediate region 103 is more than twice the thickness of the silicon carbide layer 10, therefore... Figure 16 As shown, the diffusion current flowing from the first contact C1 and the diffusion current flowing from the second contact C2 do not cross at the bottom of the silicon carbide layer 10. Because the diffusion currents do not cross at the bottom of the silicon carbide layer 10, conductivity modulation is not promoted. Further low resistance reduction does not occur in the drift region 34, and surge current flowing in the termination region 102 can be suppressed. Therefore, heat generation in the termination region 102 is suppressed, and thermal damage in the termination region 102 is suppressed. Thus, the surge current tolerance of the MOSFET 300 is improved.

[0344] From the viewpoint of improving the surge current withstand capability of MOSFET 300, the width of the intermediate region 103 in the second direction from the element region 101 toward the terminal region 102 is preferably 2.5 times or more the thickness of the silicon carbide layer 10, and more preferably 3 times or more.

[0345] When the width of the intermediate region 103 increases, the occupancy of the component region 101 of the MOSFET 300 decreases. If the occupancy of the component region 101 of the MOSFET 300 decreases, the on-state current of the MOSFET 300 decreases.

[0346] From the viewpoint of increasing the on-current of the MOSFET 300, the width of the intermediate region 103 in the direction from the element region 101 toward the terminal region 102 is preferably 10 times or less the thickness of the silicon carbide layer 10, more preferably 5 times or less. For example, the second width in the first direction from the element region 101, including the first gate line 25a of the gate wiring layer 25, toward the terminal region 102 ( Figure 15 The thickness of the silicon carbide layer 10 is preferably w2). Figure 15 The width of the element region 101 in the middle region 103 towards the terminal region 102 is less than 10 times, more preferably less than 5 times. Additionally, for example, the first width (in the second direction from the element region 101 of the middle region 103 towards the terminal region 102) Figure 14 The thickness of the silicon carbide layer 10 is preferably w1). Figure 14 The value of t in the figure is less than 10 times, more preferably less than 5 times.

[0347] The terminal region 102 preferably includes a second diode D2. By providing the second diode D2 in the terminal region 102, the initial voltage for hole injection from the second contact C2 into the drift region 34 increases. This increase in the initial voltage for hole injection from the second contact C2 into the drift region 34 suppresses conductivity modulation in the drift region 34 of the terminal region 102. Therefore, heat generation in the terminal region 102 is suppressed, and thermal damage in the terminal region 102 is prevented.

[0348] According to the third embodiment, a MOSFET with suppressed thermal damage and improved surge current tolerance in the terminal region has been achieved.

[0349] (Fourth Implementation)

[0350] The semiconductor device of the fourth embodiment differs from that of the third embodiment in that it does not include a second diode in the terminal region. Hereinafter, some descriptions that are repeated in the third embodiment will be omitted.

[0351] Figure 17 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 17 It is the same as the third embodiment. Figure 14 The corresponding diagram.

[0352] The semiconductor device of the fourth embodiment is a planar gate type vertical MOSFET 400 using silicon carbide. The MOSFET 400 of the fourth embodiment is, for example, a DIMOSFET whose body region and source region are formed by ion implantation. Furthermore, the semiconductor device of the fourth embodiment includes an SBD as a built-in diode.

[0353] like Figure 17 As shown, the terminal region 102 of MOSFET400 does not contain a second diode.

[0354] According to the fourth embodiment, similar to the third embodiment, a MOSFET with suppressed thermal damage and improved surge current tolerance in the terminal region is realized.

[0355] In the first to fourth embodiments, the SiC crystal structure was described using 4H-SiC as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Additionally, surfaces other than the (0001) surface can also be applied to the surface of the silicon carbide layer 10.

[0356] In the first to fourth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but the first conductivity type can also be set to p-type and the second conductivity type to n-type.

[0357] In the first to fourth embodiments, aluminum (Al) is exemplified as a p-type impurity, but boron (B) can also be used. Additionally, nitrogen (N) and phosphorus (P) are exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be used.

[0358] In the first to fourth embodiments, the case in which the gate electrode 18 has a stripe shape in the element region 101 is described as an example, but the gate electrode 18 may also have a grid shape structure.

[0359] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: The component area includes a transistor, a first diode, and a first contact. The terminal region surrounds the element region and includes a second contact portion; and The intermediate region, located between the component region and the terminal region, does not include the transistor, the first diode, the first contact portion, or the second contact portion. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, the silicon carbide layer comprising: A first silicon carbide region of a first conductivity type has a first region that is in contact with the first surface and opposite the gate electrode, and a second region that is in contact with the first surface and in contact with the first electrode. The second silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, adjacent to the first region, opposite to the gate electrode, and in contact with the first electrode at the first interface. and The third silicon carbide region of the first conductivity type is disposed between the second silicon carbide region and the first surface, and is electrically connected to the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the second silicon carbide region, and between the gate electrode and the first region. The terminal area includes: The first wiring layer electrically connected to the first electrode; The second electrode; and The silicon carbide layer includes a first silicon carbide region and a fourth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface and in contact with the first wiring layer at a second interface. The intermediate region includes the silicon carbide layer, which includes the first silicon carbide region and a fifth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface. The transistor includes the gate electrode, the gate insulating layer, the first region, the second silicon carbide region, and the third silicon carbide region. The first diode includes the first electrode and the second region. The first contact portion includes the first interface. The second contact portion includes the second interface. The width of the intermediate region in the direction from the element region toward the terminal region is more than twice the thickness of the silicon carbide layer.

2. The semiconductor device according to claim 1, wherein, The intermediate region also includes a connection layer that connects the first electrode to the first wiring layer. The connecting layer does not contact the fifth silicon carbide region.

3. The semiconductor device according to claim 2, wherein, The gate electrode extends in a first direction parallel to the first surface.

4. The semiconductor device according to claim 3, wherein, The connecting layer is disposed in a second direction of the first electrode, the second direction being parallel to the first surface and perpendicular to the first direction.

5. The semiconductor device according to claim 4, wherein, The first wiring layer has: a first portion extending in the second direction; and a second portion extending in the second direction, with the first electrode sandwiched between the second portion and the first portion; The third portion extending in the first direction; And a fourth portion, extending in the first direction, with the first electrode sandwiched between the fourth portion and the third portion. The connecting layer is disposed between the first electrode and the fourth part.

6. The semiconductor device according to claim 5, wherein, The intermediate region also includes a gate electrode pad and a second wiring layer electrically connected to the gate electrode pad. The gate electrode is electrically connected to the gate electrode pad via the second wiring layer. The second wiring layer has: a first line extending in the second direction and disposed between the first portion and the first electrode; and a second line extending in the second direction and disposed between the second portion and the first electrode.

7. The semiconductor device according to claim 6, wherein, The first electrode, the first wiring layer, the connection layer, the gate electrode pad, and the second wiring layer all contain the same material.

8. The semiconductor device according to claim 3, wherein, The first width of the intermediate region in the second direction perpendicular to the first direction is greater than the second width of the intermediate region in the first direction.

9. The semiconductor device according to claim 1, wherein, The terminal region includes a second diode. The first silicon carbide region included in the terminal region has a third region that is in contact with the first surface and the first wiring layer. The second diode includes the first wiring layer and the third region.

10. A semiconductor device comprising: The component area includes a transistor, a first diode, and a first contact. The terminal region surrounds the element region and includes a second contact portion; and The intermediate region, located between the component region and the terminal region, does not include the transistor, the first diode, the first contact portion, or the second contact portion. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, and has a first surface on the side of the first electrode and a second surface on the side of the second electrode. The silicon carbide layer comprises: A first silicon carbide region of a first conductivity type has a first region that is in contact with the first surface and opposite to the gate electrode, and a second region that is in contact with the first surface and in contact with the first electrode. The second silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, adjacent to the first region, opposite to the gate electrode, and in contact with the first electrode at the first interface. and A third silicon carbide region of the first conductivity type is disposed between the second silicon carbide region and the first surface and is electrically connected to the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the second silicon carbide region and between the gate electrode and the first region. The terminal area includes: The first electrode; The second electrode; and The silicon carbide layer includes a first silicon carbide region and a fourth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface and in contact with the first electrode at a second interface. The intermediate region includes: The first electrode; The second electrode; and The silicon carbide layer includes a first silicon carbide region and a fifth silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface. The transistor includes the gate electrode, the gate insulating layer, the first region, the second silicon carbide region, and the third silicon carbide region. The first diode includes the first electrode and the second region. The first contact portion includes the first interface. The second contact portion includes the second interface. The width of the intermediate region in the direction from the element region toward the terminal region is more than twice the thickness of the silicon carbide layer.

11. The semiconductor device according to claim 10, wherein, The terminal region includes a second diode. The terminal region includes a first silicon carbide region having a third region that is in contact with the first surface and the first electrode. The second diode includes the first electrode and the third region.

12. The semiconductor device according to claim 10, wherein, The intermediate region also includes: Gate electrode pads; and A gate wiring layer is disposed between the first electrode and the silicon carbide layer, and has: a first gate line electrically connected to the gate electrode pad and the gate electrode, and extending in a second direction perpendicular to a first direction parallel to the first surface; and a second gate line extending in the second direction, with the gate electrode sandwiched between the second gate line and the first gate line.

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