Semiconductor device

Abstract

A semiconductor device with improved reliability has a semiconductor portion and first to third electrodes. The first electrode is provided on the back surface of the semiconductor portion. The second electrode is provided on the surface of the semiconductor portion. The semiconductor portion includes a first layer of a first conductivity type and second and third layers of a second conductivity type. Further, the semiconductor portion includes an active region and a terminal region surrounding the active region, and the second electrode is provided on the active region. The second layer is provided between the first layer and the second electrode and is electrically connected to the second electrode. The third layer surrounds the second layer along the boundary between the active region and the terminal region and is provided separately from the second layer. The third electrode extends in the first layer between the first electrode and the second electrode and extends in the third layer along the surface of the semiconductor portion. The third layer is electrically connected to the second electrode via the third electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-153420 (filed on September 21, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] High reliability is required for semiconductor devices used in power converters and similar applications. For example, high breakdown capacity for high voltage and high current is important. Summary of the Invention

[0005] The implementation provides a semiconductor device that improves reliability.

[0006] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, a second electrode, a third electrode, a first insulating film, and a fourth electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the second conductivity type. The first electrode is disposed on the back surface of the semiconductor portion, and the second electrode is disposed on the surface of the semiconductor portion. The third electrode is disposed between the first electrode and the second electrode, electrically connected to the second electrode, and extends from the surface side of the semiconductor portion into the semiconductor portion. The first insulating film is disposed between the third electrode and the semiconductor portion, electrically insulating the third electrode from the semiconductor portion. The fourth electrode is disposed on the surface of the semiconductor portion and is separate from the second electrode. The semiconductor portion includes an active region and an end region surrounding the active region in a plane parallel to the back surface, and the second electrode is disposed on the active region. The first semiconductor layer extends between the first electrode and the second electrode. The second semiconductor layer is disposed between the first semiconductor layer and the second electrode and is electrically connected to the second electrode. The third semiconductor layer is disposed on the surface side of the semiconductor portion and is configured to surround the second semiconductor layer along the boundary between the active region and the terminal region, and is separated from the second semiconductor layer. The third electrode is configured to extend from the surface side of the semiconductor portion into the first semiconductor layer, opposite the second semiconductor layer through the first insulating film, and extend along the surface of the semiconductor portion into the third semiconductor layer. The fourth electrode is disposed on the third semiconductor layer, electrically connected to the third semiconductor layer, and electrically connected to the portion of the third electrode extending into the third semiconductor layer. The third semiconductor layer is electrically connected to the second electrode via the third electrode and the fourth electrode. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view showing the semiconductor device involved in the embodiment.

[0008] Figure 2 (a) to (c) are other schematic cross-sectional views representing the semiconductor device involved in the embodiment.

[0009] Figure 3 This is a schematic top view showing the semiconductor device involved in the implementation.

[0010] Figure 4 (a) and (b) are schematic diagrams illustrating the first characteristic of the semiconductor device involved in the embodiment.

[0011] Figure 5 It is a graph representing the second characteristic of the semiconductor device involved in the implementation.

[0012] Figure 6 (a) and (b) are schematic diagrams illustrating the third characteristic of the semiconductor device involved in the embodiment.

[0013] Figure 7 (a) to (e) are schematic diagrams illustrating the fourth characteristic of the semiconductor device involved in the embodiment.

[0014] Figure 8 This is a schematic diagram illustrating the fifth characteristic of the semiconductor device involved in the embodiment.

[0015] Figure 9 (a) and (b) are schematic diagrams illustrating the semiconductor device involved in the first variation of the embodiment.

[0016] Figure 10 This is a schematic top view illustrating the semiconductor device involved in the second variation of the embodiment.

[0017] Figure 11 (a) to (c) are schematic cross-sectional views showing the semiconductor device involved in the third variation of the embodiment.

[0018] Figure 12 (a) to (c) are schematic cross-sectional views showing the semiconductor device involved in the fourth variation of the embodiment.

[0019] Figure 13 (a) and (b) are schematic cross-sectional views showing the semiconductor device involved in the fifth variation of the embodiment.

[0020] Figure 14 This is a schematic cross-sectional view illustrating the semiconductor device involved in the sixth variation of the embodiment. Detailed Implementation

[0021] The embodiments will now be described with reference to the accompanying drawings. The same numbers will be used to designate the same parts in the drawings, and detailed descriptions will be omitted where appropriate; different parts will be described separately. Furthermore, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., are not limited to being the same as in reality. Additionally, even when showing the same parts, sometimes the dimensions and ratios of each part may be shown differently depending on the drawings.

[0022] Furthermore, the configuration and structure of each part are explained using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are orthogonal to each other, representing the X, Y, and Z directions, respectively. Additionally, sometimes the Z direction is set upwards, and its opposite direction downwards for explanation.

[0023] Figure 1 This is a schematic cross-sectional view showing the semiconductor device 1 according to the embodiment.

[0024] Figure 2 (a) to (c) are other schematic cross-sectional views representing the semiconductor device 1 according to the embodiment. Figure 2 (a) is along Figure 1 The cross-sectional view of line A-A shown in the figure. Figure 2 (b) is along Figure 1 The cross-sectional view of line B-B shown. Figure 2 (c) is along Figure 1 The cross-sectional view of the C-C line shown.

[0025] Semiconductor device 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Semiconductor device 1 includes an active region AR and an end region TR. Figure 1 This is a cross-sectional view representing the active region AR. Figure 2 (a) to (c) are sectional views representing the end region TR.

[0026] like Figure 1 As shown, semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a third electrode 40, and a control electrode 50. The semiconductor portion 10 has a surface 10F and a back surface 10B opposite to it. The semiconductor portion 10 is, for example, silicon. The first electrode 20 is disposed on the back surface of the semiconductor portion 10. The second electrode 30 is disposed on the surface of the semiconductor portion 10. The first electrode 20 is, for example, a collector electrode. The second electrode 30 is, for example, an emitter electrode.

[0027] The third electrode 40 is disposed between the first electrode 20 and the second electrode 30. The third electrode 40 is disposed inside a trench TG1 formed on the surface side of the semiconductor section 10. The third electrode 40 is electrically insulated from the semiconductor section 10 by the first insulating film 43. Furthermore, a second insulating film 45 is disposed between the second electrode 30 and the third electrode 40. The second insulating film 45 is, for example, an interlayer insulating film. The first insulating film 43 and the second insulating film 45 are, for example, silicon oxide films.

[0028] A control electrode 50 is disposed between the first electrode 20 and the second electrode 30. The control electrode 50 is located inside a trench TG2 formed on the surface side of the semiconductor section 10. The control electrode 50 is electrically insulated from the semiconductor section 10 by a third insulating film 53. Furthermore, the control electrode 50 is electrically insulated from the second electrode 30 by a second insulating film 45. The third insulating film 53 is, for example, a gate insulating film. The third insulating film 53 is, for example, a silicon oxide film.

[0029] like Figure 1 and Figure 2 As shown in (a) to (c), the semiconductor section 10 includes, for example, a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of a second conductivity type, a fourth semiconductor layer 17 of a first conductivity type, a fifth semiconductor layer 19 of a second conductivity type, and a sixth semiconductor layer 21 of a first conductivity type. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type.

[0030] The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. The first semiconductor layer 11 is, for example, an n-type substrate layer. The third electrode 40 and the control electrode 50 extend from the surface side of the semiconductor portion 10 into the first semiconductor layer 11.

[0031] The second semiconductor layer 13 is disposed between the first semiconductor layer 11 and the second electrode 30. The second semiconductor layer 13 is, for example, a p-type substrate layer. The second semiconductor layer 13 is disposed opposite to the third electrode 40 through the first insulating film 43. In addition, the second semiconductor layer 13 is disposed opposite to the control electrode 50 through the third insulating film 53.

[0032] The third semiconductor layer 15 is disposed on the surface side of the semiconductor portion 10 at the boundary between the active region AR and the terminal region TR. The third semiconductor layer 15 is, for example, a p-type guard ring. The third semiconductor layer 15 is configured to be separate from the second semiconductor layer 13.

[0033] The fourth semiconductor layer 17 is partially disposed between the second semiconductor layer 13 and the second electrode 30. The fourth semiconductor layer 17 is, for example, an n-type emitter layer. The fourth semiconductor layer 17 is configured to be connected to the third insulating film 53. The second electrode 30 is electrically connected to the second semiconductor layer 13 and the fourth semiconductor layer 17.

[0034] The fifth semiconductor layer 19 is disposed between the first semiconductor layer 11 and the first electrode 20. The fifth semiconductor layer 19 is, for example, a p-type collector layer. The first electrode 20 is electrically connected to the fifth semiconductor layer 19.

[0035] The sixth semiconductor layer 21 is disposed between the first semiconductor layer 11 and the fifth semiconductor layer 19. The sixth semiconductor layer 21 contains a higher concentration of first conductivity type impurities than the concentration of first conductivity type impurities in the first semiconductor layer 11. The sixth semiconductor layer 21 is, for example, an n-type buffer layer.

[0036] like Figure 2 As shown in (a) to (c), the semiconductor section 10 further includes a seventh semiconductor layer 23 of the first conductivity type and an eighth semiconductor layer 25 of the second conductivity type in the terminal region TR.

[0037] The seventh semiconductor layer 23 is disposed on the surface side of the semiconductor portion 10 at a position separate from the third semiconductor layer 15. The seventh semiconductor layer 23 contains a higher concentration of first conductivity type impurities than the concentration of first conductivity type impurities in the first semiconductor layer 11. The seventh semiconductor layer 23 is, for example, an n-type EQPR (Equivalent Potential Ring).

[0038] The eighth semiconductor layer 25 is disposed on the surface side of the semiconductor portion 10 between the third semiconductor layer 15 and the seventh semiconductor layer 23. The eighth semiconductor layer 25 is disposed at a position separate from the third semiconductor layer 15 and the seventh semiconductor layer 23. The eighth semiconductor layer 25 is, for example, a p-type guard ring. For example, multiple eighth semiconductor layers 25 can be disposed between the third semiconductor layer 15 and the seventh semiconductor layer 23.

[0039] The semiconductor device 1 also includes a fourth electrode 60, a fifth electrode 65, and a control wiring 70. The fourth electrode 60 and the fifth electrode 65 are disposed on the end region TR of the semiconductor section 10. The control wiring 70 is disposed, for example, on the active region AR.

[0040] The second insulating film 45 extends from the active region AR to the terminal region TR, covering the surface of the terminal region TR of the semiconductor section 10. The fourth electrode 60 and the fifth electrode 65 are disposed on the second insulating film 45. The control wiring 70 is electrically insulated from the semiconductor section 10 and the third electrode 40 by passing through the second insulating film 45.

[0041] The fourth electrode 60 is disposed above the third semiconductor layer 15. That is, the third semiconductor layer 15 is disposed, for example, in the Z direction, between the first semiconductor layer 11 and the fourth electrode 60. The fourth electrode 60 is electrically connected to the third semiconductor layer 15 via a contact hole provided in the second insulating film 45. The fourth electrode 60 is, for example, a field plate electrode.

[0042] like Figure 2 As shown in (a), the fourth electrode 60 is also disposed above the end of the third electrode 40. The fourth electrode 60 is electrically connected to the third electrode 40 via other contact holes provided in the second insulating film 45. Additionally, the third semiconductor layer 15 is electrically connected to the second electrode 30 in the active region AR via contact holes provided in the second insulating film 45. That is, the third semiconductor layer 15 is electrically connected to the second electrode 30 via the fourth electrode 60 and the third electrode 40.

[0043] The fifth electrode 65 is disposed on the eighth semiconductor layer 25 through the second insulating film 45. The fifth electrode 65 is electrically connected to the eighth semiconductor layer 25 via a contact hole provided in the second insulating film 45. The fifth electrodes 65 are disposed on multiple eighth semiconductor layers 25. The fifth electrode 65 is, for example, a field plate electrode.

[0044] like Figure 2 As shown in (b), the third semiconductor layer 15 is disposed separately from the second semiconductor layer 13. The second semiconductor layer 13 is electrically connected to the second electrode 30 and is at the same potential as the second electrode 30. On the other hand, the third semiconductor layer 15 is electrically connected to the second electrode 30 via the fourth electrode 60 and the third electrode 40. The third electrode 40 is formed, for example, using conductive polysilicon. For example, the resistance of the third electrode 40 can be controlled by the doping level of impurities in the polysilicon. The third semiconductor layer 15 is electrically connected to the second electrode 30 via a predetermined resistance.

[0045] like Figure 2 As shown in (c), the control wiring 70 is disposed, for example, on the surface side of the semiconductor portion 10, between the second electrode 30 and the fourth electrode 60. The control wiring 70 is disposed separately from the second electrode 30 and the fourth electrode 60. The control wiring 70 is electrically connected to the control electrode 50 via a contact hole provided in the second insulating film 45.

[0046] Furthermore, in the example described above, the fifth semiconductor layer 19 (p-type collector layer) is configured to extend from the active region AR to the terminal region TR, but the implementation is not limited to this. For example, it could also be configured such that the fifth semiconductor layer 19 does not extend in the terminal region TR. In this case, the sixth semiconductor layer 21 is connected to the first electrode 20 in the terminal region TR.

[0047] Figure 3 This is a schematic top view showing the semiconductor device 1 involved in the embodiment. Figure 3 This is a top view showing the surface 10F of the semiconductor section 10. Furthermore, in Figure 3 The fourth semiconductor layer 17, the first insulating film 43, and the third insulating film 53 are omitted.

[0048] like Figure 3 As shown, the third semiconductor layer 15 is configured to surround the second semiconductor layer 13. In addition, the eighth semiconductor layer 25 (not shown) also surrounds the second semiconductor layer 13 in the same manner as the third semiconductor layer 15.

[0049] The third electrode 40 and the control electrode 50 extend, for example, in the Y direction. The third electrode 40 and the control electrode 50 extend across the second semiconductor layer 13 and the third semiconductor layer 15. The two ends of the third electrode 40 and the control electrode 50 are respectively located in the third semiconductor layer 15.

[0050] The third semiconductor layer 15 is disposed separately from the second semiconductor layer 13. A portion of the first semiconductor layer 11 is exposed between the second semiconductor layer 13 and the third semiconductor layer 15. A first distance Lc from the second semiconductor layer 13 to the third semiconductor layer 15 is appropriately set.

[0051] Figure 4 (a) and (b) are schematic diagrams illustrating a first characteristic of the semiconductor device 1 according to the embodiment. Figure 4 (a) is a partial cross-sectional view of semiconductor device 1. Figure 4 (b) shows the voltage-current characteristics of semiconductor device 1 when it is turned off. The horizontal axis is the voltage Vce applied between the first electrode 20 and the second electrode 30. The vertical axis is the current Ic flowing between the first electrode 20 and the second electrode 30.

[0052] like Figure 4 As shown in (a), the fourth electrode 60 is electrically connected to the second electrode 30 via a resistor Rp. The fourth electrode 60 is electrically connected to the second electrode 30 via the third electrode 40 (see Figure 1). Figure 2 (a) That is, the resistor Rp is the resistance of the third electrode 40. In addition, the third semiconductor layer 15 is electrically connected to the fourth electrode 60. In other words, the third semiconductor layer 15 is electrically connected to the second electrode 30 via the resistor Rp.

[0053] A portion of the first semiconductor layer 11 extends between the second semiconductor layer 13 and the third semiconductor layer 15. The first semiconductor layer 11 is configured, for example, to be in contact with the second insulating film 45 between the second semiconductor layer 13 and the third semiconductor layer 15. Therefore, when the semiconductor device 1 is disconnected, the second semiconductor layer 13 and the third semiconductor layer 15 are electrically connected via a p-type inversion layer induced between the first semiconductor layer 11 and the second insulating film 45. Here, the channel resistance of the p-type inversion layer is set to Rc.

[0054] The voltage-current characteristics when semiconductor device 1 is disconnected are determined by the balance between resistance Rp and channel resistance Rc. Resistance Rp is controlled, for example, by the impurity concentration of the polysilicon used in the third electrode 40. Furthermore, the channel resistance Rc is determined by the first distance Lc from the second semiconductor layer 13 to the third semiconductor layer 15 (see reference). Figure 3 The channel resistance Rc is determined by the distance Lc. The longer the distance Lc is, the greater the channel resistance Rc becomes.

[0055] Figure 4 (b) shows the current-voltage characteristics of semiconductor device 1 using the first distances Lc1 to Lc4 as parameters. Here, the resistance Rp is 1 × 10⁻⁶. 12 Ωμm. Lc1 to Lc4 are in the relationship Lc1 < Lc2 < Lc3 < Lc4.

[0056] like Figure 4 As shown in (b), if the first distance Lc is extended from Lc1 to Lc2, the breakdown voltage VB increases from VB1 to VB2. Furthermore, if the first distance Lc is extended to Lc3 or Lc4, the breakdown voltage VB decreases to VB3 or VB4, which are lower than VB1. That is, if the first distance Lc is changed, the electric field distribution in the terminal region TR changes, reflecting the shift of the avalanche breakdown point from the outer edge 15e of the third semiconductor layer 15 to the outer edge 13e of the second semiconductor layer 13.

[0057] Furthermore, when the first distance Lc is set to Lc2, Lc3, and Lc4, a so-called ripple occurs where, after the voltage Vce reaches the breakdown voltages VB2, VB3, and VB4, the current Ic increases and the voltage Vce decreases. If the ripple described above occurs, the current Ic increases rapidly, sometimes leading to component damage due to overcurrent.

[0058] Figure 5 It is a graph representing the second characteristic of the semiconductor device 1 according to the embodiment. Figure 5 The horizontal axis represents the first distance Lc. The vertical axis represents the breakdown voltage VB.

[0059] like Figure 5 As shown, when the resistance Rp is 1×10 12 In the case of Ωμm, the breakdown voltage VB remains constant until the first distance Lc becomes 10μm. On the other hand, the breakdown voltage VB increases between Lc = 10μm and 15μm. Furthermore, if the first distance Lc is made longer than 15μm, the breakdown voltage VB decreases.

[0060] When the first distance Lc is less than 10 μm, the channel resistance Rc is small, and the potential difference between the second semiconductor layer 13 and the third semiconductor layer 15 is small. Therefore, the outer edge 15e of the third semiconductor layer 15 (refer to...) Figure 4The electric field at (a) increases, causing avalanche breakdown at the outer edge 15e. If the first distance Lc exceeds 15 μm, the channel resistance Rc increases, and the potential difference between the second semiconductor layer 13 and the third semiconductor layer 15 increases. Therefore, avalanche breakdown occurs at the outer edge 13e of the second semiconductor layer 13.

[0061] As mentioned above, if Rp is set to 1 × 10 12 If Ωμm, the breakdown voltage VB rises during the intermediate state of the avalanche breakdown point transitioning from the outer edge 15e of the third semiconductor layer 15 to the outer edge 13e of the second semiconductor layer 13.

[0062] On the other hand, when Rp = 1 × 10 6 In the case of Ωμm, the breakdown voltage VB remains constant until the first distance Lc becomes 20μm. If the first distance Lc exceeds 20μm, the breakdown voltage VB decreases. If the resistance Rp decreases, the voltage drop between the third semiconductor layer 15 and the second electrode 30 decreases. Therefore, even if the first distance Lc is extended, the voltage drop across the outer edge 15e of the third semiconductor layer 15 (refer to...) remains constant. Figure 4 The electric field of (a) will also remain high. That is, avalanche breakdown in the outer edge 15e of the third semiconductor layer 15 is dominated and maintained. If the first distance Lc exceeds 20 μm, then in the outer edge 13e of the second semiconductor layer 13 ( Figure 4 In (a) reference), avalanche breakdown occurs, and the breakdown voltage VB decreases.

[0063] Figure 6 This is a schematic diagram illustrating the third characteristic of the semiconductor device 1 according to the embodiment. Figure 6 The diagram shows that Rp = 1 × 10 9 Ωμm, 1×10 6 Voltage and current characteristics at Ωμm and Lc = 20μm. The horizontal axis represents voltage Vce, and the vertical axis represents current Ic.

[0064] Set the resistor Rp to 1×10 9 In the case of Ωμm, the characteristic of voltage Vce increasing with current Ic after avalanche breakdown occurs at breakdown voltage VB1 is shown. The breakdown voltage VB eventually reaches a higher withstand voltage VBf than VB1. That is, by setting the resistor Rp to 1×10 6 Ωμm and 1×10 12 The intermediate value between Ω and μm is used to obtain the ratio, which is set as Rp = 1 × 10. 6 The breakdown voltage VB1 at Ωμm is the higher breakdown voltage VBf.

[0065] Furthermore, it is possible to obtain the characteristic that the voltage Vce increases with the increase of current Ic after the initial avalanche breakdown. As a result, the so-called breakover withstand capability can be improved, for example, preventing component damage caused by sudden return.

[0066] Figure 7 (a) to (e) are schematic cross-sectional views showing the fourth characteristic of the semiconductor device 1 according to the embodiment. Figure 7 (a) to (e) show that Rp is set to 1×10 9 The voltage and current characteristics under varying distances Lc (Ωμm). The horizontal axis represents voltage Vce, and the vertical axis represents current Ic.

[0067] Figure 7 (a) shows the voltage-current characteristics when Lc = 10 μm. Figure 7 As shown in (a), avalanche breakdown occurs when Vce = VB1.

[0068] like Figure 7 As shown in (b), with Lc = 12.5 μm, after avalanche breakdown at Vce = VB1, the voltage Vce increases with the increase of current Ic. The breakdown voltage VB eventually reaches VBf.

[0069] like Figure 7 As shown in (c) and (d), a sudden cyclic return occurs after Vce = VBf when Lc = 15 μm and Lc = 17.5 μm. In this case, the current Isnp at which the cyclic return occurs is greater than... Figure 4 The example shown in (b) is larger, and the penetration resistance is improved.

[0070] like Figure 7 As shown in (e), even when Lc = 20 μm, the voltage Vce increases with increasing current Ic after avalanche breakdown at Vce = VB1. The breakdown voltage VB eventually reaches VBf.

[0071] Therefore, the first distance Lc is preferably longer than 10 μm and less than 20 μm (see reference). Figure 5 Furthermore, the first distance Lc is more preferably 12.5 μm or more and 20 μm or less.

[0072] Figure 8 This is a schematic diagram illustrating the fifth characteristic of the semiconductor device 1 according to the embodiment. Figure 8 The voltage-current characteristics are shown when the first distance Lc is set to 15 μm and the resistance Rp is varied. The horizontal axis represents voltage Vce, and the vertical axis represents current Ic.

[0073] like Figure 8 As shown, in Rp = 7 × 106 Ωμm~1×10 10 Within the Ωμm range, the characteristic that after avalanche breakdown occurs at Vce = VB1, the voltage Vce increases with the increase of current Ic is obtained. That is, the resistor Rp is preferably 7 × 10⁻⁶. 6 Ωμm or larger and 1×10 10 Below Ωμm.

[0074] Figure 9 (a) and (b) are schematic diagrams illustrating the semiconductor device 2 involved in the first variation of the embodiment. Figure 9 (a) is a top view showing the surface 10F of the semiconductor section 10. Figure 9 (b) shows the voltage-current characteristics when semiconductor device 2 is turned off. Furthermore, in Figure 9 In (a), the third electrode 40, the control electrode 50, the fourth semiconductor layer 17, the first insulating film 43 and the third insulating film 53 are omitted.

[0075] like Figure 9 As shown in (a), the semiconductor device 2 has a first distance Lcs and a second distance Lcc between the second semiconductor layer 13 and the third semiconductor layer 15. The second semiconductor layer 13, for example, is located at the surface 10F of the semiconductor portion 10 (see reference). Figure 1 When viewed from above in parallel, it is shaped like a quadrilateral. The third semiconductor layer 15, which surrounds the second semiconductor layer 13, also has a quadrilateral outer edge.

[0076] The first distance Lcs is the distance from the edge of the second semiconductor layer 13 to the inner edge of the third semiconductor layer 15. The second distance Lcc is the distance from the corner of the second semiconductor layer 13 to the inner edge of the corner of the third semiconductor layer 15.

[0077] At the outer edge of the corner of the third semiconductor layer 15, for example, when disconnected, the electric field concentrates, causing a decrease in the breakdown voltage VB of the end region TR. Therefore, it is preferable to increase the breakdown voltage VB at the corner of the third semiconductor layer 15 by making the second distance Lcc longer than the first distance Lcs. As a result, avalanche breakdown can occur along the outer edge of the third semiconductor layer 15.

[0078] exist Figure 9 In the voltage-current characteristic shown in (b), the horizontal axis is set as voltage Vce, and the vertical axis is set as current Ic. Figure 9 As shown in (b), the current Ic before avalanche breakdown increases at the corner of the third semiconductor layer 15 where electric field concentration is likely to occur.

[0079] In the third semiconductor layer 15, by making the second distance Lcc longer than the first distance Lcs, avalanche breakdown occurs along the outer edge of the region from the second semiconductor layer 13 to the third semiconductor layer 15 at a distance equal to the first distance Lcs. This mitigates current concentration at the corners of the third semiconductor layer 15 and improves punch-through capacity.

[0080] Figure 10 This is a schematic top view showing the semiconductor device 3 involved in the second variation of the embodiment. Figure 10 This is a top view showing the surface 10F of the semiconductor section 10. Furthermore, in Figure 10 The third electrode 40, control electrode 50, fourth semiconductor layer 17, first insulating film 43 and third insulating film 53 are omitted.

[0081] In this example, a first distance Lcs and a second distance Lcc are also provided between the second semiconductor layer 13 and the third semiconductor layer 15. Additionally, the second semiconductor layer 13 is located at the surface 10F of the semiconductor portion 10 (see reference). Figure 1 When viewed from above in parallel, it is shaped like a quadrilateral. The third semiconductor layer 15, which surrounds the second semiconductor layer 13, also has a quadrilateral outer edge.

[0082] like Figure 10 As shown, the third semiconductor layer 15 is divided into multiple portions 15a. A connection portion 15b is provided between two adjacent portions 15a of the third semiconductor layer 15. The connection portion 15b contains a lower concentration of second conductivity type impurities compared to the concentration of second conductivity type impurities in the multiple portions 15a.

[0083] The first distance Lcs is shorter than the second distance Lcc. Furthermore, the first distance Lcs is located between the edge of the second semiconductor layer 13 and the inner edge of one of the plurality of portions 15a of the third semiconductor layer 15 that is opposite to the edge of the second semiconductor layer 13. The second distance Lcc is located between the corner of the second semiconductor layer 13 and the inner edge of the portion 15a located at the corner of the third semiconductor layer 15. Additionally, the second distance Lcc is also located between the connection portion 15b of the second semiconductor layer 13 and the third semiconductor layer 15.

[0084] As described above, by dividing the third semiconductor layer 15 via the connection portion 15b, it is possible to configure each portion 15a to have a different potential when disconnected. Furthermore, avalanche breakdown may occur, for example, at the outer edge of the portion 15a of the third semiconductor layer 15 having a first distance Lcs. In this example, by dispersing the breakdown points of avalanche breakdown, current concentration can be mitigated, thereby improving punch-through capacity.

[0085] Figure 11(a) to (c) are schematic cross-sectional views showing the semiconductor device 4 according to the third variation of the embodiment. Figure 11 (a) is along Figure 1 The cross-sectional view of the active region AR of line A-A shown. Figure 11 (b) is along Figure 1 The cross-sectional view of the active region AR of the B-B line shown. Figure 11 (c) is along Figure 1 The cross-sectional view of the active region AR of the C-C line shown.

[0086] like Figure 11 As shown in (a), the semiconductor device 4 includes, for example, two third electrodes 40 arranged in the Y direction. The third electrodes 40 are respectively disposed between the semiconductor portion 10 and the second electrode 30. A second insulating film 45 is disposed between the second electrode 30 and the third electrode 40. The third electrode 40 is electrically connected to the second electrode 30 via contact holes provided in the second insulating film 45. Furthermore, the third electrode 40 is electrically connected to a fourth electrode 60 via other contact holes provided in the second insulating film 45.

[0087] Semiconductor device 4 includes, for example, control wiring 70a, control wiring 70b, and control wiring 70c. Control wirings 70a, 70b, and 70c are electrically connected, for example, to control pads (not shown) disposed on the surface side of semiconductor portion 10. Control wirings 70a, 70b, and 70c are disposed on the surface side of semiconductor portion 10 and are electrically insulated from semiconductor portion 10 by a second insulating film 45. Control wirings 70a and 70b are, for example, disposed in active region AR (see reference). Figure 2 The two ends of (a) in the Y direction. Control wiring 70c is located between control wiring 70a and control wiring 70b.

[0088] Semiconductor device 4 has a so-called finger portion FP. The finger portion FP includes a 9th semiconductor layer 27 of a second conductivity type and control wiring 70c. The 9th semiconductor layer 27 is disposed between two 3rd electrodes 40. The control wiring 70c is disposed on the 9th semiconductor layer 27 through a 2nd insulating film 45.

[0089] The two third electrodes 40 each have an end located in the ninth semiconductor layer 27. The third electrode 40 is connected, for example, to the end of the second semiconductor layer 13 located in the ninth semiconductor layer 27. In addition, the end of the third electrode 40 opposite to the end located in the ninth semiconductor layer 27 is connected to the fourth electrode 60.

[0090] like Figure 11As shown in (b), the 9th semiconductor layer 27 is disposed separately from the 2nd semiconductor layer 13. A portion of the 1st semiconductor layer 11 extends between the 2nd semiconductor layer 13 and the 9th semiconductor layer 27 and is in contact with the 2nd insulating film 45. In this case, the 9th semiconductor layer 27 is, for example, connected to the 3rd semiconductor layer 15 at its end (not shown) in the X direction.

[0091] like Figure 11 As shown in (c), the control electrode 50 extends in the Y direction and is connected to control wirings 70a, 70b, and 70c via contact holes provided in the second insulating film 45. The control electrode 50 is connected to control wirings 70a and 70b at, for example, both ends in the Y direction. The control electrode 50 has a portion in the finger portion FP located between a portion of the ninth semiconductor layer 27 and the control wiring 70c. The control electrode 50 is connected to the control wiring 70c in the finger portion FP.

[0092] Figure 12 (a) to (c) are schematic cross-sectional views showing the semiconductor device 5 according to the fourth variation of the embodiment. Figure 12 (a) is along Figure 1 The cross-sectional view of the active region AR of line A-A shown. Figure 12 (b) is along Figure 1 The cross-sectional view of the active region AR of the B-B line shown. Figure 12 (c) is along Figure 1 The cross-sectional view of the active region AR of the C-C line shown. Semiconductor device 5 differs from semiconductor device 4 in the relationship between the second semiconductor layer 13, the third semiconductor layer 15, and the ninth semiconductor layer 27.

[0093] like Figure 12 As shown in (a), the semiconductor device 4 includes, for example, two third electrodes 40 arranged in the Y direction. The third electrodes 40 are electrically connected to the second electrode 30. In addition, the third electrodes 40 are electrically connected to the fourth electrode 60.

[0094] The finger portion FP includes a 9th semiconductor layer 27 and control wiring 70c. The 9th semiconductor layer 27 is disposed between the two 3rd electrodes 40. The control wiring 70c is disposed on the 9th semiconductor layer 27 through a 2nd insulating film 45.

[0095] like Figure 12 As shown in (b), the 9th semiconductor layer 27 is configured to be connected to the 2nd semiconductor layer 13. In this case, the 9th semiconductor layer 27 is configured, for example, to be separated from the 3rd semiconductor layer 15 at an end (not shown) in the X direction.

[0096] like Figure 12As shown in (c), the control electrode 50 extends in the Y direction and is connected to control wirings 70a, 70b, and 70c. For example, the control electrode 50 is connected to control wirings 70a and 70b at both ends in the Y direction, respectively. Additionally, the control electrode 50 is connected to control wiring 70c in the finger portion FP.

[0097] Figure 13 (a) and (b) are schematic cross-sectional views of the semiconductor device 6 according to the fifth variation of the embodiment. Figure 13 (b) is along Figure 13 The cross-sectional view of line D-D shown in (a). Semiconductor device 6 is, for example, a MOSFET.

[0098] like Figure 13 As shown in (a), the third electrode 40 and the control electrode 50 are disposed inside a trench TG1. The third electrode 40 is disposed between the first electrode 20 and the control electrode 50. The control electrode 50 is disposed between the second electrode 30 and the third electrode 40.

[0099] The third electrode 40 is disposed on the bottom surface of trench TG1, facing the first semiconductor layer 11 through the first insulating film 43. The control electrode 50 faces the second semiconductor layer 13 through the third insulating film 53. A fourth insulating film 55 is disposed between the third electrode 40 and the control electrode 50. The fourth insulating film 55 electrically insulates the third electrode 40 from the control electrode 50. The fourth insulating film 55 is, for example, a silicon oxide film.

[0100] like Figure 13 As shown in (b), the third electrode 40 and the control electrode 50 extend, for example, in the Y direction. Additionally, the two control electrodes 50 are arranged in the Y direction. The third electrode 40 has upwardly extending contact portions 40a and 40b at both ends of the trench TG1 in the Y direction. Furthermore, the third electrode 40 has an upwardly extending contact portion 40c between the two control electrodes 50.

[0101] The second electrode 30 is connected to the contact portion 40c of the third electrode 40 via a contact hole provided in the second insulating film 45. The fourth electrode 60 is connected to the contact portions 40a and 40c of the third electrode 40 via other contact holes provided in the second insulating film 45.

[0102] like Figure 13 As shown in (b), a control wiring 70 is provided between the second electrode 30 and the fourth electrode 60. The control wiring 70 is electrically insulated from the semiconductor section 10 through the second insulating film 45. For example, the control wiring 70 is provided on the end of the control electrode 50 and is connected to the control electrode 50 through a contact hole provided in the second insulating film 45.

[0103] In this example, the second electrode 30 is also electrically connected to the fourth electrode 60 via the third electrode 40. The fourth electrode 60 is electrically connected to the third semiconductor layer 15 via a contact hole provided in the second insulating film 45. That is, the third semiconductor layer 15 is electrically connected to the second electrode 30 via the third electrode 40. Furthermore, the third semiconductor layer 15 is disposed separately from the second semiconductor layer 13 (see reference). Figure 2 (b) Therefore, in this example, by appropriately setting the resistance Rp of the third electrode 40 and the first distance Lc between the second semiconductor layer 13 and the third semiconductor layer 15, the punch-through resistance can be improved.

[0104] Figure 14 This is a schematic cross-sectional view showing the semiconductor device 7 according to the sixth variation of the embodiment. The semiconductor device 7 is, for example, a diode. The semiconductor device 7 can be used, for example, as a freewheeling diode integrated with an IGBT.

[0105] like Figure 14 As shown, the semiconductor device 7 has a plurality of third electrodes 40 disposed inside the trench TG1. The third electrodes 40 extend from the surface side of the semiconductor portion 10 into the first semiconductor layer 11. A second semiconductor layer 13 and a ninth semiconductor layer 27 of a second conductivity type are disposed between adjacent third electrodes 40.

[0106] A second semiconductor layer 13 is disposed between the first semiconductor layer 11 and the second electrode 30. A ninth semiconductor layer 27 is disposed between the second semiconductor layer 13 and the second electrode 30. The ninth semiconductor layer 27 contains a higher concentration of second conductivity type impurities than the concentration of second conductivity type impurities in the second semiconductor layer 13, and is electrically connected to the second electrode 30. The ninth semiconductor layer 27 is, for example, a p-type contact layer.

[0107] In this example, the second electrode 30 is also electrically connected to the fourth electrode 60 via the third electrode 40 (see reference). Figure 2 (a)). That is, the second electrode 30 is electrically connected to the third semiconductor layer 15 (not shown) via the third electrode 40. Furthermore, the second semiconductor layer 13 is configured to be separate from the third semiconductor layer 15 (see reference [reference]). Figure 2 (b) Therefore, by appropriately setting the resistance Rp of the third electrode 40 and the first distance Lc between the second semiconductor layer 13 and the third semiconductor layer 15, the punch-through resistance can be improved.

[0108] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: The semiconductor section includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the second conductivity type; The first electrode is disposed on the back side of the semiconductor portion; The second electrode is disposed on the surface of the semiconductor portion; The third electrode is disposed between the first electrode and the second electrode, is electrically connected to the second electrode, and extends from the surface side of the semiconductor portion into the semiconductor portion; A first insulating film is disposed between the third electrode and the semiconductor portion, thereby electrically insulating the third electrode from the semiconductor portion; as well as The fourth electrode is disposed on the surface of the semiconductor portion and is separate from the second electrode. The semiconductor portion includes an active region and an end region surrounding the active region in a plane parallel to the back surface, and the second electrode is disposed on the active region. The first semiconductor layer extends between the first electrode and the second electrode. The second semiconductor layer is disposed between the first semiconductor layer and the second electrode and is electrically connected to the second electrode. The third semiconductor layer is disposed on the surface side of the semiconductor portion and is configured to surround the second semiconductor layer along the boundary between the active region and the terminal region, and is separate from the second semiconductor layer. The third electrode is configured to extend from the surface side of the semiconductor portion into the first semiconductor layer, face the second semiconductor layer across the first insulating film, and extend along the surface of the semiconductor portion into the third semiconductor layer. The fourth electrode is disposed on the third semiconductor layer, electrically connected to the third semiconductor layer, and electrically connected to the portion of the third electrode extending within the third semiconductor layer. The third semiconductor layer is electrically connected to the second electrode via the third electrode and the fourth electrode. The first distance from the second semiconductor layer to the third semiconductor layer is greater than 10 μm and less than 20 μm. The fourth electrode is electrically connected to the second electrode via a resistor of 7 × 10⁻⁶. 6 Ωμm or larger and 1×10 10 Below Ωμm.

2. The semiconductor device of claim 1, wherein, It also has a second insulating film disposed between the second electrode and the third electrode. The third electrode is electrically connected to the second electrode via a contact hole provided in the second insulating film.

3. The semiconductor device as claimed in claim 2, wherein, The second insulating film extends between the semiconductor portion and the fourth electrode. The third semiconductor layer and the third electrode are electrically connected to the fourth electrode via other contact holes provided in the second insulating film.

4. The semiconductor device as claimed in claim 2, wherein, It also has: A control electrode is disposed between the first electrode and the second electrode, and is located inside other trenches on the surface side of the semiconductor portion; and A third insulating film is disposed between the control electrode and the semiconductor portion. The second semiconductor layer is separated from the control electrode by the third insulating film. The second insulating film extends between the second electrode and the control electrode, thereby electrically insulating the control electrode from the second electrode. The semiconductor portion further includes a fourth semiconductor layer of the first conductivity type. The fourth semiconductor layer is partially disposed between the second semiconductor layer and the second electrode, is in contact with the third insulating film, and is electrically connected to the second electrode.

5. The semiconductor device as claimed in claim 2, wherein, It also has: A control electrode is disposed inside the trench of the semiconductor portion and positioned between the third electrode and the second electrode; A third insulating film is disposed between the control electrode and the semiconductor portion; and A fourth insulating film is disposed between the control electrode and the third electrode. The second semiconductor layer is separated from the control electrode by the third insulating film. The second insulating film extends between the second electrode and the control electrode, thereby electrically insulating the control electrode from the second electrode. The semiconductor portion further includes a fourth semiconductor layer of the first conductivity type. The fourth semiconductor layer is partially disposed between the second semiconductor layer and the second electrode, is in contact with the third insulating film, and is electrically connected to the second electrode.

6. The semiconductor device of claim 2, wherein, The semiconductor portion further includes a fifth semiconductor layer of the second conductivity type disposed between the first semiconductor layer and the first electrode.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The third semiconductor layer has a plurality of first portions arranged along the boundary between the active region and the terminal region, and a second portion disposed between two adjacent first portions. The second part contains a lower concentration of the second conductivity type impurity compared to the concentration of the second conductivity type impurity in the first part.

8. The semiconductor device according to any one of claims 1 to 6, wherein, When viewed from above parallel to the surface of the semiconductor portion, the second semiconductor layer has a quadrilateral outer edge. The first distance from the corner of the outer edge of the second semiconductor layer to the third semiconductor layer is longer than the second distance from the edge of the outer edge of the second semiconductor layer to the third semiconductor layer.

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