An intelligent power module

Abstract

The application provides a kind of intelligent power module, comprising: metal substrate layer, insulating layer being arranged on metal substrate layer, circuit layer being arranged on insulating layer, Hivc drive logic circuit being arranged on circuit layer, power switch circuit, cache circuit, IPM upper bridge arm drive circuit, IPM lower bridge arm drive circuit, FPC drive circuit, IPM switch tube assembly, PFC switch tube assembly, IPM working protection circuit, PFC working protection circuit, and protective layer being arranged on circuit layer, Hivc drive logic circuit is respectively connected with power switch circuit, IPM upper bridge arm drive circuit, IPM lower bridge arm drive circuit and FPC drive circuit, IPM upper bridge arm drive circuit, IPM lower bridge arm drive circuit is respectively connected with IPM switch group component, and FPC drive circuit is connected with PFC switch group component.The application Hivc application ability can realize inverter function and PFC function, and two functions are powered by independent power supply, so as to improve the applicability of product in complex application environment.

Description

Technical Field

[0001] This invention relates to the field of intelligent power module technology, and more particularly to an intelligent power module. Background Technology

[0002] An Intelligent Power Module (IPM) is a power drive semiconductor product that combines power electronics and HVIC (High-Voltage Integrated Circuit) technology. Internally, it integrates power switching devices and high-voltage drive circuitry, and includes built-in fault detection circuits for overvoltage, overcurrent, and overheating. It is widely used in systems such as frequency converters, welding machines, and servo drives. Internally, it consists of an upper bridge arm, a lower bridge arm, logic circuits, and protection circuits, using integrated circuit logic chips to achieve drive control and protection feedback. During operation, the IPM receives control signals from the MCU (Microcontroller Unit) to drive subsequent circuits, and simultaneously sends system status detection signals back to the MCU for processing. This allows for real-time monitoring of the IPM's operating dynamics, such as detecting sudden overcurrent, overvoltage, or overtemperature events, enabling timely protective actions.

[0003] HIVC (High Voltage Gate Driver IC) is a high-voltage-resistance IC that directly drives the gates of power MOSFETs and IGBTs using input signals from a microcontroller. It can replace common pulse transformers and optocouplers. As the core of intelligent power modules, it controls the operation of all power devices. The structural framework of the HVIC determines the drive control method of the solution, ultimately determining the product's differentiation and competitiveness.

[0004] Currently, high-voltage drive devices on the market generally have one, three, six, or seven channels, and without exception, they all use a single power supply. This makes them difficult to adapt to the complex, miniaturized, and intelligent multi-functional control systems that are the future trend.

[0005] Therefore, there is an urgent need to provide a new intelligent power module to solve the above problems. Summary of the Invention

[0006] To address the shortcomings of the aforementioned technologies, this invention proposes a novel intelligent power module.

[0007] To address the aforementioned technical problems, this invention provides an intelligent power module, comprising: a metal substrate layer, an insulating layer disposed on the metal substrate layer, a circuit layer disposed on the insulating layer, a HIVC drive logic circuit, a power switch circuit, a buffer circuit, an IPM upper bridge arm drive circuit, an IPM lower bridge arm drive circuit, an FPC drive circuit, an IPM switching transistor assembly, a PFC switching transistor assembly, an IPM operation protection circuit, a PFC operation protection circuit, and a protective layer disposed on the circuit layer. The HIVC drive logic circuit is electrically connected to the power switch circuit, the IPM upper bridge arm drive circuit, the IPM lower bridge arm drive circuit, and the FPC drive circuit, respectively. The IPM upper bridge arm drive circuit and the IPM lower bridge arm drive circuit are electrically connected to the IPM switching assembly, and the FPC drive circuit is electrically connected to the PFC switching assembly.

[0008] The IPM switching assembly includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in parallel. The IPM upper bridge arm drive circuit is connected to the first transistor, the second transistor, and the third transistor, respectively. The IPM lower bridge arm drive circuit is connected to the fourth transistor, the fifth transistor, and the sixth transistor, respectively.

[0009] The PFC switching assembly includes a seventh transistor and an eighth transistor connected in parallel, and the FPC driving circuit is connected to the seventh transistor and the eighth transistor respectively.

[0010] Preferably, the power switch circuit includes an input power supply Vin, a first resistor R100, a second resistor R200, a third resistor R300, a capacitor C1, a first MOSFET Q100, a second MOSFET Q200, a switch ENNOT, and an output terminal Vout; the input power supply Vin is connected to the first terminal of the first resistor R100 and the drain D of the first MOSFET Q100, and the second terminal of the first resistor R100 is connected to the first terminal of the third resistor R300, the gate G of the first MOSFET Q100, and the drain D of the second MOSFET Q200. The source S is connected, the second end of the third resistor R300 is connected to the first end of the capacitor C1 and the first end of the switch ENNOT, the second end of the capacitor C1 is grounded, the second end of the switch ENNOT is connected to the gate G of the second MOSFET and the first end of the second resistor R200, the drain D of the second MOSFET Q200 is grounded, the source S of the second MOSFET Q200 is connected to the first end of the second resistor R200, and the second end of the second resistor R200 is connected to the source S of the first MOSFET and the output terminal Vout.

[0011] Preferably, the HIVC drive logic circuit further includes a high-voltage side drive circuit and a low-voltage side drive circuit.

[0012] Preferably, the high-voltage side driving circuit includes a first Schmitt trigger, a first filter unit, a first potential shift circuit, a first NAND gate, a pulse generation circuit, a dv / dt filter circuit, a latch, a NOR gate, a second NAND gate, a third NAND gate, a UV filter circuit, MOSFET 1, MOSFET 2, MOSFET 3, MOSFET 4, a first current-limiting resistor, and a third current-limiting resistor; the output terminal of the first Schmitt trigger is connected to the input terminal of the first filter unit, the output terminal of the first filter unit is connected to the input terminal of the first potential shift circuit, and the output terminal of the potential shift circuit is connected to the first input terminal of the first NAND gate and the first input terminal of the second NAND gate, respectively. The output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the input terminal of the pulse generation circuit. The output terminal of the pulse generation circuit is connected to the gates of MOSFET 1 and MOSFET 2. The drain terminal of MOSFET 1 is connected to the input terminal of the dv / dt filter circuit 305. The drain terminal of MOSFET 2 is connected to the UV filter circuit. The output terminal of the dv / dt filter circuit is connected to the input terminal S of the latch. The output terminal of the UV filter circuit is connected to the input terminal R of the latch. The output terminal Q of the latch is connected to the input terminal of the NOR gate. The output terminal of the NOT gate is connected to the gates of MOSFET 3 and MOSFET 4.

[0013] The low-voltage side driving circuit includes a second Schmitt trigger, a second filter unit, a second potential shift circuit, a delay circuit, a comparator, MOSFET 5, and MOSFET 6. The output terminal of the second Schmitt trigger is connected to the input terminal of the second filter unit, the output terminal of the second filter unit is connected to the input terminal of the second potential shift circuit, the output terminal of the second potential shift circuit is connected to the input terminal of the third NAND gate, the output terminal of the third NAND gate is connected to the delay circuit, the output terminal of the delay circuit is connected to the input terminal of the comparator, and the output terminal of the comparator is connected to the gates of MOSFET 5 and MOSFET 6.

[0014] Preferably, the low-voltage side drive circuit further includes a low-voltage signal EN enable terminal, a low-voltage signal ITRIP terminal, a low-voltage signal IPM-VCC terminal, a low-voltage signal IPM-FAULT terminal, a low-voltage signal PFC-TRIP terminal, a low-voltage signal PFC-VCC terminal, and a low-voltage side drive PFCIN terminal.

[0015] Preferably, the low-voltage signal EN enable terminal includes a third Mit trigger, a third filter circuit, and a first enable drive circuit;

[0016] The low-voltage signal ITRIP terminal includes a fourth Mit trigger, a fourth filter circuit, and a third potential shift circuit.

[0017] The low-voltage signal IPM-VCC terminal includes a first switching circuit, a fifth Mit trigger, a fifth filtering circuit, a fourth potential shifting circuit, and a first power supply undervoltage protection circuit.

[0018] The low-voltage signal IPM-FAULT terminal includes a sixth det trigger, a first fault output circuit, and a sixth filter circuit.

[0019] The low-voltage signal PFC-FAULT terminal includes a seventh det trigger, a second fault output circuit 337, and a seventh filter circuit.

[0020] The low-voltage signal PFC-TRIP terminal includes an eighth Mitt trigger, an eighth filter circuit, and a fifth potential shift circuit.

[0021] The low-voltage signal PFC-VCC terminal includes a second switching circuit, a ninth Mit trigger, a ninth filter circuit, a second power supply undervoltage protection circuit, and a sixth potential shift circuit.

[0022] The low-voltage side drive PFCIN terminal includes a tenth Schmitt trigger, a tenth filter circuit, a seventh potential shift circuit, a second pulse generation circuit, a second delay circuit, a second comparator, MOSFET 7, and MOSFET 8. The output terminal of the tenth Schmitt trigger is interconnected with the input terminal of the tenth filter unit. The output terminal of the tenth filter unit is interconnected with the input terminal of the seventh potential shift circuit. The output terminal of the seventh potential shift circuit is interconnected with the second pulse generation circuit. The output terminal of the second delay circuit is interconnected with the input terminal of the second comparator. The output terminal of the second comparator 352 is connected to the gate of MOSFET 7 and MOSFET 8.

[0023] Preferably, the HIVC drive logic circuit is externally shorted by a power supply.

[0024] Compared with related technologies, this invention achieves insulation by placing an insulating layer between the metal substrate layer and the circuit layer. By integrating HIVC drive logic circuits, power switch circuits, buffer circuits, IPM upper bridge arm drive circuits, IPM lower bridge arm drive circuits, FPC drive circuits, IPM switching transistor assemblies, PFC switching transistor assemblies, IPM protection circuits, PFC protection circuits, and a protective layer on the circuit layer, this structure greatly improves the application capabilities of the HIVC drive logic circuits. For highly integrated high-voltage circuits, multiple functions can be used simultaneously, while also allowing for independent control of some functions, realizing both inverter and PFC functions. Furthermore, both functions are powered by independent power supplies, thereby improving the product's applicability in complex application environments and making it compatible with the future trend of complex, miniaturized, and intelligent multi-functional control systems. Attached Figure Description

[0025] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0026] Figure 1 This is a circuit diagram of the intelligent power module of the present invention;

[0027] Figure 2 This is a circuit diagram of the power switch of the present invention;

[0028] Figure 3 This is the topology diagram of the HVIC driver logic circuit;

[0029] Figure 4 This is a diagram of the internal circuit structure of the power module of the present invention;

[0030] Figure 5 This is a schematic diagram of the internal structure of the intelligent power module of the present invention;

[0031] Figure 6 This is an assembly diagram of the intelligent power module of the present invention. Detailed Implementation

[0032] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] The specific embodiments and examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0034] Please refer to Figure 1-6 As shown, the present invention provides an intelligent power module 100, comprising: a metal substrate layer 603, an insulating layer 602 disposed on the metal substrate layer 603, a circuit layer 601 disposed on the insulating layer 602, a HIVC drive logic circuit 10, a cache circuit 101, an IPM upper bridge arm drive circuit 102, an IPM lower bridge arm drive circuit 103, an FPC drive circuit 104, an IPM switch assembly 105, a PFC switch assembly 106, an IPM operation protection circuit 107, a PFC operation protection circuit 108, a power switch circuit 109, and a protective layer 600 disposed on the circuit layer.

[0035] The IPM switching assembly 107 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6 connected in parallel. The IPM upper bridge arm drive circuit 102 is connected to the first transistor Q1, the second transistor Q2, and the third transistor Q3, respectively. The IPM lower bridge arm drive circuit 103 is connected to the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6, respectively.

[0036] The PFC switch assembly 106 includes a seventh transistor Q7 and an eighth transistor Q8 connected in parallel, and the FPC drive circuit 104 is connected to the seventh transistor Q7 and the eighth transistor Q8 respectively.

[0037] Specifically, by placing the insulating layer 602 between the metal substrate layer 603 and the circuit layer 601, an insulating effect is achieved. The circuit layer 601 integrates the HIVC drive logic circuit 10, the buffer circuit 101, the IPM upper bridge arm drive circuit 102, the IPM lower bridge arm drive circuit 103, the FPC drive circuit 104, the IPM switch assembly 105, the PFC switch assembly 106, the IPM operation protection circuit 107, the PFC operation protection circuit 108, the power switch circuit 109, and the protective layer 600. This structure greatly enhances the application capabilities of the HIVC drive logic circuit 10. It allows for the independent control of multiple functions within a highly integrated high-voltage circuit, enabling both inverter and PFC functions to be used independently. Furthermore, the two functions are powered by independent power supplies, improving the product's applicability in complex application environments and making it compatible with the future trend of complex, miniaturized, and intelligent multi-functional control systems.

[0038] It should be noted that the intelligent power module 100 integrates PFC and IPM functional parts, and the high-voltage devices achieve driving, undervoltage protection and other functions through logical relationships. The HIVC drive logic circuit 10 is used to receive and feed back the PWM input control signal from the peripheral main control board MCU to drive the IPM upper bridge arm drive circuit 102, the lower bridge arm drive circuit 103, and the PFC drive circuit 104. The IPM switching component works to achieve the purpose of motor driving, and the PFC switching component works to achieve the purpose of voltage boosting and stabilization. Meanwhile, the HIVC drive logic circuit 10 is internally equipped with control voltage undervoltage protection (UV), overtemperature protection (OT), overcurrent protection (OC), and short circuit protection (SC). When a fault occurs during module operation, it can achieve interlocking between the upper and lower bridges and cut off the power signal to prevent product burnout and ensure product stability and reliability. The buffer circuit 101 receives the MCU signal from the peripheral circuit, filters and amplifies it, and then outputs it to the corresponding switching transistor drive circuit. The IPM upper bridge arm drive circuit 102 includes a bootstrap circuit, undervoltage protection circuit, UPU drive circuit, UPV drive circuit, and UPW drive circuit. The I and the IPM lower bridge arm drive circuit 103 include UNU drive circuit, UNV drive circuit, and UNW drive circuit. The IPM intelligent power module PFC drive circuit includes the PFC drive circuit. The IPM protection circuit 107 monitors the operating status of the switching transistors Q1, Q2, Q3, Q4, Q5, and Q6. When a fault occurs, the ITRIP detects an abnormal signal and feeds it back to the MCU, which immediately takes action, cutting off the signal. The FAULT signal transitions from a high level to a low level to protect the module. When the system detects abnormal signals for undervoltage protection (UV), overtemperature protection (OT), overcurrent protection (OC), or short circuit protection (SC), the FAULT signal transitions from a high level to a low level, feeding the signal back to the MCU for immediate action. When the signal is cut off, the module stops working. The PFC protection circuit 108 is responsible for monitoring the working status of the Q7 switch in the module. When a fault occurs, PFCTRIP detects an abnormal signal and feeds the signal back to the MCU, which immediately takes action to cut off the signal. The PFC-FAULT signal changes from a high level to a low level to achieve the function of protecting the module. When the system detects abnormal overcurrent protection (OC) or short circuit protection (SC) signals, the PFC-FAULT signal changes from a high level to a low level and feeds the signal back to the MCU, which immediately takes action to cut off the signal, and the module stops working.

[0039] Furthermore, the power switch circuit 109 includes an input power supply Vin, a first resistor R100, a second resistor R200, a third resistor R300, a capacitor C1, a first MOSFET Q100, a second MOSFET Q200, a switch ENNOT, and an output terminal Vout. The input power supply Vin is connected to the first terminal of the first resistor R100 and the drain D of the first MOSFET Q100. The second terminal of the first resistor R100 is connected to the first terminal of the third resistor R300, the gate G of the first MOSFET Q100, and the second MOSFET Q200. The source S of the first MOSFET is connected to the first terminal of the second MOSFET. The second terminal of the third resistor R300 is connected to the first terminal of the capacitor C1 and the first terminal of the switch ENNOT. The second terminal of the capacitor C1 is grounded. The second terminal of the switch ENNOT is connected to the gate G of the second MOSFET and the first terminal of the second resistor R200. The drain D of the second MOSFET Q200 is grounded. The source S of the second MOSFET Q200 is connected to the first terminal of the second resistor R200. The second terminal of the second resistor R200 is connected to the source S of the first MOSFET and the output terminal Vout.

[0040] The above structure, through the selection of an independent power supply switching circuit, allows for the free selection of IPM or PFC function circuits when using intelligent power modules, depending on application requirements. Switching circuit operation: In the initial power-on state, the input power Vin charges capacitor C100 to the power supply voltage via resistors R100 and R300. MOSFETs Q100 and Q200 are cut off, and Vout has no output. When the circuit needs to be powered on, an ENNOT signal is given, causing the switch to close. The voltage across capacitor C100 is applied to the gate of the NMOS transistor, causing Q200 to quickly saturate and conduct. The gate potential of Q100 is pulled down to near 0V, and Q100 also quickly conducts and saturates, resulting in a voltage output from Vout. At this time, Vout is applied to the gate of NMOS transistor Q200 via resistor R200, maintaining Q200's conduction and forming a self-locking loop. If ENNOT is closed at this time, Vout will continue to charge capacitor C100, without affecting the circuit's power-on state. If ENNOT is off, capacitor C100 discharges to near 0V through resistor R3 and the drain-sink (DS) junction of Q200, preparing the circuit for shutdown. When the circuit needs to shut down, the ENNOT signal is disconnected. Due to the effect of capacitor C100, the gate potential of NMOS transistor Q200 is pulled low to a low level, and Q200 is turned off. After Q200 is turned off, the gate potential of the PMOS transistor rises to a high level, Q100 is turned off, and there is no output Vout. At this time, capacitor C100 begins to slowly charge again through resistors R100 and R300 until it approaches the input power supply voltage, restoring the circuit to its initial power-on state.

[0041] In this embodiment, the HIVC driving logic circuit 10 further includes a high-voltage side driving circuit 11 and a low-voltage side driving circuit 12.

[0042] Furthermore, the high-voltage side drive circuit includes a first Schmitt trigger 300, a first filter unit 301, a first potential shift circuit 302, a first NAND gate 303, a pulse generation circuit 304, a dv / dt filter circuit 305, a latch 306, a NOR gate 307, a second NAND gate 308, a third NAND gate 309, a UV filter circuit 311, MOSFETs 1, 2, 3, and 4, a first current-limiting resistor RS1, and a first current-limiting resistor RS2. The output terminal of the first Schmitt trigger 300 is connected to the input terminal of the first filter unit 301, the output terminal of the first filter unit 301 is connected to the input terminal of the first potential shift circuit 302, and the output terminal of the potential shift circuit 302 is connected to the first input terminal of the first NAND gate 303 and the second NAND gate 308, respectively. The first input terminal is connected, the output terminal of the second NAND gate 308 is connected to the second input terminal of the first NAND gate 303, the output terminal of the first NAND gate 303 is connected to the input terminal of the pulse generation circuit 304, the output terminal of the pulse generation circuit 304 is connected to the gates of MOS transistor 1 and MOS transistor 2, the drain terminal of MOS transistor 1 is connected to the input terminal of the dv / dt filter circuit 305, the drain terminal of MOS transistor 2 is connected to the UV filter circuit 311, the output terminal of the dv / dt filter circuit 305 is connected to the input terminal S of the latch 306, the output terminal of the UV filter circuit 311 is connected to the input terminal R of the latch 306, the output terminal Q of the latch 306 is connected to the input terminal of the NOR gate 307, and the output terminal of the NOT gate 307 is connected to the gates of MOS transistor 3 and MOS transistor 4.

[0043] The signal transmission process of the above structure is as follows: The first Mitt trigger 300 filters the PWM control signal output by the peripheral main control board MCU and outputs it stably to the subsequent first filtering unit 301. The first filtering unit 301 performs high-frequency, narrow-wave filtering on the received control signal and inverts the control signal before outputting it to the first potential shift circuit 302. The first potential shift circuit 302 compensates for the coupled signal when the amplitude of the coupled signal is large, as this DC change will interfere with the interface voltage, and adds a DC level adjustment function, thereby enabling the signal to be stably output to the first NAND gate 303, the second NAND gate 308, and the third NAND gate 309. The pulse generation circuit 304 outputs the high-level signal received from the first NAND gate 303 to the first NAND gate 309. The gates of MOSFETs 1 and 2 are driven to conduct, and the gate and source of the MOSFETs are shorted to achieve unidirectional conduction. The voltage is output to VB through the first current-limiting resistor RS1 and the first current-limiting resistor RS2. The DV / DT filter circuit 305 is used to receive the drain voltage of MOSFETs 1 and 2 and filter and rectify it to stabilize the voltage. The UV filter circuit 311 receives the voltage level signal after the first current-limiting resistor RS1 and the first current-limiting resistor RS2 and filters and rectifyes it. The latch 306 is used to receive the signal from the DV / DT filter circuit 305 and the UV filter 311 and temporarily store it, so that the level signal output is synchronized. The NOR logic gate 307 is used to receive the signal from the latch 306 and compares the high and low levels of the input to control the driving and turning-on status of MOSFETs 3 and 4.

[0044] The low-voltage side driving circuit includes a second Schmitt trigger 312, a second filter unit 313, a second potential shift circuit 314, a delay circuit 310, a comparator 315, a MOSFET 5, and a MOSFET 6. The output terminal of the second Schmitt trigger 312 is connected to the input terminal of the second filter unit 313, the output terminal of the second filter unit 313 is connected to the input terminal of the second potential shift circuit 314, the output terminal of the second potential shift circuit 314 is connected to the input terminal of the third NAND gate 309, the output terminal of the third NAND gate 309 is connected to the delay circuit 310, the output terminal of the delay circuit 310 is connected to the input terminal of the comparator 315, and the output terminal of the comparator 315 is connected to the gates of the MOSFET 5 and the MOSFET 6.

[0045] The signal transmission process of the above structure is as follows: The second Mitt trigger 312 filters the PWM control signal output by the peripheral main control board MCU and outputs it stably to the subsequent second filtering unit 313. The second filtering unit 313 performs high-frequency, narrow-wave filtering on the received control signal, inverts the control signal, and outputs it to the second potential shift circuit 314, and then to the second NAND gate 308 and the third NAND gate 309. The delay circuit 310 delays the output of the control signal from the third NAND gate 309 to avoid short-circuit faults in the MOS transistors 5 and 6 of the power inverter bridge circuit caused by the simultaneous conduction of the lower bridge arm power transistor and the upper bridge arm power transistor of the high-voltage side drive circuit.

[0046] In this embodiment, the low-voltage side drive circuit 12 further includes a low-voltage signal EN enable terminal, a low-voltage signal ITRIP terminal, a low-voltage signal IPM-VCC terminal, a low-voltage signal IPM-FAULT terminal, a low-voltage signal PFC-TRIP terminal, a low-voltage signal PFC-VCC terminal, and a low-voltage side drive PFCIN terminal.

[0047] More preferably, the low-voltage signal EN enable terminal includes a third Mit trigger 316, a third filter circuit 317, and a first enable drive circuit 318; it is active high, and when the control system malfunctions, the high level is converted to a low level output.

[0048] The low-voltage signal ITRIP terminal includes a fourth Mitt trigger 319, a fourth filter circuit 320, and a third potential shift circuit 321; it is active low, and when the control system malfunctions, the low level is converted to a high level output.

[0049] The low-voltage signal IPM-VCC terminal includes a first switching circuit 325, a fifth Mit trigger 326, a fifth filtering circuit 327, a fourth potential shifting circuit 328, and a first power supply undervoltage protection circuit 329. In a conventional drive control system, if the power supply is lower than 12.5V (typical value), the module will issue an undervoltage protection signal, triggering the Fault terminal through the fault control system, resulting in a low-level output and the module stopping operation.

[0050] The low-voltage signal IPM-FAULT terminal includes a sixth detent trigger 330, a first fault output circuit 331, and a sixth filter circuit 332; it is active high, and when the control system 354 malfunctions, the high level is converted to a low level output.

[0051] The low-voltage signal PFC-FAULT terminal includes a seventh Mit trigger 336, a second fault output circuit 337, and a seventh filter circuit 338; it is active high, and when the control system 353 malfunctions, the high level is converted to a low level output.

[0052] The low-voltage signal PFC-TRIP terminal includes an eighth Mitt trigger 339, an eighth filter circuit 340, and a fifth potential shift circuit 341; it is active low, and when a fault occurs in the control system, the low level is converted to a high level output.

[0053] The low-voltage signal PFC-VCC terminal includes a second switching circuit 343, a ninth Mit trigger 344, a ninth filter circuit 327, a second power supply undervoltage protection circuit 345, and a sixth potential shift circuit 346. In a conventional drive control system, if the power supply is lower than 12.5V (typical value), the module will issue an undervoltage protection signal, triggering the Fault terminal through the fault control system, resulting in a low-level output and the module stopping operation.

[0054] The low-voltage side drive PFCIN terminal includes a tenth Schmitt trigger 347, a tenth filter circuit 348, a seventh potential shift circuit 349, a second pulse generation circuit 350, a second delay circuit 351, a second comparator 352, a MOSFET 7, and a MOSFET 8. The output terminal of the tenth Schmitt trigger 347 is interconnected with the input terminal of the tenth filter unit 348. The output terminal of the tenth filter unit 348 is interconnected with the input terminal of the seventh potential shift circuit 349. The output terminal of the seventh potential shift circuit 349 is interconnected with the second pulse generation circuit 350. The output terminal of the second delay circuit 351 is interconnected with the input terminal of the second comparator 352. The output terminal of the second comparator 352 is connected to the gate of the MOSFET 7 and the MOSFET 8.

[0055] In this embodiment, the intelligent power module 100 internally comprises a power section and a drive control section. 407 consists of six freewheeling diodes in the power section of the IPM, 408 consists of six transistors in the power section of the IPM, and 409 is a switching power device in the PFC section. 410 is the HVIC of the drive control section, with seven channels: six channels for inversion and one channel for PFC. These two functions are powered by independent power supplies, allowing users to select only one function based on their operating environment.

[0056] In this embodiment, the intelligent power module 100 is a seven-channel HVIC, including a six-channel IPM functional section circuit 801 and a one-channel PFC functional section circuit 802. Circuit 801 has an independent power supply 1 803, a power selection port 804, and other function ports A. Circuit 802 has an independent power supply 2 805, a power selection port 806, and other function ports B. It is worth noting that when using this HVIC, the user can short-circuit the power supply externally according to the external motherboard design.

[0057] Compared with related technologies, this invention achieves insulation by placing an insulating layer between the metal substrate layer and the circuit layer. By integrating HIVC drive logic circuits, power switch circuits, buffer circuits, IPM upper bridge arm drive circuits, IPM lower bridge arm drive circuits, FPC drive circuits, IPM switching transistor assemblies, PFC switching transistor assemblies, IPM protection circuits, PFC protection circuits, and a protective layer on the circuit layer, this structure greatly improves the application capabilities of the HIVC drive logic circuits. For highly integrated high-voltage circuits, multiple functions can be used simultaneously, while also allowing for independent control of some functions, realizing both inverter and PFC functions. Furthermore, both functions are powered by independent power supplies, thereby improving the product's applicability in complex application environments and making it compatible with the future trend of complex, miniaturized, and intelligent multi-functional control systems.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any alterations, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A smart power module, characterized in that, include: The system comprises a metal substrate, an insulating layer disposed on the metal substrate, a circuit layer disposed on the insulating layer, a HIVC drive logic circuit, a power switch circuit, a buffer circuit, an IPM upper bridge arm drive circuit, an IPM lower bridge arm drive circuit, a PFC drive circuit, an IPM switch assembly, a PFC switch assembly, an IPM operation protection circuit, a PFC operation protection circuit, and a protective layer disposed on the circuit layer. The HIVC drive logic circuit is electrically connected to the power switch circuit, the IPM upper bridge arm drive circuit, the IPM lower bridge arm drive circuit, and the PFC drive circuit, respectively. The IPM upper bridge arm drive circuit and the IPM lower bridge arm drive circuit are electrically connected to the IPM switch assembly, and the PFC drive circuit is electrically connected to the PFC switch assembly. The IPM switching assembly includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in parallel. The IPM upper bridge arm drive circuit is connected to the first transistor, the second transistor, and the third transistor, respectively. The IPM lower bridge arm drive circuit is connected to the fourth transistor, the fifth transistor, and the sixth transistor, respectively. The PFC switching assembly includes a seventh transistor, a seventh diode, and an eighth diode. The PFC driving circuit is connected to the base of the seventh transistor, the emitter of the seventh transistor is connected to the anode of the seventh diode, the collector of the seventh transistor is connected to the cathode of the seventh diode and the anode of the eighth diode, and the cathode of the eighth diode is used to connect to the DC-BUS port. The power switch circuit includes an input power supply Vin, a first resistor R100, a second resistor R200, a third resistor R300, a capacitor C1, a first MOSFET Q100, a second MOSFET Q200, a switch ENNOT, and an output terminal Vout. The input power supply Vin is connected to the first terminal of the first resistor R100 and the source S of the first MOSFET Q100. The second terminal of the first resistor R100 is connected to the first terminal of the third resistor R300, the gate G of the first MOSFET Q100, and the source of the second MOSFET Q200. The S-connection is established, with the second terminal of the third resistor R300 connected to the first terminal of the capacitor C1 and the first terminal of the switch ENNOT. The second terminal of the capacitor C1 is grounded. The second terminal of the switch ENNOT is connected to the gate G of the second MOSFET and the first terminal of the second resistor R200. The drain D of the second MOSFET Q200 is grounded. The source S of the second MOSFET Q200 is connected to the first terminal of the second resistor R200. The second terminal of the second resistor R200 is connected to the drain D of the first MOSFET and the output terminal Vout.

2. The intelligent power module as described in claim 1, characterized in that, The HIVC driving logic circuit also includes a high-voltage side driving circuit and a low-voltage side driving circuit.

3. The intelligent power module as described in claim 2, characterized in that, The high-voltage side drive circuit includes a first Schmitt trigger, a first filter unit, a first potential shift circuit, a first NAND gate, a pulse generation circuit, a dv / dt filter circuit, a latch, a NOR gate, a second NAND gate, a third NAND gate, a UV filter circuit, MOSFET 1, MOSFET 2, MOSFET 3, MOSFET 4, a first current-limiting resistor, and a first current-limiting resistor. The output of the first Schmitt trigger is connected to the input of the first filter unit. The output of the first filter unit is connected to the input of the first potential shift circuit. The output of the potential shift circuit is connected to the first input terminal of the first NAND gate and the first input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate. The output of the first NAND gate is connected to the input of the pulse generation circuit. The output of the pulse generation circuit is connected to the gates of MOS transistor 1 and MOS transistor 2. The drain of MOS transistor 1 is connected to the input of the dv / dt filter circuit 305. The drain of MOS transistor 2 is connected to the UV filter circuit. The output of the dv / dt filter circuit is connected to the input S of the latch. The output of the UV filter circuit is connected to the input R of the latch. The output Q of the latch is connected to the input of the NOR gate. The output of the NOT gate is connected to the gates of MOS transistor 3 and MOS transistor 4. The low-voltage side driving circuit includes a second Schmitt trigger, a second filter unit, a second potential shift circuit, a delay circuit, a comparator, MOSFET 5, and MOSFET 6. The output of the second Schmitt trigger is connected to the input of the second filter unit, the output of the second filter unit is connected to the input of the second potential shift circuit, the output of the second potential shift circuit is connected to the input of the third NAND gate, the output of the third NAND gate is connected to the delay circuit, the output of the delay circuit is connected to the input of the comparator, and the output of the comparator is connected to the gates of MOSFET 5 and MOSFET 6.

4. The intelligent power module as described in claim 3, characterized in that, The low-voltage side drive circuit also includes a low-voltage signal EN enable terminal, a low-voltage signal ITRIP terminal, a low-voltage signal IPM-VCC terminal, a low-voltage signal IPM-FAULT terminal, a low-voltage signal PFC-TRIP terminal, a low-voltage signal PFC-VCC terminal, a low-voltage signal PFC-FAULT terminal, and a low-voltage side drive PFCIN terminal.

5. The intelligent power module as described in claim 4, characterized in that, The low-voltage signal EN enable terminal includes a third Schmitt trigger, a third filter circuit, and a first enable drive circuit; The low-voltage signal ITRIP terminal includes a fourth Schmitt trigger, a fourth filter circuit, and a third potential shift circuit. The low-voltage signal IPM-VCC terminal includes a first switching circuit, a fifth Schmitt trigger, a fifth filtering circuit, a fourth potential shifting circuit, and a first power supply undervoltage protection circuit. The low-voltage signal IPM-FAULT terminal includes a sixth Schmitt trigger, a first fault output circuit, and a sixth filter circuit. The low-voltage signal PFC-FAULT terminal includes a seventh Schmitt trigger, a second fault output circuit 337, and a seventh filter circuit. The low-voltage signal PFC-TRIP terminal includes an eighth Schmitt trigger, an eighth filter circuit, and a fifth potential shift circuit. The low-voltage signal PFC-VCC terminal includes a second switching circuit, a ninth Schmitt trigger, a ninth filter circuit, a second power supply undervoltage protection circuit, and a sixth potential shift circuit. The low-voltage side drive PFCIN terminal includes a tenth Schmitt trigger, a tenth filter circuit, a seventh potential shift circuit, a second pulse generation circuit, a second delay circuit, a second comparator, MOSFET 7, and MOSFET 8. The output terminal of the tenth Schmitt trigger is interconnected with the input terminal of the tenth filter circuit. The output terminal of the tenth filter circuit is interconnected with the input terminal of the seventh potential shift circuit. The output terminal of the seventh potential shift circuit is interconnected with the second pulse generation circuit. The output terminal of the second delay circuit is interconnected with the input terminal of the second comparator. The output terminal of the second comparator 352 is connected to the gate of MOSFET 7 and MOSFET 8.

6. The intelligent power module as described in claim 1, characterized in that, The HIVC drive logic circuit is externally shorted by a power supply.

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