Current steering digital-to-analog converter and method for improving high frequency linearity thereof

Abstract

The application provides a current steering digital-to-analog converter and a high-frequency linearity improvement method thereof, wherein a common-source and common-gate stage transistor is additionally connected in series between a tail current source transistor and a switch pair transistor, and an effective common-source and common-gate stage transistor is additionally connected in series between the switch pair transistor and a differential analog output end of the current steering digital-to-analog converter, so that the output impedance of the current switch unit can be increased, and the nonlinearity caused by the input digital modulation effect due to the limited output impedance can be reduced; meanwhile, a direct current bias current source is used to provide a direct current bias current for the effective common-source and common-gate stage transistor, so that the effective common-source and common-gate stage transistor is always kept open, the nonlinearity influence related to the input digital code caused by the parasitic capacitance when the effective common-source and common-gate stage transistor is completely disconnected can be avoided, and the linearity of the current switch unit of the current steering digital-to-analog converter and the current steering digital-to-analog converter under high frequency can be improved.

Description

Technical Field

[0001] This invention relates to the field of digital-to-analog converter technology, and in particular to a current-driven digital-to-analog converter and a method for improving its high-frequency linearity. Background Technology

[0002] A current-controlled digital-to-analog converter (DC-Analog Converter) consists of multiple current switching units. Each current switching unit comprises a pair of switches and a tail current source. A pair of differential digital signals, obtained from the input digital signal of the DC-Analog Converter, controls the opening and closing of the two switches, thus determining which of the two switches the tail current source flows through. The differential output of the DC-Analog Converter is formed by the parallel connection of the outputs of multiple current switching units, each typically driving a load resistor. Therefore, the impedance seen at the output is the parallel combination of the output impedance and the load resistor. Since the magnitude of the output impedance depends on the number of current switching units connected in parallel and is related to the input digital signal, and because the impedance of an ideal current source is infinite, while the impedance of a real current source cannot be infinite, the total finite output impedance of the DC-Analog Converter affects its linearity, leading to harmonic distortion.

[0003] Currently, a common-source cascode structure is typically used to increase the overall output impedance of current-controlled digital-to-analog converters (DC-Analog Converters). The improved cascode structure increases the output resistance and reduces the impact of parasitic capacitance from other transistors on dynamic performance. However, the added cascode transistors also introduce their own parasitic capacitance. High-speed changing input digital data can be directly fed to the differential analog output through this parasitic capacitance, generating nonlinearity related to the input digital data. This becomes the main limitation on the output impedance of the current switching unit of the current-controlled DC-Analog Converter at high frequencies.

[0004] Therefore, there is an urgent need for a technical solution to reduce the nonlinear effects related to the input digital data caused by the parasitic capacitance of the cascode transistor in the current-driven digital-to-analog converter. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a current-controlled digital-to-analog converter (DAC) technical solution. For the current switching unit of the DAC, a common-source cascode transistor (CRT) is added in series between the tail current source transistor and the switching pair. An effective CRT is also added in series between the switching pair and the differential analog output terminal of the DAC. This increases the output impedance of the current switching unit, thereby reducing the nonlinearity caused by the input digital modulation effect due to the limited output impedance. Simultaneously, a DC bias current is provided to the effective CRT, ensuring that the effective CRT remains on at all times, thus reducing the nonlinear effects related to the input digital signal caused by the parasitic capacitance of the effective CRT.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A current-driven digital-to-analog converter includes a tail current source transistor, a common-source cascode transistor, a first switch, a second switch, a first effective common-source cascode transistor, a second effective common-source cascode transistor, a DC bias current source, and two load resistors. The source of the tail current source transistor is grounded, its gate is connected to a first bias voltage, its drain is connected to the source of the common-source cascode transistor, its gate is connected to a second bias voltage, its drain is connected to the source of the first switch, its gate is connected to a first digital signal, its drain is connected to the source of the first effective common-source cascode transistor, its source is also connected to a first output terminal of the DC bias current source, its gate is connected to a third bias voltage, and its drain is connected to the operating voltage via one of the load resistors connected in series. The differential analog output positive terminal of the current switching unit of the current-driven digital-to-analog converter is connected to the source of the first switching transistor. The gate of the second switching transistor is connected to the second digital signal. The drain of the second switching transistor is connected to the source of the second effective cascode transistor. The source of the second effective cascode transistor is also connected to the second output terminal of the DC bias current source. The gate of the second effective cascode transistor is connected to the third bias voltage. The drain of the second effective cascode transistor is connected to the operating voltage via another load resistor connected in series. The drain of the second effective cascode transistor is the differential analog output negative terminal of the current switching unit of the current-driven digital-to-analog converter. The DC bias current source provides a first DC bias current to the first effective cascode transistor and a second DC bias current to the second effective cascode transistor, so that the first effective cascode transistor and the second effective cascode transistor are always turned on.

[0008] Optionally, the tail current source transistor, the common-source cascode transistor, the first switch, the second switch, the first effective common-source cascode transistor, and the second effective common-source cascode transistor are all NMOS transistors.

[0009] Optionally, the parameters of the first switch are the same as those of the second switch, and the parameters of the first effective cascode transistor are the same as those of the second effective cascode transistor.

[0010] Optionally, the size of the first switch is smaller than the size of the first effective cascode transistor.

[0011] Optionally, the DC bias current source includes a buffer amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the first bias voltage, the drain of the first NMOS transistor is connected to the source of the third NMOS transistor, the gate of the third NMOS transistor is connected to the second bias voltage, the drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the output terminal of the buffer amplifier, and the non-inverting input terminal of the buffer amplifier is connected to the fourth bias voltage. The buffer amplifier has its inverting input connected to its output. The source of the second NMOS transistor is grounded, and its gate is connected to the first bias voltage. The drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor, and its gate is connected to the second bias voltage. The drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, and its gate is connected to the output of the buffer amplifier. The drain of the fifth NMOS transistor is the first output of the DC bias current source, and the drain of the sixth NMOS transistor is the second output of the DC bias current source.

[0012] Optionally, the parameters of the first NMOS transistor are the same as those of the second NMOS transistor, the parameters of the third NMOS transistor are the same as those of the fourth NMOS transistor, and the parameters of the fifth NMOS transistor are the same as those of the sixth NMOS transistor.

[0013] Optionally, the size of the first NMOS transistor is larger than the size of the third NMOS transistor, and the size of the third NMOS transistor is larger than the size of the fifth NMOS transistor.

[0014] A method for improving the high-frequency linearity of a current-driven digital-to-analog converter includes:

[0015] For at least one current switching unit of the current-steering digital-to-analog converter, a common-source cascode transistor is added in series between the tail current source transistor and the switching pair, and an effective common-source cascode transistor is added in series between the switching pair and the differential analog output terminal of the current-steering digital-to-analog converter to increase the output impedance of the current switching unit.

[0016] For at least one current switching unit of the current-controlled digital-to-analog converter, a DC bias current is provided to the effective cascode transistor so that the effective cascode transistor remains on at all times.

[0017] As described above, the current-driven digital-to-analog converter and its high-frequency linearity improvement method provided by the present invention have at least the following beneficial effects:

[0018] Adding a common-source cascode transistor in series between the tail current source transistor and the first and second switching transistors, adding a first effective common-source cascode transistor in series between the first switching transistor and the positive terminal of the differential analog output of the current-steering digital-to-analog converter, and adding a second effective common-source cascode transistor in series between the second switching transistor and the negative terminal of the differential analog output of the current-steering digital-to-analog converter, can effectively increase the output impedance of the current switching unit and reduce the nonlinearity caused by the input digital modulation effect due to the limited output impedance. At the same time, by providing a first DC bias current to the first effective common-source cascode transistor and a second DC bias current to the second effective common-source cascode transistor through a DC bias current source, the first and second effective common-source cascode transistors are kept on at all times. This can effectively avoid the nonlinear effects related to the input digital caused by the parasitic capacitance when the first and second effective common-source cascode transistors are completely off, and improve the linearity of the current-steering digital-to-analog converter. Attached Figure Description

[0019] Figure 1 The diagram shows the schematic of a traditional current-controlled digital-to-analog converter current switching unit.

[0020] Figure 2 The diagram shows the output impedance of a current-controlled digital-to-analog converter, which is a thermometer decoding structure.

[0021] Figure 3 The diagram shows a schematic of a conventional current-driven digital-to-analog converter core unit circuit.

[0022] Figure 4 Displayed as Figure 3 The amplitude-frequency curve of the output impedance of the core unit of the medium current-controlled digital-to-analog converter as a function of signal frequency.

[0023] Figure 5 This diagram shows the schematic of the core unit circuit of a common-source, common-gate current-steering digital-to-analog converter.

[0024] Figure 6 This shows a partial schematic diagram of the current-driven digital-to-analog converter in this invention.

[0025] Figure 7 Displayed as Figure 6 Schematic diagram of a DC bias current source.

[0026] Figure 8 Displayed as Figure 6 A schematic diagram of the dynamic parasitic capacitance of the medium current switching unit. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0029] As described in the background section, the current-controlled digital-to-analog converter consists of multiple current switching units, each with the following structure: Figure 1 As shown, it consists of a pair of switches S1 and S2 and a tail current source I. O The system consists of a pair of differential digital signals DN / DP obtained from the input digital signal of the current-steering digital-to-analog converter, which control the opening and closing of switches S1 and S2 respectively, thereby determining the tail current source I. O It flows through switch S1 or switch S2. For example... Figure 1 As shown, the differential output terminal V of the current-controlled digital-to-analog converter OUT It consists of multiple current switching units connected in parallel at their output terminals, and each of them typically drives a load resistor R. L Load resistance R L One end is connected to the working voltage V CC Two load resistors R L The other end is the differential output terminal V OUT positive terminal OUT P OUT terminal N Therefore, from the differential output terminal VOUT The impedance you see is the output impedance Z. DAC With load resistance R L The parallel connection, due to the output impedance Z DAC The size depends on the number of current switching units connected in parallel and is related to the input digital of the current-steering digital-to-analog converter. Ideal tail current source I O The impedance is infinite, while the actual tail current source I O The impedance cannot be infinite, such as Figure 1 As shown, tail current source I O impedance Z O Including equivalent resistance R O and equivalent capacitance C O Two parts, whose impedance Z O The total finite output impedance of the current-controlled digital-to-analog converter affects its linearity, leading to harmonic distortion.

[0030] On the one hand, with Figure 2 Taking the output impedance of a current-controlled digital-to-analog converter in a thermometer decoding structure as an example, the total number of its current switching units is N. Figure 2 This shows the relationship between its output impedance and the input signal, where x represents the digital input code, Zo represents the output impedance of the current switching unit (including the equivalent capacitance Co and the equivalent resistance Ro), and Z... L Load resistor R L The impedance. Based on the circuit structure, the differential output voltage of the current-controlled digital-to-analog converter can be calculated as:

[0031]

[0032] Further expansion of formula (1):

[0033]

[0034] Expanding formula (2) using Taylor series at x = 0, we get:

[0035]

[0036] After expanding by a power series, we obtain the following based on the third harmonic distortion formula:

[0037]

[0038] For a differential output current-controlled digital-to-analog converter (DAC), its main output harmonic component is the third harmonic. Therefore, the dynamic error of the current-controlled DAC due to its limited output impedance is reflected in SFDR (Spurious Free Dynamic Range).

[0039]

[0040] At low frequencies, the output impedance of a current-controlled digital-to-analog converter is mainly determined by the equivalent resistance Ro, i.e.:

[0041]

[0042] As can be seen from formula (6), at low frequencies, the effect of the output impedance of the current-controlled digital-to-analog converter on SFDR does not change with the signal frequency. From this perspective, the effect of the finite output impedance on the current-controlled digital-to-analog converter at low frequencies can be attributed to the static error INL (Integral Nonlinearity). The formula for the effect of the finite output resistance on INL at low frequencies is:

[0043]

[0044] As can be seen from formula (7), for a 12-bit resolution current-controlled digital-to-analog converter, when the load resistance R L When the resistance is 25Ω, the equivalent resistance Ro required to obtain 1LSB of INL is approximately 100MΩ.

[0045] At higher frequencies, the output impedance of a current-controlled digital-to-analog converter is primarily determined by its equivalent capacitance Co. Therefore:

[0046]

[0047] In formula (8) f in This represents the input signal frequency. As can be seen from formula (8), at high frequencies, SFDR decreases at a rate of -40dB per frequency band as the input signal frequency increases. To improve the dynamic performance of the current-controlled digital-to-analog converter, the value of the equivalent capacitance (or parasitic capacitance) Co of the tail current source needs to be reduced.

[0048] On the other hand, with Figure 3 The circuit shown is an example of a conventional current-controlled digital-to-analog converter core unit circuit. Figure 1 Switches S1 and S2 in Figure 3 It is implemented using NMOS transistors N1 and N2. Figure 1 Tail current source I O exist Figure 3 The implementation uses NMOS transistor N3, and assumes that the switching transistor N... l The output impedances of N2 and N2 are respectively r o1 and r o2 r o1 =r o2 The transconductance is g. m The output impedance of the tail current source transistor N3 is r o3The parasitic capacitance at the common source point A of the switching pair is C. A The parasitic capacitance C at point A A This includes the parasitic capacitance of transistor N3 and the interconnection capacitance between them. When the switching transistor N... l When the circuit is turned on, the output impedance of the switching current unit is Z. DAC(CELL) for:

[0049]

[0050] The output impedance Z of the switching current unit can be plotted according to formula (9). DAC(CELL) With input signal f in The amplitude-frequency curve of frequency change is as follows Figure 4 As shown, from Figure 4 The output impedance Z of the current-controlled digital-to-analog converter switching current unit can be seen. DAC(CELL) There is a pole l / (2πr) o3 C A When the signal frequency is greater than this pole, the output impedance Z DAC(CELL) As the SFDR decreases, it gradually worsens. Although parasitic capacitance of interconnects can be reduced through proper layout, its effect is limited.

[0051] Meanwhile, with advancements in manufacturing technology, the channel length modulation effect has further significantly limited the output impedance r of a single transistor. o Therefore, in order to improve the accuracy and dynamic performance of the current-steering digital-to-analog converter, it is necessary to increase the output impedance Z of the core unit of the current-steering digital-to-analog converter. DAC(CELL) .

[0052] Currently, a common-source cascode structure is typically used to increase the overall output impedance of current-driven digital-to-analog converters, such as... Figure 5 As shown, in the current switching unit, the drain of the switching pair NMOS transistors N1 and N2 is connected to the differential output terminal V. OUT An NMOS transistor N5 and N6 are connected in series between the current switching transistors N1 and N2, serving as the active cascode of the current switching unit. Simultaneously, an NMOS transistor N4 is connected in series between the source of the switching pair NMOS transistors N1 and N2 and the drain of the tail current source transistor N3, serving as the cascode of the current switching unit. This simplifies the process. Figure 5 and Figure 3 The output impedance of all NMOS transistors is r. o The transconductance is g. m Therefore, the output impedance Z of the current switching unit at low frequencies is... DAC(CELL) From the original Figure 3 g m ×r o 2 Increased to Figure 5 g m 3 ×r o 4 Therefore, the improved cascode structure increases the output resistance of the current switching unit, and the increased effective cascode stage reduces the impact of parasitic capacitances from transistors N1 to N4 on the dynamic performance of the current-steering digital-to-analog converter. However, the increased effective cascode stage also introduces parasitic capacitances from themselves (C of transistors N5 and N6). GS Capacitor and C GD The high-rate-changing current-driven digital-to-analog converter input digital data can be directly fed to the differential analog output V through the parasitic capacitance of transistors N5 and N6. OUT This generates nonlinearity related to the input digital signal, which becomes the main limitation on the output impedance of the current switching unit of the current-controlled digital-to-analog converter at high frequencies.

[0053] Among them, NMOS transistor N1 has a parasitic capacitance C GS1 and C GD1 The NMOS transistor N2 has a parasitic capacitance C. GS2 and C GD2 NMOS transistor N3 has a parasitic capacitance C. GS3 and C GD3 NMOS transistor N4 has a parasitic capacitance C. GS4 and C GD4 NMOS transistor N5 has a parasitic capacitance C. GS5 and C GD5 The NMOS transistor N6 has a parasitic capacitance C. GS6 and C GD6 .

[0054] Therefore, this invention proposes a technical solution to reduce the nonlinear effects related to input digital data caused by the parasitic capacitance of the cascode transistor in a current-driven digital-to-analog converter (D / A converter): A cascode transistor connected in series is added between the tail current source transistor and the switching pair; an effective cascode transistor is added in series between the switching pair and the differential analog output terminal of the current-driven D / A converter. This increases the output impedance of the current switching unit, thereby reducing the nonlinearity caused by the input digital data modulation effect due to the limited output impedance. Simultaneously, a DC bias current source provides DC bias current to the effective cascode transistor, ensuring that the effective cascode transistor remains on at all times. This avoids the nonlinear effects related to input digital data caused by the parasitic capacitance when the effective cascode transistor is completely off, thus improving the linearity of the current switching unit and the current-driven D / A converter itself.

[0055] First, such as Figure 6As shown, the present invention provides a current-driven digital-to-analog converter, which includes a tail current source transistor N3, a common-source cascode transistor N4, a first switch N1, a second switch N2, a first effective common-source cascode transistor N5, a second effective common-source cascode transistor N6, a DC bias current source I1, and two load resistors R. L The source of the tail current source transistor N3 is grounded, and the gate of the tail current source transistor N3 is connected to the first bias voltage V. CS The drain of the tail current source transistor N3 is connected to the source of the common-source cascode transistor N4, and the gate of the common-source cascode transistor N4 is connected to the second bias voltage V. CAS The drain of the common-source common-gate transistor N4 is connected to the source of the first switching transistor N1, the gate of the first switching transistor N1 is connected to the first digital signal DN, the drain of the first switching transistor N1 is connected to the source of the first effective common-source common-gate transistor N5, the source of the first effective common-source common-gate transistor N5 is also connected to the first output terminal of the DC bias current source I1, and the gate of the first effective common-source common-gate transistor N5 is connected to the third bias voltage V. CAS_active The drain of the first effective cascode transistor N5 is connected in series with a load resistor R. L Connect to working voltage V CC The source of the second switch N2 is connected to the source of the first switch N1. The gate of the second switch N2 is connected to the second digital signal DP. The drain of the second switch N2 is connected to the source of the second effective cascode transistor N6. The source of the second effective cascode transistor N6 is also connected to the second output terminal of the DC bias current source I1. The gate of the second effective cascode transistor N6 is connected to the third bias voltage V. CAS_active The drain of the second effective cascode transistor N6 is connected in series with another load resistor R. L Connect to working voltage V CC Among them, the DC bias current source I1 provides the first DC bias current I to the first effective cascode transistor N5. OUT1 The DC bias current source I1 provides the second DC bias current I to the second effective cascode transistor N6. OUT2 This ensures that the first effective cascode transistor N5 and the second effective cascode transistor N6 remain on at all times.

[0056] The current-driven digital-to-analog converter (DDC converter) comprises a tail current source transistor N3, a common-source cascode transistor N4, a first switch N1, a second switch N2, a first effective common-source cascode transistor N5, a second effective common-source cascode transistor N6, and a DC bias current source I1, forming a current switching unit. The entire DDC converter includes multiple current switching units connected in parallel. The differential output terminal V of the DDC converter... OUT It is composed of the output terminals of multiple current switching units connected in parallel, and its differential output terminal V OUTEach of the two ends drives a load resistor R. L .

[0057] In detail, such as Figure 6 As shown, the tail current source transistor N3, the common-source cascode transistor N4, the first switch transistor N1, the second switch transistor N2, the first effective common-source cascode transistor N5, and the second effective common-source cascode transistor N6 are all NMOS transistors.

[0058] More in detail, such as Figure 6 As shown, the first bias voltage V CS The first input terminal of the current switching unit, and the second bias voltage V CAS The second input terminal of the current switching unit, and the third bias voltage V CAS_active The first digital signal DN is the third input terminal of the current switching unit, the second digital signal DP is the fifth input terminal of the current switching unit, the source of the first effective cascode transistor N5 is the sixth input terminal of the current switching unit, the source of the second effective cascode transistor N6 is the seventh input terminal of the current switching unit, the drain of the first effective cascode transistor N5 is the first output terminal of the current switching unit, and the drain of the second effective cascode transistor N6 is the second output terminal of the current switching unit.

[0059] More in detail, such as Figure 6 As shown, the parameters of the first switch N1 are the same as those of the second switch N2, and the parameters of the first effective cascode transistor N5 are the same as those of the second effective cascode transistor N6; the size of the first switch N1 is smaller than the size of the first effective cascode transistor N5.

[0060] In detail, such as Figure 7 As shown, in an optional embodiment of the present invention, the DC bias current source I1 includes a buffer amplifier A1, a first NMOS transistor N9, and a second NMOS transistor N... 10 The third NMOS transistor N 11 The fourth NMOS transistor N 12 The fifth NMOS transistor N 13 and the sixth NMOS transistor N 14 The source of the first NMOS transistor N9 is grounded, and the gate of the first NMOS transistor N9 is connected to the first bias voltage V. CS The drain of the first NMOS transistor N9 is connected to the drain of the third NMOS transistor N. 11 The source of the third NMOS transistor N 11 The gate is connected to the second bias voltage V CAS The third NMOS transistor N 11 The drain of the fifth NMOS transistor is connected to the N. 13The source of the fifth NMOS transistor. 13 The gate of the second NMOS transistor is connected to the output of buffer amplifier A1. The non-inverting input of buffer amplifier A1 is connected to the fourth bias voltage of 1.2V, and the inverting input of buffer amplifier A1 is connected to the output of buffer amplifier A1. 10 The source of the second NMOS transistor is grounded. 10 The gate is connected to the first bias voltage V CS The second NMOS transistor N 10 The drain of the fourth NMOS transistor is connected to the N. 12 The source of the fourth NMOS transistor N 12 The gate is connected to the second bias voltage V CAS The fourth NMOS transistor N 12 The drain of the sixth NMOS transistor is connected to the N. 14 The source of the sixth NMOS transistor. 14 The gate of the buffer amplifier A1 is connected to the output terminal of the buffer amplifier.

[0061] Among them, the first NMOS transistor N9 and the second NMOS transistor N 10 The tail current source transistor, the third NMOS transistor N 11 The fourth NMOS transistor N 12 It is a common-source, common-gate transistor, the fifth NMOS transistor N 13 and the sixth NMOS transistor N 14 This is an effective common-source common-gate transistor; the gate of the first NMOS transistor N9 is the first input terminal of the DC bias current source I1, and the third NMOS transistor N... 11 The gate of the amplifier is the second input terminal of the DC bias current source I1, and the non-inverting input terminal of the buffer amplifier A1 is the third input terminal of the DC bias current source I1. The fifth NMOS transistor N 13 The drain of the DC bias current source I1 is the first output terminal, which outputs the first DC bias current I. OUT1 The sixth NMOS transistor N 14 The drain of the DC bias current source I1 is the second output terminal, which outputs the second DC bias current I. OUT2 .

[0062] In detail, the parameter specifications of the first NMOS transistor N9 are the same as those of the second NMOS transistor N... 10 The parameters and specifications are the same, the third NMOS transistor N 11 The parameter specifications and the fourth NMOS transistor N 12 The parameters and specifications are the same, the fifth NMOS transistor N 13 The parameter specifications and the sixth NMOS transistor N 14 The parameters and specifications are the same; the size of the first NMOS transistor N9 is larger than that of the third NMOS transistor N. 11 Size, third NMOS transistor N 11The size is larger than that of the fifth NMOS transistor N 13 The size.

[0063] In an optional embodiment of the present invention, the operating voltage V CC The power supply voltage is 1.8V, and the first bias voltage is V. CS The value is 300mV~400mV, the second bias voltage V CAS The value is 700mV~800mV, and the third bias voltage V CAS_active The value of the first bias voltage is 1.5V to 1.6V, the value of the fourth bias voltage is 1.2V, and the digital signals of the current switching unit (i.e., the first digital signal DN and the second digital signal DP) are complementary differential digital signals of 1.2V / 0V.

[0064] More in detail, such as Figures 6-8 As shown, the working principle of the current-driven digital-to-analog converter in this invention is analyzed as follows:

[0065] In the specific design of the current switching unit, the tail current source transistor N3 is designed to be relatively large, with a W / L ratio of 2μ / 0.4μ and 16 gates, primarily to ensure the matching of the current source array; the common-source common-gate transistor N4 is designed to be slightly smaller, with a W / L ratio of 0.8μ / 0.2μ and 2 gates, primarily to support the operating current of the first switch N1 and the second switch N2; the sizes of the first switch N1 and the second switch N2 are designed to be as small as possible, with a W / L ratio of 0.8μ / 0.06μ and 1 gate. The primary objective is to achieve a higher conversion rate. The first effective cascode transistor N5 and the second effective cascode transistor N6 are designed with a W / L of 1.0μF / 0.28μF and a gate count of 1. Their design aims to reduce the parasitic resistance from the first switch N1, the second switch N2, the tail current source transistor N3, and the cascode transistor N4. However, this design introduces parasitic capacitance (C) from the effective cascode transistors themselves (i.e., the first effective cascode transistor N5 and the second effective cascode transistor N6). GS and C GD Since the input digital signal of the current-controlled digital-to-analog converter controls the on / off state of the first switch N1 and the second switch N2, the rapidly changing input digital signal passes through the parasitic capacitance (C) of the effective common-source cascode transistors N5 and N6. GS and C GD It is directly fed to the differential analog output terminal V of the current-controlled digital-to-analog converter. OUT The nonlinearity caused by digital modulation effect becomes the main limitation on the output impedance of current-driven digital-to-analog converters at high frequencies.

[0066] To ensure good linearity of the current-driven digital-to-analog converter (DC-Analog Converter) at high frequencies, the distortion caused by the finite output impedance at high frequencies is analyzed. This distortion is primarily due to the output impedance of the actually conducting portion. Any non-conducting impedance (including parasitic capacitance) remains constant only on each side of the differential output of the DC-driven DC-Analog Converter. When the input digital signal of the DC-driven DC-Analog Converter operates at high frequencies, these constant impedances do not contribute to the high-frequency distortion of the DC-driven DC-Analog Converter. Therefore, this invention adds a DC bias current source I1 to the source of the first effective cascode transistor N5 and the second effective cascode transistor N6, providing DC bias current to the first effective cascode transistor N5 and the second effective cascode transistor N6. The purpose is to prevent the first effective cascode transistor N5 and the second effective cascode transistor N6 from being completely turned off. In other words, even if the first switch N1 or the second switch N2 of the DC-driven DC-Analog Converter is not conducting, the tail current source I1... O Without the first effective cascode transistor N5 or the second effective cascode transistor N6, but because the sources of the first effective cascode transistor N5 and the second effective cascode transistor N6 are designed with fixed DC bias current sources I1 of equal amplitude, the first effective cascode transistor N5 and the second effective cascode transistor N6 are always in the on state. This avoids the infinite charging and discharging process of parasitic capacitance under input digital control when the first effective cascode transistor N5 and the second effective cascode transistor N6 are completely turned off, and eliminates the nonlinear distortion caused by the nonlinear modulation effect of the parasitic capacitance of the effective cascode transistor with the input digital. The first effective cascode transistor N5 and the second effective cascode transistor N6 remain active.

[0067] Depend on Figure 6 It can be seen that from the differential analog output terminal V of the current switching unit OUT As can be seen, although the parasitic capacitances associated with nodes B and C can still exist, these parasitic capacitances are irrelevant to whether the first switch N1 and the second switch N2 are in the on or off state. This is because the switching tail current of the current switching unit moves from one side to the other and does not change the effective capacitance seen from the output node, i.e., the parasitic capacitances connected to nodes B and C. These parasitic capacitances do not contribute to the nonlinear distortion of the current-controlled digital-to-analog converter operating at high frequencies.

[0068] Therefore, the first part causing the change in the dynamic effective capacitance seen at the output of the current-controlled digital-to-analog converter is the capacitance (C) of the first switch N1 and the second switch N2 in the current switching unit. GS capacitance, Figure 7The schematic diagram of the dynamic parasitic capacitance of the current switching unit shown can provide a more intuitive understanding. Because the source design of the first effective cascode transistor N5 and the second effective cascode transistor N6 incorporates a small bias current source I1, a fixed first DC bias current I with equal and slightly smaller amplitude is provided. OUT1 Second DC bias current I OUT2 This makes the "dynamically effective" capacitor of the first part seen from the output terminal equal to the capacitors of the first switching transistor N1 and the second switching transistor N2 in the current switching unit. GS The capacitor, due to the code-correlation modulation effect caused by the finite output impedance, is affected by the inherent gain (g) of the first switch N1 and the second switch N2 and the first effective cascode transistor N5 and the second effective cascode transistor N6. m ×r o The improved design of the effective cascode transistor and its fixed DC bias current source I1 together reduces the nonlinear distortion caused by the current-driven digital-to-analog converter and digital correlation modulation effect by an order of magnitude at high frequencies.

[0069] Utilize Figure 7 The DC bias current source I1 shown provides Figure 5 The effective DC bias current source of the common-source cascode transistor N5 / N6, such as Figure 7 As shown: The fourth bias voltage of 1.2V is output through buffer amplifier A1 and supplied to the fifth NMOS transistor N. 13 and the sixth NMOS transistor N 14 The gate bias voltage, the buffer amplifier A1 gain is designed to be above 50dB, the first NMOS transistor N9 and the second NMOS transistor N 10 The gate bias voltage is determined by the external first bias voltage V. CS Provided, third NMOS transistor N 11 and the fourth NMOS transistor N 12 The gate bias voltage is determined by an external second bias voltage V. CAS Provided; First NMOS transistor N9 and second NMOS transistor N 10 The design dimensions are W / L of 2μ / 0.4μ and the number of gates is 2; the third NMOS transistor is N 11 and the fourth NMOS transistor N 12 The design dimensions are W / L of 0.8μ / 0.2μ and the number of gates is 2; the fifth NMOS transistor N 13 and the sixth NMOS transistor N 14 The design dimensions are W / L of 1.0μ / 0.28μ, with 1 gate, and the fifth NMOS transistor is N. 13 and the sixth NMOS transistor N 14 The drain currents respectively output the first DC bias current I OUT1Second DC bias current I OUT2 .

[0070] Secondly, based on the above design concept of the current-steering digital-to-analog converter, this invention also provides a method for improving the high-frequency linearity of the current-steering digital-to-analog converter, which includes the following steps:

[0071] S1. For at least one current switching unit of the current-driven digital-to-analog converter, a common-source cascode transistor is added in series between the tail current source transistor and the switching pair, and an effective common-source cascode transistor is added in series between the switching pair and the differential analog output terminal of the current-driven digital-to-analog converter to increase the output impedance of the current switching unit.

[0072] S2. For at least one current switching unit of the current-controlled digital-to-analog converter, a DC bias current is provided to the effective cascode transistor so that the effective cascode transistor is always turned on.

[0073] Specifically, in step S1, a common-source cascode transistor is added in series between the tail current source transistor and the switching pair, and an effective common-source cascode transistor is added in series between the switching pair and the differential analog output terminal of the current-steering digital-to-analog converter. This effectively increases the output impedance and reduces the nonlinearity caused by the input digital modulation effect due to the limited output impedance. In step S2, a DC bias current is provided to the effective common-source cascode transistor to keep it always on. This avoids the nonlinear effects related to the input digital caused by the parasitic capacitance when the effective common-source cascode transistor is completely off, and improves the linearity of the current-steering digital-to-analog converter at high frequencies.

[0074] In summary, in the current-driven digital-to-analog converter and its high-frequency linearity improvement method provided by this invention, by adding a series-connected common-source cascode transistor between the tail current source transistor and the first and second switching transistors, adding a series-connected first effective common-source cascode transistor between the first switching transistor and the positive terminal of the differential analog output of the current-driven digital-to-analog converter, and adding a series-connected second effective common-source cascode transistor between the second switching transistor and the negative terminal of the differential analog output of the current-driven digital-to-analog converter, the output impedance of the current switching unit can be effectively increased, which can reduce the input digital modulation caused by the limited output impedance. The nonlinearity caused by the effect; at the same time, by providing a first DC bias current to the first effective cascode transistor and a second DC bias current to the second effective cascode transistor through a DC bias current source, the first effective cascode transistor and the second effective cascode transistor are always kept on, which can effectively avoid the nonlinear effects related to the input digital caused by the parasitic capacitance when the first effective cascode transistor and the second effective cascode transistor are completely off, and improve the linearity of the current switching unit and the current-steering digital-to-analog converter at high frequencies.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A current-driven digital-to-analog converter, characterized in that, The device includes a tail current source transistor, a common-source common-gate transistor, a first switch, a second switch, a first effective common-source common-gate transistor, a second effective common-source common-gate transistor, a DC bias current source, and two load resistors. The source of the tail current source transistor is grounded, its gate is connected to a first bias voltage, its drain is connected to the source of the common-source common-gate transistor, its gate is connected to a second bias voltage, its drain is connected to the source of the first switch, its gate is connected to a first digital signal, its drain is connected to the source of the first effective common-source common-gate transistor, its source is also connected to the first output terminal of the DC bias current source, its gate is connected to a third bias voltage, and its drain is connected to the operating voltage via one of the load resistors connected in series. The drain of the first effective common-source common-gate transistor is the current source. The differential analog output positive terminal of the current switching unit of the analog-to-digital converter is connected to the following: the source of the second switching transistor is connected to the source of the first switching transistor; the gate of the second switching transistor is connected to the second digital signal; the drain of the second switching transistor is connected to the source of the second effective cascode transistor; the source of the second effective cascode transistor is also connected to the second output terminal of the DC bias current source; the gate of the second effective cascode transistor is connected to the third bias voltage; the drain of the second effective cascode transistor is connected to the operating voltage via another load resistor connected in series; and the drain of the second effective cascode transistor is the differential analog output negative terminal of the current switching unit of the current-controlled analog-to-digital converter. The DC bias current source provides a first DC bias current to the first effective cascode transistor and a second DC bias current to the second effective cascode transistor, ensuring that both the first and second effective cascode transistors remain on at all times. The DC bias current source includes a buffer amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the first NMOS transistor is grounded, its gate is connected to the first bias voltage, its drain is connected to the source of the third NMOS transistor, its gate is connected to the second bias voltage, its drain is connected to the source of the fifth NMOS transistor, its gate is connected to the output terminal of the buffer amplifier, and the non-inverting input terminal of the buffer amplifier is connected to a fourth bias voltage. The inverting input terminal of the buffer amplifier is connected to the output terminal of the buffer amplifier. The source of the second NMOS transistor is grounded, the gate of the second NMOS transistor is connected to the first bias voltage, the drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the second bias voltage, the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the output terminal of the buffer amplifier. The drain of the fifth NMOS transistor is the first output terminal of the DC bias current source, and the drain of the sixth NMOS transistor is the second output terminal of the DC bias current source. The size of the first NMOS transistor is larger than the size of the third NMOS transistor, and the size of the third NMOS transistor is larger than the size of the fifth NMOS transistor.

2. The current-controlled digital-to-analog converter according to claim 1, characterized in that, The tail current source transistor, the common-source common-gate transistor, the first switch transistor, the second switch transistor, the first effective common-source common-gate transistor, and the second effective common-source common-gate transistor are all NMOS transistors.

3. The current-controlled digital-to-analog converter according to claim 1 or 2, characterized in that, The parameters of the first switching transistor are the same as those of the second switching transistor, and the parameters of the first effective cascode transistor are the same as those of the second effective cascode transistor.

4. The current-controlled digital-to-analog converter according to claim 3, characterized in that, The size of the first switching transistor is smaller than the size of the first effective cascode transistor.

5. The current-controlled digital-to-analog converter according to claim 4, characterized in that, The parameters of the first NMOS transistor are the same as those of the second NMOS transistor, the parameters of the third NMOS transistor are the same as those of the fourth NMOS transistor, and the parameters of the fifth NMOS transistor are the same as those of the sixth NMOS transistor.

6. A method for improving the high-frequency linearity of a current-driven digital-to-analog converter, wherein the method is applied to the current-driven digital-to-analog converter as described in any one of claims 1 to 5, characterized in that, include: For at least one current switching unit of the current-steering digital-to-analog converter, a common-source cascode transistor is added in series between the tail current source transistor and the switching pair, and an effective common-source cascode transistor is added in series between the switching pair and the differential analog output terminal of the current-steering digital-to-analog converter to increase the output impedance of the current switching unit. For at least one current switching unit of the current-controlled digital-to-analog converter, a DC bias current is provided to the effective cascode transistor so that the effective cascode transistor remains on at all times.

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