Semiconductor structure and its preparation method

Abstract

This application relates to the semiconductor field, and particularly to a semiconductor structure and its fabrication method. The semiconductor structure includes: a gate on a substrate, with source or drain electrodes on both sides of the gate; a dielectric layer on the substrate; a contact structure that penetrates the dielectric layer and is electrically connected to the source or drain; and a first electrical connection portion and a second electrical connection portion spaced apart, the first and second electrical connection portions being located on the top surface of the dielectric layer, and the second electrical connection portion contacting a portion of the top surface of the contact structure. The first electrical connection portion includes a first barrier layer and a first conductive layer stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and the distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, wherein the first distance is greater than the second distance. This application embodiment helps to reduce the short-circuit risk of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Memory is a common semiconductor structure containing many tiny conductive structural units, such as gates, bit lines, and source / drain electrodes. To bring these tiny conductive structures out, metal interconnect structures are typically fabricated on top of them.

[0003] Using metal interconnect structures to bring out conductive structures can not only improve the operating speed of memory but also increase its integration density. Typically, in semiconductor structures, multiple contact structures located in the dielectric layer and electrical connections connected to these contact structures are used as metal interconnect structures. Furthermore, each metal interconnect structure is spaced apart, bringing out the isolated conductive structures individually.

[0004] However, as memory sizes become smaller, the internal contact structures and electrical connections become increasingly dense, which can easily cause short circuits within the semiconductor structure. Summary of the Invention

[0005] This application provides a semiconductor structure and its fabrication method, which at least helps to improve the problem of short circuit between the contact structure and the first electrical connection.

[0006] According to some embodiments of this application, one aspect of this application provides a semiconductor structure, including: a substrate; a gate located on a portion of the substrate, and a source or drain electrode being located in the substrate on both sides of the gate; a dielectric layer located on the substrate, and the dielectric layer covering the top surface and sidewalls of the gate; a contact structure, the contact structure penetrating the dielectric layer and electrically connected to the source or drain electrode; a first electrical connection portion and a second electrical connection portion disposed at intervals, the first electrical connection portion and the second electrical connection portion being located on the top surface of the dielectric layer, and the second electrical connection portion also contacting a portion of the top surface of the contact structure, the first electrical connection portion including a first barrier layer and a first conductive layer stacked thereon, the distance between the sidewall of the first barrier layer facing the contact structure and the contact structure in the direction from the source to the drain electrode is a first distance, the distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a second distance, and the first distance is greater than the second distance.

[0007] According to some embodiments of this application, another aspect of this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate and a gate located on a portion of the substrate, wherein a source or drain is located in the substrate on both sides of the gate; a dielectric layer is further provided on the substrate, and the dielectric layer covers the top surface and sidewalls of the gate; forming a contact structure, the contact structure penetrating the dielectric layer and electrically connected to the source or drain; forming a first electrical connection portion and a second electrical connection portion disposed at intervals, the first electrical connection portion and the second electrical connection portion being located on the top surface of the dielectric layer, and the second electrical connection portion also contacting a portion of the top surface of the contact structure, the first electrical connection portion comprising a first barrier layer and a first conductive layer stacked thereon, wherein in the direction from the source to the drain, the distance between the sidewall of the first barrier layer toward the contact structure and the contact structure is a first distance, and the distance between the sidewall of the first conductive layer toward the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.

[0008] The technical solution provided in this application has at least the following advantages:

[0009] The semiconductor structure provided in this application includes a substrate, a gate, a source, a drain, and a dielectric layer. It also includes a contact structure that penetrates the dielectric layer and is electrically connected to the source or drain to achieve electrical connection between the source or drain and a conductive structure. A first electrical connection portion and a second electrical connection portion are spaced apart, and the second electrical connection portion also contacts a portion of the top surface of the contact structure to draw out current from the source or drain. The first electrical connection portion includes a first barrier layer and a first conductive layer stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and the distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance. The first distance is greater than the second distance. That is, by changing the bottom contour of the first electrical connection portion, the distance between the first barrier layer and its adjacent contact structure is relatively large, making it less likely for them to contact each other, thereby avoiding short circuits between the first electrical connection portion and the contact structure, and thus improving the electrical performance of the semiconductor structure. Furthermore, by not changing the width of the first conductive layer, the first electrical connection portion can maintain good conductivity. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0011] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor structure;

[0012] Figure 2 A cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0013] Figure 3 This is a schematic diagram of another cross-sectional structure of a semiconductor structure provided in an embodiment of this application;

[0014] Figures 4 to 8 This is a schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0015] As can be seen from the background art, the existing technology has the problem that short circuits are easily caused between the phase-spaced electrical connection parts and contact structures.

[0016] Analysis revealed that one of the reasons why short circuits are prone to occur between the electrical connection and the contact structure is that the distance between the electrical connection and the adjacent contact structure is small, making it easy for a short circuit to occur between the bottom of the electrical connection and the top surface of the adjacent contact structure.

[0017] The causes of the above problems will now be further analyzed using a semiconductor structure as an example. Figure 1 This is a schematic diagram of a semiconductor structure, for reference. Figure 1 The semiconductor structure includes: a substrate 100; a gate 110 located on a portion of the substrate 100 and a sidewall layer 117 located on the surface of the gate 110, the gate 110 including a gate dielectric layer 111, a gate conductive layer 112 and a gate capping layer 113, and a source or drain electrode in the substrate 100 on both sides of the gate 110; a dielectric layer 130 located on the substrate 100, and the dielectric layer 130 covering the top surface and sidewalls of the gate 110; a contact structure 120 penetrating the dielectric layer 130 and electrically connected to the source or drain electrode; a first electrical connection portion 140 and a second electrical connection portion 150 disposed at intervals, the first electrical connection portion 140 and the second electrical connection portion 150 both located on the top surface of the dielectric layer 130, and the second electrical connection portion 150 also contacts a portion of the top surface of the contact structure 120.

[0018] The second electrical connection portion 150 contacts a portion of the top surface of the contact structure 120, and the first electrical connection portion 140 is connected to a portion of the top surface of another contact structure (not shown), respectively leading out the isolated source or drain electrodes. During the process of forming the first electrical connection portion 140 and the second electrical connection portion 150, alignment errors may occur, resulting in an excessively small distance between the contact structure 120 and the first electrical connection portion 140, making it easy for a short circuit to occur between the top of the contact structure 120 and the bottom of the first electrical connection portion 140.

[0019] This application provides a semiconductor structure that only changes the bottom contour of the first electrical connection portion, making the distance between the first barrier layer and the contact structure larger. This avoids the problem of alignment errors causing the first electrical connection portion and the contact structure to be too close during the process of forming the first electrical connection portion and the second electrical connection portion, thereby reducing the risk of short circuit and increasing the process window for forming the first electrical connection portion and the second electrical connection portion.

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0021] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0022] refer to Figure 2 The semiconductor structure includes: a substrate 200; a gate 210 located on a portion of the substrate 200, with a source or drain electrode located in the substrate 200 on both sides of the gate 210; a dielectric layer 230 located on the substrate 200, covering the top surface and sidewalls of the gate 210; a contact structure 220 penetrating the dielectric layer 230 and electrically connected to the source or drain electrode; and a first electrical connection portion 240 and a second electrical connection portion 250 disposed at intervals, both the first electrical connection portion 240 and the second electrical connection portion 250 being located in the dielectric layer. The top surface of the first electrical connection 240 is 230, and the second electrical connection 250 is in contact with a portion of the top surface of the contact structure 220. The first electrical connection 240 includes a first barrier layer 241 and a first conductive layer 242 stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer 241 facing the contact structure 220 and the contact structure 220 is a first distance L1, and the distance between the sidewall of the first conductive layer 242 facing the contact structure 220 and the contact structure 220 is a second distance L2. The first distance L1 is greater than the second distance L2.

[0023] This embodiment only modifies the bottom contour of the first electrical connection portion 240, increasing the distance between the first barrier layer 241 and its adjacent contact structure 220. This makes them less likely to come into contact, reducing the risk of short circuits in the semiconductor structure. It also increases the process window for forming the first electrical connection portion 240 and the second electrical connection portion 250. Furthermore, by not changing the width of the first conductive layer 242, it achieves a relatively large volume and low resistance, thus maintaining good conductivity in the first electrical connection portion 240.

[0024] The semiconductor structure can be a memory, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0025] The substrate 200 may be a semiconductor substrate or a silicon substrate on an insulator. In some embodiments, the substrate 200 may be a silicon substrate. In other embodiments, the substrate 200 may also be a germanium substrate, a silicon germanide substrate, or a silicon carbide substrate.

[0026] The gate 210 includes a gate dielectric layer 211, a gate conductive layer 212, and a gate capping layer 213 stacked sequentially. In some embodiments, the gate conductive layer 212 may include a first gate conductive layer 214, a barrier layer 215, and a second gate conductive layer 216 stacked sequentially. The barrier layer 215 prevents mutual diffusion between the first gate conductive layer 214 and the second gate conductive layer 216. The first gate conductive layer 214 is made of a semiconductor material, and the second gate conductive layer 216 is made of a metal material. In some embodiments, the first gate conductive layer 214 may be made of polysilicon, the barrier layer 215 may be made of titanium nitride, and the second gate conductive layer 216 may be made of tungsten, copper, or aluminum.

[0027] In other embodiments, the gate conductive layer can be a single-layer structure, and the material of the gate conductive layer can be a semiconductor material or a metal. The semiconductor material can be polycrystalline silicon, and the metal material can be any one of tungsten, copper, or aluminum.

[0028] The gate cap layer 213 mainly serves as an isolation and insulation layer, and the material of the gate cap layer 213 can be silicon oxide or silicon nitride.

[0029] The semiconductor structure may further include: a first sidewall layer 217 covering the sidewall of the gate 210; a second sidewall layer 218 covering the sidewall of the first sidewall layer 217, the gate 210, and a portion of the substrate 200; and an etch stop layer 219 covering the second sidewall layer 218.

[0030] A source electrode is located within one side of the substrate 200 of the gate 210, and a drain electrode is located within the other side of the substrate 200. The bottom surface of the contact structure 220 is electrically connected to the source electrode or the drain electrode, and the top surface is connected to the second electrical connection portion 250, thereby forming an electrical connection between the source electrode or the drain electrode and the second electrical connection portion 250. In some embodiments, the semiconductor structure is a PMOS transistor, and the doped ions of the source and drain electrodes are P-type ions; in other embodiments, the semiconductor structure is an NMOS transistor, and the doped ions of the source and drain electrodes are N-type ions.

[0031] The dielectric layer 230 includes a first dielectric layer 231 and a second dielectric layer 232 stacked sequentially. In some embodiments, the top of the first dielectric layer 231 may be flush with the top of the etch stop layer 219 to isolate the gate 210 from other conductive structures; the second dielectric layer 232 is higher than the top of the etch stop layer 219, and during the etching process, the second dielectric layer 232 located on top of the gate 210 can provide protection for the gate 210, thereby preventing damage to the gate 210. In other embodiments, the top of the first dielectric layer may be higher than the top of the etch stop layer; in still other embodiments, the top of the first dielectric layer may be lower than the top of the etch stop layer.

[0032] In some embodiments, the density of the second dielectric layer 232 is greater than that of the first dielectric layer 231 to enhance the protective effect of the second dielectric layer 232 on the gate 210; in other embodiments, the density of the second dielectric layer 232 may also be equal to that of the first dielectric layer 231.

[0033] In some embodiments, the material of the first dielectric layer 231 may be silicon oxide, and the material of the second dielectric layer 232 may be silicon nitride or silicon oxynitride.

[0034] The second electrical connection portion 250 is in contact with the contact structure 220, and the first electrical connection portion 240 is adjacent to the contact structure 220 and in contact with another contact structure (not shown) in the semiconductor structure, each drawing out the current from two adjacent source or drain electrodes in the substrate 200. The first barrier layer 241 in the first electrical connection portion 240 covers the bottom surface of the first conductive layer 242 and is in contact with the surface of the dielectric layer 230, which can prevent ions in the first conductive layer 242 from diffusing into the dielectric layer 230.

[0035] In the direction from the source to the drain, the width of the first barrier layer 241 is smaller than the width of the first conductive layer 242. This creates a void between the bottom of the first conductive layer 242, the sidewall of the first barrier layer 241 facing the contact structure 220, and the top surface of the dielectric layer 230. Due to this void, the distance between the bottom of the first electrical connection 240 and the contact structure 220 is larger, thereby reducing the probability of contact between the first electrical connection 240 and the contact structure 220, and thus reducing the risk of a short circuit.

[0036] Specifically, in some embodiments, the ratio of the width of the first barrier layer 241 to the width of the first conductive layer 242 is 0.5 to 0.9. Within this ratio range, on the one hand, the width of the first barrier layer 241 is smaller than the width of the first conductive layer 242, resulting in a larger distance between the bottom of the electrical connection portion 240 and the contact structure 220. On the other hand, the contact area between the first barrier layer 241 and the first conductive layer 242 is larger, resulting in a smaller contact resistance between the first barrier layer 241 and the first conductive layer 242. Consequently, the current conduction capability inside the first electrical connection portion 240 is better, and the conductivity of the first electrical connection portion 240 is maintained well.

[0037] The material of the first barrier layer 241 can be TiN or TaN, and the material of the first conductive layer 242 can be tungsten. The function of the first barrier layer 241 is to prevent metal ions in the first conductive layer 242 from diffusing into the dielectric layer 230.

[0038] In other embodiments, the material of the first barrier layer 241 may be either Ta or Ti, and the material of the first conductive layer 242 may be either copper or aluminum.

[0039] The thickness of the first barrier layer 241 is less than the thickness of the first conductive layer 242. It can be understood that within this thickness range, the thickness of the first conductive layer 242 is relatively large, and the conductivity of the first conductive layer 242 is relatively strong. Thus, the overall resistance of the first electrical connection portion 240 is relatively small, which is beneficial to improving the current conduction capability.

[0040] The orthographic projection of the first barrier layer 241 onto the surface of the substrate 200 lies within the orthographic projection of the first conductive layer 242 onto the surface of the substrate 200. That is, the first barrier layer 241 and the first conductive layer 242 are directly opposite each other, and in the direction from the source to the drain, the width of the first barrier layer 241 is smaller than the width of the first conductive layer 242. It should be noted that, unless otherwise specified, all widths mentioned below refer to the width in the direction from the source to the drain.

[0041] In some embodiments, the second electrical connection portion 250 may include a stacked second barrier layer 251 and a second conductive layer 252, wherein the second barrier layer 251 contacts a portion of the top surface of the contact structure 220; and the top surface of the contact structure 220, the sidewall of the second barrier layer 251, and the bottom surface of the second conductive layer 252 form a void region. In other embodiments, the second electrical connection portion may also be a single-layer structure comprising only the second conductive layer.

[0042] The second barrier layer 251 contacts a portion of the top surface of the contact structure 220, forming a staggered connection structure. The advantages of this connection method are twofold: firstly, it allows for the formation of more electrical connections on the surface of the dielectric layer 230 of the same area, fully utilizing space and improving the performance of the semiconductor structure; secondly, compared to the second barrier layer 251 covering the entire top surface of the contact structure 220, the presence of a portion of the top surface of the contact structure 220 not connected to the second barrier layer 251 further increases the relative distance between the second electrical connection portion 250 and the first electrical connection portion 240, reducing the risk of short circuits between the first electrical connection portion 240 and the second electrical connection portion 250.

[0043] With the direction from the first connecting portion 240 to the second connecting portion 250 as the left, the sidewall of the second barrier layer 251 away from the contact structure 220 is recessed to the right relative to the sidewall of the second conductive layer 252 away from the contact structure 220, thereby increasing the relative distance between the second barrier layer 251 and the first barrier layer 241. In other words, the width of the second barrier layer 251 is smaller than the width of the second conductive layer 252. Therefore, by reducing only the width of the second barrier layer 251 without changing the width of the second conductive layer 252, a void is formed between the bottom of the second conductive layer 252, the sidewall of the second barrier layer 251 away from the contact structure 220, and the top surface of the contact structure 220. The presence of this void makes it less likely that the adjacent first electrical connection portion 240 and second electrical connection portion 250, which are prone to narrow contact and short circuits, will come into contact, further reducing the risk of short circuits. Furthermore, the sidewall of the second barrier layer 251 facing the contact structure 220 is recessed to the left relative to the sidewall of the second conductive layer 252 facing the contact structure 220, thereby increasing the distance between the bottom of the second electrical connection portion 250 and the top of the adjacent contact structure (not shown), reducing the probability of contact and thus reducing the risk of short circuit.

[0044] It is understood that, in other embodiments, the sidewall of the second barrier layer facing the contact structure may also be flush with the sidewall of the second conductive layer facing the contact structure, such as... Figure 3 As shown.

[0045] In some embodiments, the width of the first barrier layer 241 is equal to the width of the second barrier layer 251 in the direction from the source to the drain. This is because, in the process steps of forming the first barrier layer 241 and the second barrier layer 251, a one-step etching method is used, and the same process parameters are set for etching back the first barrier layer 241 and the second barrier layer 251. Therefore, the width of the first barrier layer 241 is equal to the width of the second barrier layer 251. This simplifies the process steps and facilitates large-scale production.

[0046] In other embodiments, the width of the first barrier layer 241 may not be equal to the width of the second barrier layer 251 in the direction from the source to the drain. The first barrier layer 241 may be configured such that its sidewall facing the contact structure 220 is recessed to the right relative to the sidewall of the first conductive layer 242 facing the contact structure 220, and its sidewall away from the contact structure 220 is recessed to the left relative to the sidewall of the first conductive layer 242 away from the contact structure 220; the second barrier layer 251 may be flush with the sidewall of the second conductive layer 252 facing the contact structure 220, and its sidewall away from the contact structure 220 may be recessed to the right relative to the sidewall of the second conductive layer 252 away from the contact structure 220.

[0047] In some embodiments, the material of the first barrier layer 241 can be the same as the material of the second barrier layer 251; the material of the first conductive layer 242 can be the same as the material of the second conductive layer 252. This allows for the simultaneous formation of the first barrier layer 241 having a width smaller than the width of the first conductive layer 242, the second barrier layer 251 having a width smaller than the width of the second conductive layer 252, and the length of the first barrier layer 241 being equal to the width of the second barrier layer 251 in the direction from the source to the drain, thus simplifying the process flow.

[0048] The contact structure 220 extends through the entire dielectric layer 230, and the width of the contact structure 220 located in the first dielectric layer 231 is greater than the width of the contact structure 220 located in the second dielectric layer 232, forming a structure that is narrower at the top and wider at the bottom. This is because the second dielectric layer 232 has a higher density and is more difficult to etch in actual processes, thus the width of the contact structure 220 formed in the second dielectric layer 232 is smaller. It is understood that in some other embodiments, the width of the contact structure located in the first dielectric layer may also be equal to the width of the contact structure located in the second dielectric layer.

[0049] In some embodiments, the contact structure 220 includes: a conductive body portion 221 penetrating the dielectric layer 230, and a second electrical connection portion 250 in contact with a portion of the surface of the conductive body portion 221; and a diffusion barrier layer 222 located on the sidewalls and bottom of the conductive body portion 221. The diffusion barrier layer 222 can prevent ions in the conductive body portion 221 from diffusing into the dielectric layer 230 and the substrate 200.

[0050] The top surface of the diffusion barrier layer 222 between the conductive main body 221 and the first electrical connection 240 is lower than the top surface of the conductive main body 221, and the conductive main body 221, the dielectric layer 230, and the top surface of the diffusion barrier layer 222 between the conductive main body 221 and the first electrical connection 240 form a through-hole region. The presence of the through-hole region further increases the second distance between the first barrier layer 241 and the sidewall of the contact structure 220 compared to the condition without the through-hole region. This further reduces the risk of short circuit between the first electrical connection 240 and the contact structure 220.

[0051] In other embodiments, such as Figure 3 As shown, the top surface of the diffusion barrier layer 222 between the conductive main body 221 and the first electrical connection 240 can also be flush with the top surface of the conductive main body 221.

[0052] In some embodiments, the material of the diffusion barrier layer 222 is the same as the material of the first barrier layer 241, and the material of the conductive body portion 221 is the same as the material of the first conductive layer 242. For example, the materials of the diffusion barrier layer 222 and the first barrier layer 241 are both titanium nitride; the materials of the conductive body portion 221 and the first conductive layer 242 are both tungsten.

[0053] In other embodiments, the material of the diffusion barrier layer 222 may be different from that of the first barrier layer 241, and the material of the conductive body portion 221 may also be different from that of the first conductive layer 242. For example, the material of the diffusion barrier layer 222 may be titanium nitride, the material of the first barrier layer 241 may be tantalum nitride, the material of the conductive body portion 221 may be copper, and the material of the first conductive layer 242 may be tungsten.

[0054] In the semiconductor structure provided in the above embodiments, the first electrical connection portion 240 includes a first barrier layer 241 and a first conductive layer 242 stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer 241 facing the contact structure 220 and the contact structure 220 is a first distance L1, and the distance between the sidewall of the first conductive layer 242 facing the contact structure 220 and the contact structure 220 is a second distance L2. The first distance L1 is greater than the second distance L2. That is, by changing the bottom contour of the first electrical connection portion 240, the distance between the first barrier layer 241 and the adjacent contact structure 220 is made relatively large. During the process of forming the first electrical connection portion 240 and the second electrical connection portion 250, alignment deviations that cause the first electrical connection portion 240 to be too close to the contact structure 220 are avoided, thereby reducing the risk of short circuits. At the same time, the process window for forming the first electrical connection portion 240 and the second electrical connection portion 250 is also increased.

[0055] Another embodiment of this application provides a method for preparing a semiconductor structure, which can form the semiconductor structure provided in the previous embodiment. The method for preparing a semiconductor structure provided in another embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] Figures 4 to 8 This is a schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to another embodiment of this application.

[0057] refer to Figure 4 The substrate 200 and the gate 210 located on the substrate 200 are provided, and the substrate 200 on both sides of the gate 210 has a source or drain. The substrate 200 also has a dielectric layer 230, and the dielectric layer 230 covers the top surface and sidewalls of the gate 210.

[0058] The substrate 200 is a semiconductor substrate; in some embodiments, the semiconductor substrate is a silicon substrate. In other embodiments, the semiconductor substrate may also be a germanium substrate, a silicon germanide substrate, or a silicon carbide substrate.

[0059] The step of forming the gate 210 may include forming a gate dielectric layer 211, a gate conductive layer 212, and a gate capping layer 213 that are stacked sequentially. In some embodiments, the gate conductive layer 212 may include a first gate conductive layer 214, a barrier layer 215, and a second gate conductive layer 216 that are stacked sequentially.

[0060] It may also include: forming a first sidewall layer 217, the first sidewall layer 217 covering the sidewall of the gate 210; forming a second sidewall layer 218, the second sidewall layer 218 covering the sidewall of the first sidewall layer 217, the gate 210 and a portion of the substrate 200; and forming an etch stop layer 219, covering the second sidewall layer 218.

[0061] It also includes: forming a source in a substrate 200 on one side of the gate 210, and forming a drain in a substrate 200 on the other side of the gate 210. In some embodiments, the semiconductor structure is a PMOS transistor, and the doped ions of the source and drain are P-type ions; in other embodiments, the semiconductor structure is an NMOS transistor, and the doped ions of the source and drain are N-type ions.

[0062] The step of forming dielectric layer 230 includes: forming a first dielectric layer 231 and a second dielectric layer 232 stacked sequentially.

[0063] In some embodiments, the density of the second dielectric layer 232 is greater than the density of the first dielectric layer 231, thereby enhancing the protective effect of the second dielectric layer 232 on the gate 210. In other embodiments, the density of the second dielectric layer 232 may also be equal to the density of the first dielectric layer 231.

[0064] For detailed descriptions of the substrate, gate, and dielectric layer, please refer to the specific descriptions in the foregoing embodiments; they will not be repeated in detail below.

[0065] refer to Figure 5 and Figure 6 This forms a contact structure 220, which penetrates the dielectric layer 230 and is electrically connected to the source or drain.

[0066] Specifically, refer to Figure 5 The specific process steps for forming the contact structure 220 include: patterning the first dielectric layer 231 and the second dielectric layer 232 using an etching process to form a first through hole 21 and a second through hole 22 that are interconnected. The first through hole 21 penetrates the first dielectric layer 231, and the second through hole 22 penetrates the second dielectric layer 232. The first through hole 21 and the second through hole 22 are directly opposite to each other and are interconnected. This ensures that when the contact structure is filled in the first through hole and the second through hole in subsequent steps, the first contact layer in the first through hole and the second contact layer in the second through hole are directly opposite to each other and are interconnected. This results in a larger contact area between the first contact layer and the second contact layer, thereby reducing the contact resistance between the first contact layer and the second contact layer.

[0067] It is worth noting that in some embodiments, the same etching process parameters are used to form the first via 21 and the second via 22 in the same step. In other embodiments, the first dielectric layer 231 and the second dielectric layer 232 may also be etched separately to form the first via 21 and the second via 22.

[0068] The width of the first via 21 is greater than the width of the second via 22 because the etching rate of the second dielectric layer 232 is lower than the etching rate of the first dielectric layer 231. Relatively speaking, the second dielectric layer 232 has a higher density than the first dielectric layer 231, resulting in a faster etching rate for the first dielectric layer 231. Alternatively, the etching process gas may have a higher selectivity for the material of the second dielectric layer 232 than for the material of the first dielectric layer 232. Therefore, in a single etching step, a via structure that is narrower at the top and wider at the bottom is formed. It is understood that in other embodiments, the width of the first via may also be equal to the width of the second via.

[0069] refer to Figure 6 The step of forming the contact structure 220 includes: forming a conductive body portion 221 in the through-hole 20 and a diffusion barrier layer 222 located on the sidewalls and bottom of the conductive body portion. The diffusion barrier layer 222 can prevent ions in the conductive body portion 221 from diffusing into the substrate 200 and the dielectric layer 230.

[0070] In some embodiments, the diffusion barrier layer 222 may be made of TiN or TaN, and the conductive body portion 221 may be made of W; in other embodiments, the diffusion barrier layer 222 may also be made of either Ta or Ti, and the conductive body portion 221 may also be made of copper or aluminum.

[0071] Specifically, the specific process steps for forming the contact structure 220 are as follows:

[0072] An initial diffusion barrier layer is deposited in the first through-hole 21 and the second through-hole 22 using a deposition process, and the initial diffusion barrier layer is higher than the top surface of the dielectric layer 230; the portion of the initial diffusion barrier layer that is higher than the top surface of the dielectric layer 230 is removed, and the remaining portion of the initial diffusion barrier layer is used as the diffusion barrier layer 222.

[0073] An initial conductive body portion is deposited on the surface of the diffusion barrier layer 222 in the first through-hole 21 and the second through-hole 22 using a deposition process, and the initial conductive body portion is higher than the top surface of the dielectric layer 230; the portion of the initial conductive body portion that is higher than the top surface of the dielectric layer 230 is removed, and the remaining initial conductive body portion serves as the conductive body portion 221 to form the contact structure 220.

[0074] In some embodiments, the contact structure 220 extends through the entire dielectric layer 230. The width of the contact structure 220 in the first dielectric layer 231 is greater than the width of the contact structure 220 in the second dielectric layer 232, forming a structure that is narrower at the top and wider at the bottom. This is because the second dielectric layer 232 has a higher density and is more difficult to etch in actual processes, thus resulting in a smaller width of the contact structure 220 formed in the second dielectric layer 232. Compared to a situation where the width of the contact structure 220 in the first dielectric layer 231 is equal to the width of the contact structure 220 in the second dielectric layer 232, the larger width of the contact structure 220 in the first dielectric layer 231 increases the overall volume of the contact structure 220, resulting in lower resistance and improved current conduction capability. It is understood that in other embodiments, the width of the contact structure in the first dielectric layer may also be equal to the width of the contact structure in the second dielectric layer.

[0075] In some embodiments, before forming the contact structure 220, a metal silicide layer 225 may be formed at the bottom of the first via 21. The metal silicide layer 225 can reduce the contact resistance between the contact structure 220 and the source or drain. Specifically, the material of the metal silicide layer 225 may be cobalt silicide.

[0076] refer to Figure 2 A first electrical connection portion 240 and a second electrical connection portion 250 are formed at intervals. Both the first electrical connection portion 240 and the second electrical connection portion 250 are formed on the top surface of the dielectric layer 230, and the second electrical connection portion 250 is also in contact with a portion of the top surface of the contact structure 220. The first electrical connection portion 240 includes a first barrier layer 241 and a first conductive layer 242 stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer 241 facing the contact structure 220 and the contact structure 220 is a first distance L1, and the distance between the sidewall of the first conductive layer 242 facing the contact structure 220 and the contact structure 220 is a second distance L2. The first distance L1 is greater than the second distance L2.

[0077] In other words, a cavity is formed between the bottom of the first conductive layer 242, the side wall of the first barrier layer 241 facing the contact structure 220, and the top surface of the dielectric layer 230. The existence of this cavity increases the distance between the bottom of the first electrical connection portion 240 and the contact structure 220, thereby reducing the probability of contact between the two and thus reducing the possibility of short circuit.

[0078] The first barrier layer 241 can prevent ions in the first conductive layer 242 from diffusing into the dielectric layer 230. Specifically, in some embodiments, the material of the first barrier layer 241 can be TiN or TaN, and the material of the first conductive layer 242 can be tungsten; in other embodiments, the material of the first barrier layer 241 can also be either Ta or Ti, and the material of the first conductive layer 242 can also be either copper or aluminum.

[0079] The process steps for forming the first electrical connection portion 240 and the second electrical connection portion 250 include:

[0080] refer to Figure 7 An initial barrier layer 31 and an initial conductive layer 32 are formed sequentially on the top surface of the dielectric layer 230, with the initial barrier layer 31 covering the top surface of the contact structure 220.

[0081] Specifically, an initial barrier layer 31 and an initial conductive layer 32 are sequentially deposited on the top surface of the dielectric layer 230 using a deposition process.

[0082] refer to Figure 8 The initial conductive layer 32 and the initial barrier layer 31 are patterned to form a first initial electrical connection portion 40 and a second initial electrical connection portion 50 that are spaced apart from each other. The second initial electrical connection portion 50 is in contact with a portion of the top surface of the contact structure 220.

[0083] A dry etching process is used to etch the initial conductive layer 32 and the initial barrier layer 31. Before etching the initial conductive layer 32 and the initial barrier layer 31, a patterned mask layer is formed on the surface of the initial conductive layer 32. Using the patterned mask layer as a mask, a portion of the initial conductive layer 32 and the initial barrier layer 31 are etched until the top surface of a portion of the contact structure 220 and the top surface of a portion of the dielectric layer 230 are exposed. The exposed portion of the dielectric layer 230 can isolate the contact structure 220 from the first initial electrical connection portion 40, preventing them from contacting and causing a short circuit.

[0084] In some embodiments, the top surface of the exposed contact structure 220 and the top surface of the dielectric layer 230 can be further etched to form a concave surface facing the substrate 200. In this way, even when the etching parameter precision is low, an isolation effect can be achieved, increasing the process window for forming the first initial electrical connection 40 and the second initial electrical connection.

[0085] It is understood that in other embodiments, the top surface of the exposed contact structure and the top surface of the dielectric layer may not be etched further.

[0086] refer to Figure 2 For the first initial electrical connection portion 40 (reference) Figure 8 The initial blocking layer 41 in ) (reference) Figure 8 The first initial electrical connection portion 40 (reference) is etched towards the sidewall of the contact structure 220. Figure 8 The remaining initial blocking layer 41 in ) (reference) Figure 8 Forming a first barrier layer 241, and a first initial electrical connection portion 40 (reference) Figure 8 Initial conductive layer 42 (reference) Figure 8 The first conductive layer 242 is formed.

[0087] Wet etching process can be used to etch the sidewalls of the initial barrier layer 41.

[0088] Etching is performed only on the initial barrier layer 41 to alter the bottom contour of the first initial electrical connection portion 40. This results in a relatively larger distance between the bottom of the first electrical connection portion 240 and the sidewall of the contact structure 220, reducing the risk of short circuits caused by contact between the first electrical connection portion 240 and the sidewall of the contact structure 220. Simultaneously, alignment deviations may occur during the etching process, causing the initial barrier layer 41 to be too close to the sidewall of the contact structure 220, or even in contact. In this case, etching the initial barrier layer 41 increases the distance between the sidewall of the initial barrier layer 41 facing the contact structure 220 and the contact structure 220, preventing short circuits caused by electrical connections between the first electrical connection portion 240 and the contact structure 220. Thus, alignment deviations during the etching process that could lead to excessively close distances between the first electrical connection portion 240 and the contact structure 220 are avoided, reducing the risk of short circuits between them and increasing the process window for forming the first electrical connection portion 240 and the second electrical connection portion 250. Furthermore, without changing the width of the initial conductive layer 42, i.e., without changing the resistance of the initial conductive layer 42, it can still maintain its good conductivity.

[0089] In some embodiments, when the first initial electrical connection portion 40 (reference) Figure 8 The initial blocking layer 41 in ) (reference) Figure 8 In the process step of etching the sidewall of the contact structure 220, the second initial electrical connection portion 50 (reference) is also etched. Figure 8 The initial blocking layer 51 in ) (reference) Figure 8 The sidewalls of the first electrical connection 240 are etched. That is, a void is formed between the bottom of the second conductive layer 252 of the second electrical connection 250, the sidewall of the second barrier layer 251 of the second electrical connection 250 away from the contact structure 220, and the top surface of the contact structure 220. The presence of this void makes it difficult for the adjacent first electrical connection 240 and second electrical connection 250 to make contact, further reducing the risk of short circuit. It is understood that in some other embodiments, the sidewalls of the initial barrier layer in the second electrical connection may not be etched.

[0090] In some embodiments, in relation to the first initial electrical connection portion 40 (reference 40) Figure 8 The barrier layer 41 in the reference Figure 8 In the etching process towards the sidewall of the contact hole structure 220, the exposed diffusion barrier layer 221 is also etched. Therefore, the conductive body portion 222, the dielectric layer 230, and the top surface of the diffusion barrier layer 221 located between the conductive body portion 222 and the first electrical connection portion 240 in the contact structure 220 form a via region. The presence of this via region further increases the second distance between the first barrier layer 241 and the sidewall of the contact structure 220 compared to the case where no via region is formed. This further reduces the risk of short circuits between the first electrical connection portion 240 and the contact structure 220. It is understood that in some embodiments, the exposed diffusion barrier layer may not be etched.

[0091] The semiconductor structure fabrication method provided in the above-described embodiments involves over-etching the first barrier layer 241 in the first electrical connection portion 240, resulting in a larger distance between the first barrier layer 241 and the sidewall of the contact structure 220 compared to the distance between the first conductive layer 242 and the sidewall of the contact structure 220. In other words, by altering the bottom contour of the first electrical connection portion 240, the distance between the first barrier layer 241 and its adjacent contact structure 220 is made relatively large, thus reducing the likelihood of them making contact. During the formation of the first electrical connection portion 240 and the second electrical connection portion 250, alignment deviations that could lead to a close distance between the first electrical connection portion 240 and the contact structure 220 are avoided, thereby reducing the risk of short circuits. Furthermore, the process window for forming the first electrical connection portion 240 and the second electrical connection portion 250 is increased.

[0092] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; a gate located on a portion of the substrate, and having a source or drain in the substrate located on both sides of the gate; A dielectric layer located on the substrate, and the dielectric layer covering the surface of the gate; A contact structure that penetrates the dielectric layer and is electrically connected to the source or the drain; A first electrical connection portion and a second electrical connection portion are arranged at intervals, both of which are located on the top surface of the dielectric layer, and the second electrical connection portion is also in contact with a portion of the top surface of the contact structure. The first electrical connection portion includes a first barrier layer and a first conductive layer stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer toward the contact structure and the contact structure is a first distance, and the distance between the sidewall of the first conductive layer toward the contact structure and the contact structure is a second distance. The first distance is greater than the second distance. The second electrical connection portion includes a second barrier layer and a second conductive layer stacked together. The second barrier layer is in contact with a portion of the top surface of the contact structure. The top surface of the contact structure, the sidewall of the second barrier layer, and the bottom surface of the second conductive layer form a void region.

2. The semiconductor structure according to claim 1, characterized in that, In the direction from the source to the drain, the width of the first barrier layer is smaller than the width of the first conductive layer.

3. The semiconductor structure according to claim 2, characterized in that, The ratio of the width of the first barrier layer to the width of the first conductive layer is 0.5 to 0.

9.

4. The semiconductor structure according to claim 1, characterized in that, The material of the first barrier layer includes TiN or TaN, and the material of the first conductive layer includes W.

5. The semiconductor structure according to claim 1, characterized in that, The thickness of the first barrier layer is less than the thickness of the first conductive layer.

6. The semiconductor structure according to claim 1, characterized in that, In the direction from the source to the drain, the width of the first barrier layer is equal to the width of the second barrier layer.

7. The semiconductor structure according to claim 1, characterized in that, The material of the first barrier layer is the same as the material of the second barrier layer; the material of the first conductive layer is the same as the material of the second conductive layer.

8. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the first barrier layer on the substrate surface lies within the orthographic projection of the first conductive layer on the substrate surface, and the orthographic projection area of ​​the first barrier layer on the substrate surface is smaller than the orthographic projection area of ​​the first conductive layer on the substrate surface.

9. The semiconductor structure according to claim 1, characterized in that, The contact structure includes: A conductive main body portion, the conductive main body portion penetrating the dielectric layer, and the second electrical connection portion contacting a portion of the surface of the conductive main body portion; A diffusion barrier layer is located on the sidewalls and bottom of the conductive body portion.

10. The semiconductor structure according to claim 9, characterized in that, The top surface of the diffusion barrier layer located between the conductive main body and the first electrical connection is lower than the top surface of the conductive main body, and the conductive main body, the dielectric layer, and the top surface of the diffusion barrier layer located between the conductive main body and the first electrical connection form a through-hole region.

11. The semiconductor structure according to claim 9, characterized in that, The diffusion barrier layer is made of the same material as the first barrier layer.

12. A method for fabricating a semiconductor structure, characterized in that, include: A substrate and a gate located on a portion of the substrate are provided, and a source or drain is located in the substrate on both sides of the gate; a dielectric layer is also provided on the substrate, and the dielectric layer covers the surface of the gate; A contact structure is formed, which penetrates the dielectric layer and is electrically connected to the source or the drain. A first electrical connection portion and a second electrical connection portion are formed at intervals, both the first and second electrical connection portions being located on the top surface of the dielectric layer, and the second electrical connection portion also contacting a portion of the top surface of the contact structure. The first electrical connection portion includes a first barrier layer and a first conductive layer stacked together. In the direction from the source to the drain, the distance between the sidewall of the first barrier layer toward the contact structure and the contact structure is a first distance, and the distance between the sidewall of the first conductive layer toward the contact structure and the contact structure is a second distance. The first distance is greater than the second distance. The second electrical connection portion includes a second barrier layer and a second conductive layer stacked together. The second barrier layer is in contact with a portion of the top surface of the contact structure. The top surface of the contact structure, the sidewall of the second barrier layer, and the bottom surface of the second conductive layer form a void region.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The process steps for forming the first electrical connection portion and the second electrical connection portion include: An initial barrier layer and an initial conductive layer are formed sequentially on the top surface of the dielectric layer, the initial barrier layer covering the top surface of the contact structure; The initial conductive layer and the initial barrier layer are patterned to form a first initial electrical connection portion and a second initial electrical connection portion that are spaced apart from each other. The second initial electrical connection portion is in contact with a portion of the top surface of the contact structure. The initial barrier layer in the first initial electrical connection portion is etched toward the sidewall of the contact structure, and the remaining initial barrier layer in the first initial electrical connection portion serves as the first barrier layer, and the remaining initial conductive layer in the first initial electrical connection portion serves as the first conductive layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, In the process step of etching the sidewall of the initial barrier layer in the first initial electrical connection portion toward the contact structure, the sidewall of the initial barrier layer in the second electrical connection portion is also etched.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, The contact structure includes a conductive body portion and a diffusion barrier layer located on the sidewall and bottom of the conductive body portion; in the process step of etching the initial barrier layer in the first initial electrical connection portion toward the sidewall of the contact hole structure, the exposed diffusion barrier layer is also etched.

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