Architecture and method for classification of decision tree ensembles

Abstract

An architecture for classification of decision tree ensembles comprises a rank computation block (1) and a tree processing block (2). The rank computation block (1) comprises a computation unit (10) for each feature f i to be classified. The computation unit (10) comprises a memory (11) and logic (12). The memory (11) is configured to hold thresholds of a tree in a decision tree ensemble, wherein the memory is arranged to hold the thresholds in a group for each feature f i to be classified. The thresholds in the group are ordered according to a threshold index. The logic (12) is arranged to perform a node comparison of the thresholds of the corresponding threshold group and to output a rank as a result of said comparison, wherein the rank represents an encoded address to access said thresholds. The tree processing block (2) comprises a tree processing unit (20) for each tree in the decision tree ensemble, and each processing unit is configured to determine a class of the feature f i to be classified from the rank.

Description

Technical Field

[0001] This disclosure relates to an architecture and method for classification of decision tree ensembles. Background Technology

[0002] Random forests, RF, or decision tree ensembles (DTEs) are used for various classification tasks in hardware and software. DTEs are intuitively evaluated by sequentially traversing each tree separately and then aggregating the outputs of each tree by average or majority voting. Another approach is to compute all node comparisons in parallel and convert the trees into Boolean functions that compute the tree outputs for aggregation or directly compute the aggregated output.

[0003] The decision tree ensemble classification architecture can be trained using machine learning algorithms such as random forests, AdaBoost, or gradient boosting trees. This architecture can be constructed as a hardware architecture for inferring the decision tree ensemble classification in FPGA or ASIC technologies. This architecture can be integrated into various applications in the field of edge machine learning, such as, but not limited to, smart sensors, wireless sensor networks, structural health monitoring, predictive maintenance, and healthcare.

[0004] The architecture of a decision tree ensemble classification or DTE hardware accelerator typically consists of a tree processing unit for each decision tree in the ensemble and an aggregation unit for computing the ensemble vote, such as... Figure 13 As shown. This tree processing unit can also be used independently as a hardware accelerator for a single decision tree.

[0005] Figure 14A An example of a single classification tree is shown. To predict the class of a new set of input features, each node of the tree will assign features f... i One of the nodes and the threshold t j The comparisons are performed. Starting from the root node, the comparison results in the following nodes define the path through the tree, which ends at a leaf node. The tree vote is assigned to the class C corresponding to the reached leaf. x Then, the votes of all trees in the set are aggregated using a majority voting method to obtain the final vote for the tree ensemble. The index of the feature f compared by the node, the threshold t, the class label C at the leaf node, and the structure of the tree are parameters defined through training.

[0006] Two types of architectures are widely used to implement decision trees. Essentially, the serial architecture stores all the parameters of the decision tree in memory and evaluates them from root to leaf. The parallel architecture has a comparator for each node and evaluates the entire tree at a time. More specifically, as... Figure 14BAs shown, the serial architecture traverses the decision tree of the trained model from the root to the leaf nodes. At each node, it retrieves the feature input and the threshold for the given node from memory or an input multiplexer. It then compares the two and selects the left or right sub-address as the next node to visit. It performs this operation until it reaches a leaf node and outputs the corresponding class vote. Figure 14C As shown, the parallel architecture computes comparisons of all nodes in the tree at once. Each comparator represents a tree node. Thresholds are stored in the comparator's register, and the comparator is connected to the feature input based on the node it represents. Tree voting is computed based on the comparator outputs using Boolean functions representing the tree structure. The Boolean functions are specific to the trained model and can be derived from the tree, as shown below.

[0007] The classification tree in DTE can be mathematically represented as a rooted, directed, acyclic graph DT=(V,D,E,C), with the following notation:

[0008] V vertex set Where L is the set of leaf nodes and N is the set of nodes containing the threshold. The set of internal nodes corresponding to feature f i one,

[0009] D is a Boolean variable d defined by node comparison. x set For each node, ,

[0010] The set of E edges ,in Marked as , to define when processing trees, in d x On which result should the edge be retrieved, and

[0011] A collection of class C, which consists of Assign it to a leaf node.

[0012] For each class A set of paths Defined by the following formula:

[0013]

[0014] for ,in , It is the root node ,for as well as ,in .

[0015] Figure 14CThe parallel architecture in the code implements each node as a fixed comparator. The tree structure can be formalized as a Boolean function. It calculates the tree vote for class c based on the comparator output. The Boolean function can be represented as:

[0016]

[0017] in , .

[0018] For example, Figure 14C (2) The tree shown leads to

[0019] as well as

[0020] .

[0021] However, both serial and parallel architectures have room for improvement.

[0022] The purpose of this disclosure is to provide an architecture and a method for decision tree ensemble classification, which improve the decision tree ensemble classification architecture in terms of, for example, speed, energy consumption and / or area.

[0023] These objectives are achieved through the subject matter of the independent claims. Further improvements and embodiments are described in the dependent claims. Summary of the Invention

[0024] It should be understood that any feature described in relation to any embodiment may be used alone or in combination with other features described herein, and may also be used in combination with one or more features of any other embodiment, or in any combination with any other feature of any other embodiment, unless otherwise stated. Furthermore, equivalents and modifications not described below may be employed without departing from the scope of the architecture for classification of decision tree ensembles and the method for classification of decision tree ensembles as defined in the appended claims.

[0025] The following relates to an improved concept in the field of decision tree ensemble classification. The proposed concept offers an architecture and method for solving inference in classification and regression trees, as well as decision tree ensembles (DTEs). The proposed concept can be implemented on hardware architectures such as FPGA or ASIC technology. However, the method can also be implemented in software.

[0026] The proposed concept suggests grouping and pre-sorting all comparisons for a given decision tree ensemble based on thresholds to quickly compute all nodes using logic (e.g., binary search or in-memory search). Furthermore, the architecture can be supplemented by maintaining a lookup table of pre-computed entries to further accelerate classification.

[0027] In at least one embodiment, the architecture for classification in decision tree ensembles includes a rank computation block and a tree processing block. The rank computation block includes a computation unit for each feature in the set of features to be classified. Each computation unit includes memory and logic. The memory is configured to store thresholds for the trees in the decision tree ensemble. The memory is configured to store the thresholds in a group for each feature. Furthermore, the thresholds in the group are pre-sorted according to a threshold index to allow for efficient search algorithms, such as binary search. The threshold index allows for defining search criteria, such as "<" or ">".

[0028] The logic is configured to compare thresholds for corresponding threshold groups and output a rank for the evaluated feature value. The rank represents an encoded address that represents a threshold. The tree processing block is configured to determine the class of the set of features to be classified based on the rank. For example, in some embodiments, the tree processing block includes one tree processing unit for each tree in the decision tree ensemble. Each processing unit is configured to determine the class of the set of features to be classified based on the rank. In other embodiments, there may be only one tree processing unit, which includes multiple lookup tables and combiners, which will be discussed in more detail below.

[0029] Preliminary results indicate that the new architecture can keep pace with serial and parallel architectures in terms of hardware cost and energy efficiency, with each architecture only outperforming the other in one of two quality factors. The hierarchy can be used for further processing via tree-processing blocks because they retain the same information as the computed comparisons across all nodes.

[0030] In at least one embodiment, the features in the set of features to be classified are represented as f. i , with feature index , where I represents the number of features to be classified. The threshold represents a node in the tree in the decision tree ensemble.

[0031] This logic is configured to receive the feature f to be classified. i The system takes a set of values ​​for each feature and performs a search that returns a rank for each feature, classifying the threshold as either less than or greater than the feature's value. For example, the rank is output to the corresponding tree processing unit. Finally, the tree processing unit is configured to determine the class based on a Boolean function evaluating the received rank, each Boolean function representing the structure of the decision tree in the decision tree ensemble. Alternatively, the rank is output to the corresponding lookup table.

[0032] In at least one embodiment, the tree processing block includes an aggregation unit configured to receive determined classes from the tree processing unit and form an integration vote based on the determined classes.

[0033] In at least one embodiment of the memory, the memory includes a set of storage units for each feature in a set of features to be classified. Storage units within the set can be addressed according to a threshold index.

[0034] In at least one embodiment, the logic includes a comparator that also includes a first input operable to receive a feature and a second input operable to receive a threshold from memory.

[0035] In at least one embodiment, the tree processing unit includes one or more comparators, one or more of which are configured to perform address decoding of the received level to evaluate a Boolean function based on the address-decoded level. The comparators are operable to perform comparisons based on levels, where a level is a representation of a node comparison corresponding to a threshold group. In a sense, the level is decoded for address comparison.

[0036] In at least one embodiment, each computation unit in the rank computation block is connected to a dedicated lookup table. The lookup table includes an input side operable to receive a dedicated rank from the computation unit connected to it. Furthermore, the lookup table is operable to output intermediate values, such as intermediate values ​​based on the input rank.

[0037] In at least one embodiment, each tree processing unit may be connected to a dedicated lookup table. The lookup table includes an output side configured to provide intermediate values ​​to the tree processing units connected to it. The tree processing units are operable to determine a class of a set of features to be classified based on the received intermediate values.

[0038] In other embodiments, a dedicated lookup table for each tree processing unit may no longer exist. Instead, the lookup table can be considered part of the tree processing block and can be supplemented by a combiner. For all trees, the contents corresponding to the tree structure are combined and stored in a lookup table for each feature. The lookup table entries correspond to possible configurations and, together with the combiner, form a tree processing block. However, several trees can also be internally combined into a "sub-integration".

[0039] In at least one embodiment, the architecture further includes a combiner with an arithmetic unit. The combiner is operable to receive intermediate values ​​and is operable to combine and / or weight the intermediate values ​​and output a class of features to be classified. The combiner can be implemented as a common unit for all tree or sub-integrations.

[0040] In at least one embodiment, the lookup table is implemented based on an associative memory that includes one or more comparators operable to perform "less than" or "greater than" comparisons.

[0041] In at least one embodiment, the classification method of decision tree ensemble includes the following steps: For each feature to be classified, a first threshold of the decision tree in the decision tree ensemble is stored in a group. The thresholds of the group are sorted according to the threshold index. Node comparisons of the thresholds corresponding to the threshold groups are performed. A rank is output as a result of the node comparisons, where the rank represents the encoded address used to evaluate the threshold. Finally, the class of the set of features to be classified is determined based on the rank.

[0042] In at least one embodiment, the features in the set of features to be classified are represented as f. i , with feature index Here, I represents the number of features to be classified. The threshold represents a node in the tree in the decision tree ensemble. The method further includes the following steps: receiving the features to be classified via logic and performing a search using that logic, which returns a rank for each feature, that rank divides the threshold into values ​​less than or greater than the feature value. The ranks are output to the corresponding tree processing units. The class of the features to be classified is determined by evaluating Boolean functions based on the received ranks, where each Boolean function represents a tree in the decision tree ensemble.

[0043] In at least one embodiment, the rank is determined using logic based on a binary search. Alternatively, the rank is determined based on a search in memory.

[0044] In at least one embodiment, the evaluation of the decision tree involves filling a lookup table with pre-computed values, which are stored as lookup table entries, and wherein the class is determined based on the lookup table entries.

[0045] In at least one embodiment, lookup table entries are determined by training software. The training software determines the allocation of lookup table entries such that the mathematical descriptions of both the classification architecture and the DTE are equivalent.

[0046] The following description of the accompanying drawings of the exemplary embodiments may further illustrate and explain aspects of the improved concept. Components and parts having the same structure and effect are shown with equivalent reference numerals. Descriptions of components and parts need not be repeated for each of the following figures, provided that the components and parts correspond functionally to each other in different figures.

[0047] Further aspects, features, and advantages will become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0048] In the attached diagram:

[0049] Figure 1 An example top-level diagram of an architecture used for decision tree ensemble classification is shown.

[0050] Figure 2An example embodiment of the computing unit is shown.

[0051] Figure 3 An example decision tree ensemble is shown to illustrate grouping and pre-sorting schemes.

[0052] Figure 4 An example embodiment of the computing unit is shown.

[0053] Figure 5 The FOM size of example architectures for several models trained on different datasets using different training algorithms is shown.

[0054] Figure 6 Energy comparisons of example architectures for several models trained on different datasets using different training algorithms are shown.

[0055] Figure 7 Another example embodiment of the computing unit is shown.

[0056] Figure 8 This shows the classification results calculated based on the rank using a LUT.

[0057] Figure 9 An example embodiment combining in-memory hierarchical calculation and LUT lookup is shown.

[0058] Figure 10 The classification results calculated based on LUT entries are shown.

[0059] Figure 11 Further details of an example embodiment of a combiner with the characteristic I=7 are shown.

[0060] Figure 12 Further details of an example embodiment of the combiner are shown.

[0061] Figure 13 The existing technical architecture for decision tree ensemble classification is shown, and

[0062] Figures 14A to 14C An example of existing technology for the concept of classification is shown. Detailed Implementation

[0063] Figure 1 A sample top-level diagram of a classification architecture for decision tree ensembles is shown. This architecture includes a rank computation block 1 and a tree processing block 2. The rank computation block 1 comprises multiple computational units 10. In fact, for each feature f to be classified... i There is a dedicated computing unit (index i or feature index represents an integer representing the i features to be classified). Each computing unit also includes memory 11 and logic 12.

[0064] Memory 11 includes multiple storage units and is configured to store multiple thresholds according to the decision trees in the decision tree ensemble. In other words, the memory stores the thresholds of the trees as features of the decision tree ensemble. The thresholds are grouped into feature groups, which will be discussed in more detail below. Basically, the memory includes a set of thresholds for each feature to be classified. The thresholds in the groups are sorted according to the threshold index. Logic 12 allows access to the thresholds corresponding to the threshold groups. According to the process discussed separately below, the logic outputs the rank of the accessed threshold. The rank represents the encoded address of the accessed threshold and, in turn, represents the threshold.

[0065] Tree processing block 2 includes a tree processing unit 20 for each tree in the decision tree ensemble. The tree processing unit is configured to perform classification or tree voting. In fact, each processing unit is configured to evaluate a Boolean function representing the tree in the decision tree ensemble based on its ranking.

[0066] Boolean functions can be implemented using soft logic on an FPGA or hard-wired logic on an ASIC, or using the schemes discussed below. The hierarchy is received from the hierarchy calculation block and the corresponding calculation unit. The tree processing block also includes an aggregation unit 21 (or tree combiner). This unit receives votes (or classifications) from the tree processing unit and forms its integrated vote. In other words, the aggregation unit performs majority voting.

[0067] Figure 2 An example embodiment of the computing unit is shown in more detail. Memory 11 includes multiple storage units, each with a unique address. The diagram indicates that the memory stores thresholds, which are ordered according to threshold indices. The thresholds stored in memory belong to a dedicated group associated with a corresponding feature (f1 in this example). This feature can be input via input side 13 of comparator 14 (indicated by "<" in the diagram). Another input 15 is configured to access the memory and thereby receive the threshold from the memory. Thus, the comparator can compare the feature associated with the dedicated group according to the tree definition (f1 in this example). Furthermore, logic 12 is configured to access comparator 14 via another input side 16. As a result of this control, the comparator compares the input feature with the threshold. The memory outputs a corresponding coded address, which in turn indicates the threshold / feature comparison (or tree node). The levels can be used for further processing via tree processing blocks because they store the same information as the calculated comparisons for all nodes.

[0068] In summary, similar to a serial architecture, the computation unit includes a comparator and memory. However, the memory contains a set of thresholds instead of a complete decision tree. Comparator 14 is only connected to the corresponding feature, thus eliminating the complexity of the input multiplexer, which is often required in other architectures. Furthermore, the memory only contains thresholds and not tree structure information such as feature indices or sub-addresses, which significantly reduces memory size. For example, the search logic performs a binary search to quickly compare the input features with the thresholds.

[0069] Figure 3 An example decision tree ensemble is shown to illustrate the grouping and pre-sorting scheme. The proposed concept is based on pre-sorting the thresholds, for example, to speed up comparisons. The figure illustrates an example of how the thresholds are grouped and sorted. The figure depicts three example decision trees, each including features f1, f2, and f3, and two example classes C1 and C2. The tree nodes are considered as thresholds. (with threshold index j) and corresponding input feature f i Comparisons between (with feature index i). Thresholds for all decision trees in the ensemble can be grouped by the corresponding feature index of each node. Table 1 shows example groups of thresholds obtained by feature. Threshold Able to sort according to sorting criteria, for example Logical 12 can be configured to perform fast search operations using this sorting criterion. Examples of sorted group results are shown in Table 2.

[0070]

[0071] Table 1: Thresholds for Grouping by Feature

[0072]

[0073] Table 2: Groups sorted by characteristics

[0074] The generated threshold groups are sorted individually by threshold, where the sorting criteria are as follows: Implement a fast search method, such as binary search. Instead of serially traversing the tree or computing all nodes, DTE can be evaluated by performing a binary search on each feature in the corresponding threshold group. The binary search produces an address (i.e., a rank) for each feature, which divides the threshold into values ​​less than or greater than the feature. These addresses, i.e., the ranks of the features, hold the same information as the computed comparisons for all nodes. Therefore, tree voting can be computed using Boolean functions (e.g., as done in parallel architectures) with far fewer comparisons required.

[0075] The complete architecture includes a computational unit for each feature and a tree voting function for each tree, as well as optional aggregation units to form, for example... Figure 1 The integration shown is similar to that of the parallel architecture. However, the input is an encoded address, while the parallel architecture encodes each comparison as a bit. Therefore, the tree voting function of the parallel architecture is extended to different Boolean functions. Using the terminology introduced above in the introductory section of this disclosure, the tree structure can be formalized as a Boolean function. It calculates the tree vote for class c based on the comparator output or rank R. The Boolean function can be represented as:

[0076] ,

[0077] Here r k,m This indicates that at node v k,m The calculated rank of the features used and a k,m In a pre-sorted dedicated threshold group, node v k,m The address of the threshold.

[0078] Figure 4 An example embodiment of the computing unit is shown.

[0079] The rank computation block provides multiple corresponding ranks, which are input to tree processing block 2, i.e., to the computation unit to vote on the corresponding class. One implementation of the computation unit is similar to the parallel architecture shown in Figure 14. The computation unit includes a comparator 22 for each tree node. However, the comparator in the proposed concept decodes the rank address and does not perform actual node comparisons. In fact, the address represents the comparison and can be directly used for Boolean function computation. For example, when mapped to FPGA or ASIC technology, address decoding can be minimized by using tree voting functionality through synthesis tools.

[0080] Some of the benefits of the proposed concept include:

[0081] ● The memory only needs to contain the threshold for the corresponding feature. The sub-addresses and feature indices of the nodes do not need to be stored, which greatly reduces memory usage.

[0082] ● Duplicates in the grouping threshold can be removed because they do not provide additional information for memory access, such as through binary search. This allows for even further reductions in memory size and memory access energy.

[0083] ● Compared to serial architectures, it eliminates the need to fetch feature inputs from memory or input multiplexers. This reduces circuit complexity and power consumption.

[0084] ● Decision trees are often unbalanced, which can lead to varying execution times for different decisions. This makes parallelization between trees more difficult and requires synchronization. The proposed concept suggests searching for thresholds in a balanced manner, such as using binary search, thereby reducing circuit complexity and execution time. While execution time may vary from tree to tree, it can be adjusted by introducing parallelization into the search comparison so that it remains constant across decisions.

[0085] ● Binary search performs far fewer comparisons than parallel architectures, which compute all the comparisons. In some cases, binary search even computes fewer comparisons than serial architectures, especially when long branches appear in the tree. This reduction in execution time, energy, or circuit size depends on the amount of parallelization.

[0086] The benefits discussed above are also evident in the experimental results. To compare the number of comparisons between the serial and parallel architectures, two models were trained on different datasets, and statistical analysis was performed on both models using the corresponding test datasets. For the parallel architecture, the number of comparisons was simply the number of nodes in all trees. For the serial architecture, tree iteration was performed on the real test data to statistically estimate the number of comparisons for each inference. Similarly, a binary search was performed on the test data to obtain the number for the proposed architecture.

[0087] Table 1 shows the statistics or exact number of comparisons for two models trained on different datasets. Since the execution time of the serial architecture is irregular due to the imbalance of the trees, the table contains (minimum, average, maximum) tuples.

[0088]

[0089] Table 3: Number of comparisons for the example architecture and two different datasets.

[0090] To compare the hardware area and power consumption of the architectures, three architectures were implemented in SystemVerilog and synthesized against commercial FPGAs. After synthesis, the hardware area quality factor (FOM) was defined as FF + 2∙LUT based on flip-flop (FF) and look-up table (LUT) resources. Power consumption was estimated using power estimation tools provided by the FPGA vendors and based on simulated switching activity categorized with actual test data.

[0091] Figure 5 and Figure 6The table shows a comparison of FOM size and energy for all three architectures of several models trained on different datasets. The results clearly demonstrate that the new architecture performs well in both quality factors, even outperforming the serial architecture in FOM size for most datasets. On the other hand, the serial architecture exhibits the worst energy efficiency, while the parallel architecture shows the worst performance in terms of FOM size. This makes the architecture widely applicable and proves to be the best candidate for adjusting the tradeoff between size and energy by introducing parallelization.

[0092] Figure 7 Another example embodiment of the computation unit is shown. As described above, the rank computation block 1 provides ranks that are input to the tree processing block 2, i.e., to the computation unit 10, to evaluate or vote on a class. By using ranks, the computational effort required to perform decision tree evaluation by feature values ​​can be reduced compared to directly processing feature values. In fact, computational steps can be performed to pre-compute and remain available in lookup table 17 (or LUT). Since a single LUT (whose input includes all features) can become very large, one LUT 17 is used for each feature. As shown, the LUT receives ranks from the rank computation block and outputs intermediate results tmp_results. The intermediate results can be processed by a relatively simple structured algorithm (or "combiner" 18) to process the final classification results.

[0093] This leads to decisive advantages compared to simpler implementations, such as high speeds with relatively low power requirements. The classification includes several parallel and independent memory accesses and a small, energy-efficient, and parallel algorithm. The use of LUTs allows for high flexibility, as the content of the LUTs can be freely chosen even post-manufacturing in ASIC technology. Furthermore, the hardware architecture can be very uniform, and the complete reconfigurability of the combiner is possible. This allows for mapping arbitrary DTE models.

[0094] Figure 8 An example embodiment of a combiner for computing classification results from a LUT is shown. This diagram can be used to demonstrate the principles of LUTs in a simplified or advanced manner. More detailed example implementations will be described below.

[0095] Combiner 18 comprises multiple lookup tables. In fact, there exists a dedicated LUT to receive the corresponding rank, denoted as rank[i] in the diagram. In other words, there is a dedicated LUT[i] for each feature i. The LUT has training entries for each value of the corresponding rank, generated by the training process, and representing the structure and nodes of the corresponding decision tree. The LUT outputs an intermediate result tmp_result[i]. The intermediate result can be further processed to combine multiple features into tree voting and / or voting of sub-integrations of multiple trees. Voting can be further processed, for example, by weighting them in the multiplier with their respective weights, denoted as w[m], where And M is the total number of trees and / or sub-integrations. The adder can combine intermediate results (weighted or unweighted) into a combined intermediate result. This result can be fed into a comparator to be compared with a threshold c_thr to arrive at a classification result. The portion following the weighting may already be part of the aggregation unit.

[0096] Compared to the example implementation without an attached LUT, the content of the LUT needs to be determined separately. The content is determined according to predetermined criteria. For example, the content (or LUT entry) should represent an equivalent description of the hardware architecture. Thus, the LUT entry can describe variations in the hardware (typically implemented as an ASIC) or the feature set. LUT entries are highly configurable and can be found through training based on a trained model, such as using solver software like the open-source software Z3 theorem prover. For example, a description of the hardware architecture on one hand and a description of the DTE on the other hand are input into the solver. The solver now finds an assignment of entries in LUT LUT[i] where the two descriptions are equivalent for all possible input assignments (i.e., ranks or eigenvalues).

[0097] The use of solvers (such as SMT / SAT solvers) enables hardware implementations to conform to specified models and achieve matching. The use of solvers to compute LUT entries has been described in various technical fields of FPGA logic synthesis. However, due to its high complexity, it is not used in practice. The proposed concept involves the use of solver software in the fields of AI (Artificial Intelligence) and ML (Machine Learning).

[0098] By separating the explicit encoding from the LUT content, the DTE model can be significantly compressed. Compression rates of up to 400% have been achieved so far compared to explicitly assigning all leaf nodes of the tree to each output bit for each LUT. Furthermore, the proposed architecture does not directly use the actual values ​​of the features, but instead uses their ranks as the addresses of the LUT. In the DTE tree of each node, starting from the root, feature values ​​are compared with trained thresholds. For each feature, there are several thresholds that define intervals. The ultimate key information about these values ​​is which interval they fall within. If the thresholds are ordered in ascending or descending order according to a sorting criterion, as implemented in the rank computation block, the index of the interval in which the feature value lies corresponds to its rank. The number of intervals is significantly less than all possible values ​​that a feature can assume. Therefore, fewer bits are required for encoding. The bit width of a feature, or feature rank, corresponds to the bit width of the LUT address input. For example, if a 16-bit feature can be represented by a 4-bit rank, then the LUT must consist of only 16 entries instead of 16384. By using pre-sorting, features can be reduced to ranks.

[0099] The described classifier hardware concept (a combiner for calculating classification results from LUT intermediates) can further improve upon the proposed concept. Pre-compiling the LUT contents using training (e.g., a solver such as an SMT / SAT solver) provides improved results in terms of memory and circuit size. Using actual values ​​of ranks instead of features allows for a minimum reduction in memory size. Furthermore, the combiner logic is small and energy-efficient despite being fully reconfigurable. Thus, there are no limitations on the grouping of LUT outputs and therefore on the generation of content. Special emphasis is placed on the summation of variable bit-width groups and the simple comparison with a threshold.

[0100] Figure 9 An example embodiment of in-memory hierarchy computation is shown. While the near-memory computation of hierarchy described above (i.e., based on binary search operations) is already very efficient and fast, there may be applications that represent potential bottlenecks to the classifier hardware performance. It may be necessary to estimate a threshold number of log2 of clock cycles for each feature (or the corresponding bit width of the hierarchy). Through pipelined processes, all other steps in the classification process typically have a throughput of one classification per clock cycle. Based on comparator logic, an additional concept allows feature hierarchy computation to be performed within memory itself.

[0101] The diagram illustrates a computation unit 10 for the features to be classified. This unit includes a memory 11 for pre-sorting thresholds for given features and groups. Furthermore, the unit includes logic 12 for performing comparisons with the thresholds. Based on the comparison, the logic outputs a 1-hot encoded rank, which is then input into the corresponding lookup table. Instead of binary encoding, each possible state value may have only a single line. Only the single line corresponding to the current rank is active (“hot”). Based on the entries in the lookup table LUT, the computation unit outputs an intermediate result, tmp_result.

[0102] This structure is similar to that of Content Addressable memory (CAM) supplemented by a lookup table approach. However, unlike a regular CAM, the computation units perform comparisons with "<" (or ">") instead of "=". This means that matching lines of all threshold memory units with values ​​less than (or greater than) the applied feature value are asserted. This implements hierarchical thermometer encoding. The limit of the next larger (or smaller) threshold can be determined from the thermometer encoding and converted into 1-hot encoding via inverters and gates in each memory row. For example, the result can be directly used as a word line of a LUT.

[0103] In this example embodiment, most peripheral components (such as external search logic and address decoders for LUT memory) are no longer required. Since the memory is also used for read-only operations, memory cells can be optimized for leakage current (e.g., by using Schmitt trigger structures or ULP diodes) and read performance. Write operations are only required when initializing content. This also allows for the use of NVRAM or ROM to improve power and area efficiency. In addition to performance gains calculated per clock cycle, additional power and area savings are achieved. Instead of logarithmic memory accesses for binary searches, only a single access is needed. For this, address decoders are also unnecessary, but energy consumption on the matching line increases. This is likely in an area similar to the peripheral regions, so ultimately each access will result in similar energy consumption.

[0104] Figure 10 Another example embodiment of a combiner for computing classification results from a LUT is shown. A possible implementation will be discussed. Figure 8 The simplified structure of the combiner shown is described in more detail. It can be seen that while the complexity is slightly higher, the structure remains very regular and fully reconfigurable.

[0105] A LUT[i] is described, which is dedicated to rank[i]. The individual bits of the intermediate LUT result are named tmp_result[i][x], where... , X is the total bit width of the LUT. These individual bits tmp_result[i][x] are sequentially combined into Q non-overlapping binary values c[i][q] with a configurable bit width p[q], where , which is the index of the Q individual values. These binary values c[i][q] are summed for all features f i , where , to obtain the sum . The sum s[q] is then compared with the corresponding sum threshold st[q], i.e., v[q] = s[q]<st[q]. For consecutive, non-overlapping groups of configurable size , the comparison results v[q] are combined into M group votes through AND-reduction . The results of these groups may correspond to the votes of individual trees and / or sub-ensembles of the entire DTE. The group vote g[m] can be scaled by an adjustable weight w[m] and summed . The final class membership is determined by the threshold c_thr, for example . The subsequent part starting from weighting may already be part of the aggregation unit.

[0106] Figure 11shows further details of an example embodiment of the combiner. The implementation of each part (and the illustration of the LUT) is described below using an example of seven features (i.e., I=7). The first step (selecting / combining and adding the respective bits of the index x with the binary number c[i][q]) is performed by a multiplexer and an adder. Here, the LUT outputs are first converted and added column-wise, that is, the 7 LSBs of all LUTs (index i) are added with 3-bit values. The result is added to the 3-bit value of the next column (after the 3-bit value of the next column is actually multiplied by 2, that is, after being shifted left by one bit). Therefore, the p[1] column corresponding to the bit width of the value c[i][1] produces s[1], that is, the sum of 7 added p[1] bit values. For the next column with index x+1=p[1]+1 that contributes to the next sum s[2], the 3 bits from the sum of tmp_result[i][p[1]] and the previous value are not selected, but the constant "0" is selected by the multiplexer, thus the adder chain is interrupted. For each column of the word width x of the LUT or each bit x, there is a configuration bit cfg_mux[x] containing the setting of the corresponding multiplexer. Therefore, the bit widths of all c[i][q] are freely configurable. By limiting the threshold to 2^(p[q]-2), comparing s[q]<st[q] (=2^(p[q]-2)) is also trivial. Only the value "00" of the two most significant bits (MSB) in s[q] is checked, and the least significant bit (LSB) is irrelevant. If neither bit is set, v[q]=1. To achieve full reconfigurability of the classifier, each column can be implemented equally, for example, comprising a 3-bit adder as well as a 3-bit multiplexer with configuration bits and 2-bit comparator logic, however, only the result of the next multiplexer (indexed x+1) being set to interrupt the adder chain is relevant, and with Figure 10 corresponds to the values shown in. The remaining results s[x], v[x] are ignored.

[0107] Figure 12 shows further details of an example embodiment of the combiner. This figure shows the "AND-OR" chain of the combiner. As a next step, the result of the comparator logic v[q] is AND-reduced to the value g[m]. This is done by the depicted AND-OR chain for all comparator results. The configuration bit cfg_mux[x+1] is capable of masking irrelevant values v[x], so that only relevant values are considered. Furthermore, another set of configuration bits cfg_and[x] interrupts the AND-OR chain at the boundaries between groups and can be used to determine the relevant value g[x], where cfg_and[x]=1, and the relevant value g[x] corresponds to Figure 10 the value g[m] shown in.

[0108] The votes (or classifications) from the combiner unit can be evaluated by a separate aggregation unit that performs majority voting. Optionally, a 1-bit value g[m] can be multiplied by a weight w[m]. This operation can be performed by an AND gate group or multiplexer that reduces the weights g[m] = 0, but may not be necessary for the applications discussed herein. Column x, regardless of its value, is configured with a weight of "0". The weighted results are summed to a total c_sum using an adder tree. The comparator with an adjustable threshold c_thr ultimately outputs information about which class the features of the classifier input correspond to.

[0109] So far, the AND / OR arrays, XOR circuits, and the algorithms described above used to calculate the overall result from the LUT values ​​have been examined. While the proposed implementations have performed well, the possibility of more compact and efficient structures to solve this task and further improve the compression ratio cannot be ruled out.

[0110] Although the description of the improved concept includes many details, these details should not be construed as limiting the scope of the concept or what has been or could be claimed, but rather as a description of features specific to certain embodiments of the invention. Certain features described in connection with individual embodiments in this disclosure may also be implemented in combination in a single embodiment. On the other hand, various features described in connection with individual embodiments may also be implemented individually or in any suitable sub-combination in several embodiments. Furthermore, although the foregoing may describe features as functioning in certain combinations, and even initially claimed to be so, in some cases one or more features may be removed from the claimed combination, and the claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0111] Therefore, even though the operations in the accompanying figures are presented in a specific order, this should not be construed as meaning that these operations must be performed in the order shown or sequentially, or that all the operations shown must be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0112] Many implementations have been described. However, various modifications can be made without departing from the spirit and scope of the invention. Therefore, other embodiments are also within the scope of the claims.

[0113] Figure Labels

[0114] Level 1 Calculation Block

[0115] 2 Tree processing blocks

[0116] 10 Computing Units

[0117] 11 Threshold Memory

[0118] 12 Logic

[0119] 13 Input Comparator

[0120] 14 Comparators

[0121] 15 Comparator Inputs

[0122] 16 Comparator Outputs

[0123] 17. Lookup Table

[0124] 18 Combiners

[0125] 20 Tree Processing Units

[0126] 21 Aggregation Unit

Claims

1. A classification system for decision tree ensembles, comprising a rank computation block (1) and a tree processing block (2), wherein: - The hierarchical calculation block (1) includes a calculation unit (10) for each feature of the set of features to be classified, wherein each calculation unit (10) includes a memory (11) and logic (12). - The memory (11) is configured to store thresholds for the decision trees in the decision tree ensemble, wherein the memory is configured to store the thresholds in a group for each feature, and wherein the thresholds in the group are sorted according to a threshold index. - The logic (12) is configured to perform node comparison of the thresholds of the corresponding threshold group and output the level as the comparison result, where the level represents the encoded address representing the threshold, and - The tree processing block (2) used for trees in decision tree ensembles is configured to determine the class of features to be classified based on the rank. The feature is represented as f i , with feature index , where I represents the number of features to be classified, and the threshold represents the node of the tree in the decision tree ensemble, where: - The logic (12) is configured to receive the features to be classified and perform a search, the search returning a level for each feature that classifies the threshold into values ​​less than or greater than the feature value. - The levels are respectively output to the corresponding tree processing unit (20), and The tree processing unit (20) is configured to determine the class by evaluating Boolean functions based on the received rank, each Boolean function representing a decision tree in the decision tree ensemble.

2. The system according to claim 1, wherein the tree processing block (2) includes an aggregation unit (21) configured to receive determined classes from the tree processing unit (20) and form an integrated vote based on the determined classes.

3. The system according to claim 1, wherein the memory (11) comprises: - A set of storage units for each feature in the set of features to be classified, and - Storage units within a group can be addressed using threshold indexes.

4. The system according to claim 1, wherein The logic (12) includes a comparator (14) comprising a first input operable to receive a feature and a second input operable to receive a threshold from the memory (11), wherein... - The comparator (14) is operable to perform node comparisons of thresholds for corresponding threshold groups.

5. The system of claim 4, wherein the tree processing unit (20) includes one or more comparators (22) configured to perform address decoding of the received level to evaluate a Boolean function based on the address-decoded level.

6. The system according to claim 1, wherein - Each computational unit (10) is connected to the corresponding lookup table (17). - The lookup table (17) includes an input side operable to receive a dedicated level from a computing unit (10) connected to the lookup table, and - The lookup table (17) is operable to output intermediate values ​​based on the levels received on the input side.

7. The system according to claim 6, wherein - Each level calculation block (1) is connected to the corresponding lookup table (17). - The lookup table (17) includes an output side operable to provide intermediate values ​​to a tree processing unit (20) connected to the lookup table, and - The tree processing unit (20) is operable to determine the class of the feature to be classified based on the received intermediate value.

8. The system of claim 6 further includes a combiner (18) having an arithmetic unit, the combiner being operable to receive the intermediate values ​​and operable to combine and / or weight the intermediate values ​​and output a class of features to be classified.

9. The system according to claim 6, wherein - The tree processing block (2) includes one or more lookup tables, and - Lookup tables are implemented based on associative memory that includes one or more comparators operable to perform "less than" or "greater than" comparisons.

10. A classification method using decision tree ensembles, comprising the following steps: - For each feature to be classified, the thresholds representing the decision trees in the decision tree ensemble are saved as a set. - Sort the thresholds of the groups according to the threshold index. - Perform node comparisons of the thresholds for the corresponding threshold groups. - Output the level as the result of the node comparison, where the level represents the encoded address representing the threshold, and - Determine the category of the features to be classified based on the level. The feature to be classified is represented as f. i , with feature index Where I represents the number of features to be classified, and the threshold represents a node in the tree in the decision tree ensemble, the method includes the following additional steps: - The features to be classified are received via logic (12), and a search is performed, which returns a rank for each feature that classifies the threshold into values ​​less than or greater than the feature value. - Output the levels to the corresponding tree processing units (20), and - The class of the feature to be classified is determined by evaluating Boolean functions based on the received rank, each Boolean function representing a tree in the decision tree ensemble.

11. The method of claim 10, wherein - Use logic (12) to determine the level based on binary search, or - Determine the level based on memory.

12. The method of claim 10, wherein the evaluation of the decision tree involves a lookup table (17) with pre-computed values, the pre-computed values ​​being stored as lookup table entries, and wherein the class is determined based on the lookup table entries.

13. The method of claim 12, wherein the lookup table entries are determined by training software that determines the allocation of lookup table entries such that the classification architecture and the mathematical description of the DTE are equivalent.

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