Semiconductor test structure, test apparatus and semiconductor test method

Abstract

The application provides a semiconductor test structure, a test device and a semiconductor test method. The semiconductor test structure comprises: a component to be tested, a first test terminal of the component to be tested being electrically connected to a first pad to receive a first voltage, a second test terminal of the component to be tested being electrically connected to a second pad to receive a second voltage, the second voltage being less than the first voltage; and a switch device, a first control terminal of the switch device being electrically connected to the first pad, a second control terminal of the switch device being electrically connected to the first test terminal, the switch device being turned on in response to a disconnection of a connecting line between the first test terminal and the first pad, so as to raise the current at the first pad to a preset threshold current. The above technical solution introduces a switch device in the test structure, and the switch device is turned on in response to the disconnection of the connecting line between the first test terminal and the first pad, so that the current at the first pad is raised to the preset threshold current, the test machine can timely capture the current change, the test is stopped and the component to be tested is determined to be failed, so that the machine time is saved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor testing structure, testing equipment, and semiconductor testing method. Background Technology

[0002] Time-dependent dielectric breakdown (TDDB) is a time-related reliability test commonly used to measure the dielectric performance of structures such as metal-insulator-metal (MIM), metal-oxide-metal (MOM), inter-metal-dielectric (IMD), and metal-oxide-semiconductor (MOS). Generally, the electric field applied in TDDB is lower than the intrinsic breakdown field strength of the dielectric layer and does not induce intrinsic breakdown, but breakdown still occurs after a certain period of time.

[0003] Figure 1 The diagram shows a schematic of a semiconductor device structure for a time-based breakdown test. Figure 2 and Figure 3 The diagram shows the current change trend of a semiconductor device during breakdown, where the horizontal axis represents the applied voltage time and the vertical axis represents the current flowing through the gate. Please refer to [link to relevant documentation]. Figure 1 The semiconductor device under test includes a substrate 10, a source 11, a drain 12, and a gate 13. A gate dielectric layer 14 exists between the gate 13 and the substrate 10. In the time-lapse breakdown test circuit, the gate 13 and the substrate 10 of the transistor are connected to the circuit; for example, a voltage VDD is applied to the gate 13, and the substrate 10 is connected to GND (i.e., zero voltage is applied), and the change in the gate 13 current is measured. After a long period of voltage application, the gate 13 breaks down. During breakdown, the gate current exhibits two forms, such as... Figure 2 and Figure 3 As shown.

[0004] Please see Figure 2 Before the gate dielectric layer 14 breaks down, the current of the gate 13 is small because the gate dielectric layer 14 is insulated. When the gate dielectric layer 14 breaks down, the gate 13 and the substrate 10 are connected, and the current increases instantaneously to 0.001A, reaching the standard of the instrument to judge the sample failure. The instrument immediately stops pressurizing the sample.

[0005] Please continue reading. Figure 3During the test, if the connection 19 between the gate 13 and the power supply fails at a certain moment, causing an open circuit, the current will suddenly decrease, indicating that the sample has failed. However, since the current decreases after failure, it will not meet the failure criteria of the testing equipment, and the equipment will continue to apply voltage to the device until the set voltage application time limit is reached, resulting in wasted testing time.

[0006] Therefore, designing a semiconductor test structure that saves test time without increasing test costs or reducing the accuracy of evaluation results is a problem that needs to be solved. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a semiconductor testing structure, testing equipment and semiconductor testing method that saves testing time without increasing semiconductor testing costs or reducing the accuracy of evaluation results.

[0008] To address the aforementioned problems, the present invention provides a semiconductor test structure, comprising: a component under test (DUT), wherein a first test terminal of the DUT is electrically connected to a first pad to receive a first voltage, and a second test terminal is electrically connected to a second pad to receive a second voltage, wherein the second voltage is less than the first voltage; and a switching device, wherein a first control terminal of the switching device is electrically connected to the first pad, and a second control terminal is electrically connected to the first test terminal, and the switching device is turned on in response to the disconnection of the connection line between the first test terminal and the first pad to raise the current at the first pad to a preset threshold current.

[0009] To address the above problems, the present invention provides a testing device, including the semiconductor testing structure described herein.

[0010] To address the aforementioned problems, this invention provides a semiconductor testing method, comprising the following steps: providing a semiconductor testing structure, the semiconductor testing structure including a component under test (DUT) and a switching device, wherein a first test terminal of the DUT is electrically connected to a first pad, and a second test terminal of the DUT is electrically connected to a second pad, and a first control terminal of the switching device is electrically connected to the first pad, and a second control terminal of the switching device is electrically connected to the first test terminal; applying a first voltage to the first pad and applying a second voltage to the second pad, wherein the second voltage is less than the first voltage; when the DUT is broken down, or when the switching device is turned on in response to the disconnection of the connection line between the first test terminal and the first pad, causing the current at the first pad to rise to a preset threshold current, stopping the test and determining that the DUT has failed.

[0011] The above technical solution introduces a switching device into the test structure, which is turned on in response to the disconnection of the connection line between the first test terminal and the first pad, causing the current at the first pad to rise to a preset threshold current. This allows the test equipment to promptly detect the current change, stop the test, and determine that the component under test has failed, thereby saving test time. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 The diagram shows a schematic of a semiconductor device structure for a time-based breakdown test.

[0014] Figure 2 The figure shows the current change trend when a semiconductor device breaks down over time.

[0015] Figure 3 The figure shows another current change trend when a semiconductor device breaks down over time.

[0016] Figure 4 The diagram shown is a schematic representation of an embodiment of the semiconductor testing structure described in this invention.

[0017] Figure 5 The diagram shown is a schematic representation of the current direction in one embodiment of the semiconductor test structure described in this invention.

[0018] Figure 6 The diagram shown is a schematic representation of another current direction in an embodiment of the semiconductor test structure described in this invention.

[0019] Figure 7 The diagram shown is an architectural schematic of an embodiment of the testing equipment described in this invention.

[0020] Figure 8 The diagram shown is a flowchart of one embodiment of the semiconductor testing method of the present invention. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Figure 4The diagram shown is a structural schematic of one embodiment of the semiconductor testing structure described in this invention. Please refer to [link / reference]. Figure 4 The semiconductor test structure includes a component under test (DUT) 41 and a switching device 42. The first test terminal T1 of the DUT 41 is electrically connected to a first pad 43 via a connecting line 49 to receive a first voltage V1, and its second test terminal T2 is electrically connected to a second pad 44 to receive a second voltage V2, wherein the second voltage V2 is less than the first voltage V1. The first control terminal K1 of the switching device 42 is electrically connected to the first pad 43, and its second control terminal K2 is electrically connected to the first test terminal T1. The switching device 42 is turned on in response to the disconnection of the connecting line 49 between the first test terminal T1 and the first pad 43, thereby increasing the current at the first pad 43 to a preset threshold current.

[0023] The above technical solution introduces a switching device 42 into the test structure, which is turned on in response to the disconnection of the connection line 49 between the first test terminal T1 and the first pad 43, so that the current at the first pad 43 rises to a preset threshold current, enabling the test machine to capture the current change in time, stop the test and determine that the component under test 41 has failed, thereby saving test time.

[0024] As one embodiment, the component under test 41 can be a metal-insulating layer-metal capacitor, a metal-oxide-metal capacitor, a metal-dielectric layer capacitor, a metal-oxide-semiconductor capacitor, or a metal-oxide-semiconductor field-effect transistor.

[0025] In one embodiment, the first voltage V1 is a positive voltage, and the second voltage V2 is 0 volts. Specifically, the second pad 44 is grounded. In other embodiments, the second voltage V2 may also be a positive voltage less than the first voltage V1. A voltage difference is formed across the components under test 41 and continuously applied to perform a breakdown test on the components under test 41 over time.

[0026] In one embodiment, the switching device 42 is a field-effect transistor (FET). The gate (G) and drain (D) of the FET are shorted together, serving as the first control terminal K1 of the switching device 42, electrically connected to the first pad 43. The source (S) and substrate (B) of the FET are shorted together, serving as the second control terminal K2 of the switching device 42, electrically connected to the first test terminal T1. In other embodiments, the gate (G) and source (S) of the FET can also be shorted together, serving as the first control terminal K1 of the switching device 42, electrically connected to the first pad 43. The drain (D) and substrate (B) can also be shorted together, serving as the second control terminal K2 of the switching device 42, electrically connected to the first test terminal T1. In one embodiment, the preset threshold current is the saturation current when the FET is turned on. The preset threshold current can be adjusted by regulating the channel length and width of the FET to be applied to the testing of different devices.

[0027] Figure 5 The diagram shown illustrates a current direction according to an embodiment of the semiconductor test structure described in this invention. Please refer to the appendix. Figure 5 Under normal testing conditions, when the first pad 42 receives the first voltage V1, the voltage at the gate G and drain D of the field-effect transistor connected to the first pad 43 is also the first voltage V1; the voltage at the first test terminal T1 is V1, and the voltage at the source S and substrate B of the field-effect transistor connected to the first test terminal T1 is also V1. At this time, no current flows through the field-effect transistor, and the field-effect transistor is in the off state.

[0028] Under normal testing conditions, the first pad 43, the component under test 41, and the second pad 44 form a first path, through which a first current I1 flows, and the first current I1 is less than the preset threshold current.

[0029] When the component under test 41 is broken down, the first current I1 rises to the preset threshold current. At this point, the test is stopped and the component under test 41 is determined to be faulty.

[0030] Figure 6 The diagram shown illustrates another current direction according to an embodiment of the semiconductor test structure described in this invention. Please refer to the appendix. Figure 6When the connection line 49 between the first pad 43 and the first test terminal T1 is disconnected, the voltage at the gate G and drain D of the switching device 42 is the first voltage V1, and the voltage at its source S and substrate B is 0V. A voltage difference is formed across the switching device 42, reaching the turn-on voltage of the switching device 42, thus turning on the switching device 42. At this time, the first pad 43, the switching device 42, the component under test 41, and the second pad 44 constitute a second path, through which a second current I2 flows, and the second current I2 is equal to the preset threshold current.

[0031] As one embodiment, the preset threshold current is the saturation current of the field-effect transistor (FET) when it is turned on, which serves as the switching device 42. The preset threshold current can be adjusted by changing the channel length and width of the FET to be applied to the testing of different devices.

[0032] Based on the same inventive concept, the present invention also provides a testing device.

[0033] Please see Figure 7 This is a schematic diagram of the architecture of an embodiment of the testing device described in this invention. The testing device 100 in this embodiment includes: a semiconductor testing structure 101; wherein, the semiconductor testing structure 101 adopts the present invention. Figures 4-6 The semiconductor test structure shown is detailed in the preceding description and will not be repeated here. The test equipment 100 can be used for time-lapse breakdown testing of semiconductor devices.

[0034] Based on the same inventive concept, the present invention also provides a semiconductor testing method.

[0035] Figure 8 The diagram shows a flowchart of an embodiment of the semiconductor testing method of the present invention, including the following steps: Step S81, providing a semiconductor testing structure, the semiconductor testing structure including a component under test (DUT) and a switching device, the first test terminal of the DUT being electrically connected to a first pad, the second test terminal being electrically connected to a second pad, the first control terminal of the switching device being electrically connected to the first pad, and the second control terminal being electrically connected to the first test terminal; Step S82, applying a first voltage to the first pad and applying a second voltage to the second pad, wherein the second voltage is less than the first voltage; Step S83, when the DUT is broken down, or when the switching device is turned on in response to the disconnection of the connection line between the first test terminal and the first pad, causing the current at the first pad to rise to a preset threshold current, stopping the test and determining that the DUT has failed.

[0036] Please refer to Figure 4In step S81, a semiconductor test structure is provided, the semiconductor test structure includes a component under test 41 and a switching device 42. The first test terminal T1 of the component under test 41 is electrically connected to the first pad 43 through a connecting line 49, and its second test terminal T2 is electrically connected to the second pad 44. The first control terminal K1 of the switching device 42 is electrically connected to the first pad 43, and its second control terminal K2 is electrically connected to the first test terminal T1.

[0037] As one embodiment, the component under test 41 can be a metal-insulating layer-metal capacitor, a metal-oxide-metal capacitor, a metal-dielectric layer capacitor, a metal-oxide-semiconductor capacitor, or a metal-oxide-semiconductor field-effect transistor.

[0038] In one embodiment, the switching device 42 is a field-effect transistor (FET). The gate (G) and drain (D) of the FET are shorted together, serving as the first control terminal K1 of the switching device 42, electrically connected to the first pad 43. The source (S) and substrate (B) of the FET are shorted together, serving as the second control terminal K2 of the switching device 42, electrically connected to the first test terminal T1. In other embodiments, the gate (G) and source (S) of the FET can also be shorted together, serving as the first control terminal K1 of the switching device 42, electrically connected to the first pad 43. The drain (D) and substrate (B) can also be shorted together, serving as the second control terminal K2 of the switching device 42, electrically connected to the first test terminal T1. In one embodiment, the preset threshold current is the saturation current when the FET is turned on. The preset threshold current can be adjusted by regulating the channel length and width of the FET to be applied to the testing of different devices.

[0039] Please continue to refer to this. Figure 5 And in step S82, a first voltage V1 is applied to the first pad 43 and a second voltage V2 is applied to the second pad 44, wherein the second voltage V2 is less than the first voltage V1.

[0040] like Figure 5 As shown, in one embodiment, the first voltage V1 is a positive voltage, and the second voltage V2 is 0 volts. In other embodiments, the second voltage V2 may also be a positive voltage less than the first voltage V1. Specifically, the second pad 44 is grounded. A voltage difference is formed across the components under test 41 and continuously applied to perform a breakdown test on the components under test 41 over time.

[0041] Under normal testing conditions, when the first pad 43 receives the first voltage V1, the voltage at the gate G and drain D of the field-effect transistor connected to the first pad 43 is also the first voltage V1; the voltage at the first test terminal T1 is V1, and the voltage at the source S and substrate B of the field-effect transistor connected to the first test terminal T1 is also V1. At this time, no current flows through the field-effect transistor, and the field-effect transistor is in the off state. The first pad 43, the component under test 41, and the second pad 44 constitute a first path, through which a first current I1 flows, and the first current I1 is less than the preset threshold current.

[0042] Please refer to Figures 5-6 And in step S83, when the component under test 41 is broken down, or when the switching device 42 is turned on in response to the disconnection of the connection line 49 between the first test terminal T1 and the first pad 43, causing the current at the first pad 43 to rise to a preset threshold current, the test is stopped and the component under test 41 is determined to be faulty.

[0043] like Figure 5 As shown, when the component under test 41 is broken down, the first current I1 rises to the preset threshold current. At this time, the test is stopped and the component under test 41 is determined to be faulty.

[0044] like Figure 6 As shown, when the connection line 49 between the first pad 43 and the first test terminal T1 is disconnected, the voltage at the gate G and drain D of the switching device 42 is the first voltage V1, and the voltage at its source S and substrate B is 0 volts. A voltage difference is formed across the two ends of the switching device 42, reaching the turn-on voltage of the switching device 42, thus turning on the switching device 42. At this time, the first pad 43, the switching device 42, the component under test 41, and the second pad 44 constitute a second path, through which a second current I2 flows, and the second current I2 is equal to the preset threshold current.

[0045] The above technical solution introduces a switching device 42 into the test structure. This device is activated in response to the disconnection of the connection line 49 between the first test terminal T1 and the first pad 43, causing the current at the first pad 43 to rise to a preset threshold current. This allows the test equipment to promptly detect the current change, stop the test, and determine that the component under test 41 has failed, thus saving test time. Furthermore, the preset threshold current can be adjusted by changing the channel length and width of the field-effect transistor used as the switching device 42 to apply it to the testing of different devices.

[0046] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0047] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0048] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0049] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor testing structure, characterized in that, include: The component under test (DUT) has a first test terminal electrically connected to a first pad to receive a first voltage, and a second test terminal electrically connected to a second pad to receive a second voltage, wherein the second voltage is less than the first voltage. as well as A switching device, wherein the switching device is a field-effect transistor, is electrically connected to the first pad as the first control terminal of the switching device after the gate and drain are shorted, and is electrically connected to the first test terminal as the second control terminal of the switching device after the source and substrate are shorted. Under normal test conditions, the field-effect transistor is in the off state. The field-effect transistor is turned on in response to the disconnection of the connection line between the first test terminal and the first pad, so as to raise the current at the first pad to a preset threshold current. The preset threshold current is the saturation current when the field-effect transistor is turned on.

2. The structure according to claim 1, characterized in that, The component under test is any one of a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, a metal-dielectric capacitor, a metal-oxide-semiconductor capacitor, or a metal-oxide-semiconductor field-effect transistor.

3. The structure according to claim 1, characterized in that, The second voltage is 0 volts.

4. The structure according to claim 1, characterized in that, The preset threshold current is adjusted by regulating the channel length and width of the field-effect transistor.

5. The structure according to claim 1, characterized in that, Under normal testing conditions, the first pad, the component under test, and the second pad constitute a first path, through which a first current flows, and the first current is less than the preset threshold current.

6. The structure according to claim 5, characterized in that, When the component under test is broken down, the first current rises to the preset threshold current.

7. The structure according to claim 1, characterized in that, When the connection line between the first pad and the first test terminal is disconnected, the first pad, the switching device, the component under test, and the second pad form a second path, in which a second current flows, and the second current is equal to the preset threshold current.

8. A testing device, characterized in that, Includes the semiconductor test structure as described in any one of claims 1 to 7.

9. A semiconductor testing method, characterized in that, Includes the following steps: A semiconductor test structure is provided, the semiconductor test structure includes a component under test (DUT) and a switching device. The first test terminal of the DUT is electrically connected to a first pad, and its second test terminal is electrically connected to a second pad. The switching device is a field-effect transistor (FET). The gate and drain are shorted together to serve as the first control terminal of the switching device, which is electrically connected to the first pad. The source and substrate are shorted together to serve as the second control terminal of the switching device, which is electrically connected to the first test terminal. Under normal test conditions, the FET is in the off state. A first voltage is applied to the first pad, and a second voltage is applied to the second pad, wherein the second voltage is less than the first voltage; When the component under test is broken down, or when the field-effect transistor turns on in response to the disconnection of the connection line between the first test terminal and the first pad, causing the current at the first pad to rise to a preset threshold current, the test is stopped and the component under test is determined to be faulty. The preset threshold current is the saturation current when the field-effect transistor is turned on.

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