Memory management method, memory storage device and memory control circuit unit

Abstract

The present application provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises: in a first operation mode, setting an entity management unit to span N entity regions in a rewritable non-volatile memory module; in a second operation mode, setting the entity management unit to span M entity regions in the rewritable non-volatile memory module, wherein N is greater than M; and accessing the rewritable non-volatile memory module based on the entity management unit. In this way, the management flexibility and performance of the rewritable non-volatile memory module can be improved.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory management method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of mobile phones, tablets, and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] As the capacity of rewritable non-volatile memory modules gradually increases, the physical management unit inside these modules has also expanded from a single physical block to a virtual block containing multiple physical blocks. However, fixed-size virtual blocks, besides lacking management flexibility, also fail to ensure that rewritable non-volatile memory modules provide optimal performance under different operating scenarios. Summary of the Invention

[0004] This invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can improve the management flexibility and performance of rewritable non-volatile memory modules.

[0005] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical regions. The memory management method includes: in a first operating mode, setting the physical management unit to span N physical regions among the multiple physical regions; in a second operating mode, setting the physical management unit to span M physical regions among the multiple physical regions, where N is greater than M; and accessing the rewritable non-volatile memory module based on the physical management unit.

[0006] In an exemplary embodiment of the present invention, the memory management method further includes: detecting a target event; and in response to the target event, switching the operating mode of the rewritable non-volatile memory module from the first operating mode to the second operating mode.

[0007] In an exemplary embodiment of the present invention, the memory management method further includes: in response to the completion of the target event, reverting the operating mode from the second operating mode to the first operating mode.

[0008] In one exemplary embodiment of the present invention, the target event includes one of a power outage event, a power-on event, and a table write event.

[0009] In an exemplary embodiment of the present invention, the target event further reflects that the total number of idle entity units in the rewritable non-volatile memory module is less than a critical value, and that the idle entity units do not store valid data.

[0010] In an exemplary embodiment of the present invention, the step of accessing the rewritable non-volatile memory module based on the entity management unit includes: in the first operating mode, continuously writing first data into the N entity regions; and in the second operating mode, continuously writing second data into the M entity regions.

[0011] In an exemplary embodiment of the present invention, the memory management method further includes: initiating a data merging operation. The data merging operation includes: collecting valid data from the N physical regions operating in the first operating mode; and storing the valid data into the M physical regions based on the second operating mode.

[0012] In one exemplary embodiment of the present invention, the plurality of physical regions correspond to a plurality of dies, a plurality of chip enable regions, or a plurality of planes in the rewritable nonvolatile memory module.

[0013] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes multiple physical regions. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: in a first operating mode, set the physical management unit to span N physical regions among the multiple physical regions; in a second operating mode, set the physical management unit to span M physical regions among the multiple physical regions, where N is greater than M; and access the rewritable non-volatile memory module based on the physical management unit.

[0014] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: detect a target event; and, in response to the target event, switch the operating mode of the rewritable non-volatile memory module from the first operating mode to the second operating mode.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: in response to the completion of the target event, revert the operation mode from the second operation mode to the first operation mode.

[0016] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to access the rewritable non-volatile memory module based on the entity management unit includes: in a first operating mode, instructing to continuously write first data into the N entity regions; and in a second operating mode, instructing to continuously write second data into the M entity regions.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: initiate a data merging operation. The data merging operation includes: instructing the collection of valid data from the N physical regions operating in the first operating mode; and instructing the storage of the valid data into the M physical regions based on the second operating mode.

[0018] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical regions. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: in a first operating mode, set the physical management unit to span N physical regions among the multiple physical regions; in a second operating mode, set the physical management unit to span M physical regions among the multiple physical regions, where N is greater than M; and access the rewritable non-volatile memory module based on the physical management unit.

[0019] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: detect a target event; and, in response to the target event, switch the operating mode of the rewritable non-volatile memory module from the first operating mode to the second operating mode.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: in response to the completion of the target event, revert the operating mode from the second operating mode to the first operating mode.

[0021] In an exemplary embodiment of the present invention, the operation of the memory management circuit to access the rewritable non-volatile memory module based on the physical management unit includes: in a first operating mode, instructing to continuously write first data into the N physical regions; and in a second operating mode, instructing to continuously write second data into the M physical regions.

[0022] In an exemplary embodiment of the present invention, the memory management circuitry is further configured to: initiate a data merging operation. The data merging operation includes: instructing the collection of valid data from the N physical regions operating in the first operating mode; and instructing the storage of the valid data into the M physical regions based on the second operating mode.

[0023] Based on the above, in different operating modes, the entity management unit can be configured to span different numbers of entity regions within the rewritable non-volatile memory module. By using the flexibly configured entity management unit to access the rewritable non-volatile memory module, the management flexibility and performance of the rewritable non-volatile memory module can be improved. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the system architecture of a memory storage device according to an exemplary embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of the entity management unit used in different operating modes as shown in exemplary embodiments of the present invention;

[0032] Figure 9 This is a schematic diagram illustrating data storage based on a first operation mode according to an exemplary embodiment of the present invention;

[0033] Figure 10This is a schematic diagram illustrating the execution of a data merging operation based on a second operating mode, according to an exemplary embodiment of the present invention;

[0034] Figure 11 This is a schematic diagram illustrating data storage based on a second operation mode and data type, according to an exemplary embodiment of the present invention;

[0035] Figure 12 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Detailed Implementation

[0036] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0037] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0038] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0039] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0040] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0041] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 can be connected to the memory storage device 10 via wired or wireless means.

[0042] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0043] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0044] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0045] Please refer to Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0046] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0047] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0048] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0049] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0050] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0051] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0052] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0053] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a page or a sector. If the physical programming unit is a page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 sectors, and the size of one sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer sectors, and the size of each sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a block.

[0054] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0055] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to a description of the operation of the memory control circuit unit 42.

[0056] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0057] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0058] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0059] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0060] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0061] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0062] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0063] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0064] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 6 The memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. In one exemplary embodiment, a physical unit refers to a physical programmable unit. However, in another exemplary embodiment, a physical unit may also contain multiple physical programmable units.

[0067] Entity cells 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and / or invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0068] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses. A, B, and C are all positive integers and can be adjusted according to practical needs; this invention does not impose any limitations.

[0069] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0070] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0071] Figure 7 This is a schematic diagram of the system architecture of a memory storage device according to an exemplary embodiment of the present invention.

[0072] Please refer to Figure 7 The rewritable non-volatile memory module 43 may include multiple chip-enabled (CE) regions CE(0) to CE(E). For example, the rewritable non-volatile memory module 43 may include one or more dies. Dies are obtained from wafers by laser cutting. Each die can be divided into one or more chip-enabled regions. Each chip-enabled region among the chip-enabled regions CE(0) to CE(E) may include one or more planes (also called memory planes, in...) Figure 7 The planes are labeled as planes (0) to (P). Each plane can contain multiple solid elements.

[0073] It should be noted that whether a certain chip enable region can be accessed can be controlled by the chip enable signal corresponding to that chip enable region. For example, when the chip enable signal corresponding to the chip enable region CE(i) is pulled up, the rewritable non-volatile memory module 43 can read data from or store data in the chip enable region CE(i). However, if the chip enable signal corresponding to the chip enable region CE(i) is not pulled up, the rewritable non-volatile memory module 43 cannot read data from or store data in the chip enable region CE(i).

[0074] It should be noted that in this exemplary embodiment, each of the chip enable regions CE(0) to CE(E) contains the same number of planes as an example. For instance, chip enable region CE(0) contains planes 701(0) to 701(P), and chip enable region CE(E) contains planes 702(0) to 702(P), and so on. However, the total number of planes (i.e., P) in different chip enable regions may also be different, and this invention does not impose any limitations on this.

[0075] The memory management circuit 51 can access the rewritable non-volatile memory module 43 through channels (also referred to as memory channels) 71(0) to 71(D). In particular, each of channels 71(0) to 71(D) can be used to access a specific chip enable region. For example, channel 71(i) can be used to access chip enable region (i). Furthermore, the values ​​of D, E, and P can be adjusted according to practical needs, and the present invention is not limited thereto.

[0076] The memory management circuit 51 can use a physical management unit to manage the physical cells within the rewritable non-volatile memory module 43. Specifically, a physical management unit can include (also referred to as spanning) multiple physical regions within the rewritable non-volatile memory module 43. Each physical region can correspond to a die, a chip enable region, or a plane, and multiple physical regions can correspond to multiple dies, multiple chip enable regions, or multiple planes. In other words, a physical management unit can span multiple dies, multiple chip enable regions, or multiple planes within the rewritable non-volatile memory module 43.

[0077] When data needs to be written to a physical management unit, the memory management circuit 51 can issue a sequence of write instructions for at least a portion of the physical regions within that physical management unit. These write instruction sequences can instruct the rewritable non-volatile memory module 43 to continuously write data to at least a portion of the physical cells within those physical regions. When data needs to be read from a physical management unit, the memory management circuit 51 can issue a sequence of read instructions for at least a portion of the physical regions within that physical management unit. These read instruction sequences can instruct the rewritable non-volatile memory module 43 to read data from at least a portion of the physical cells within those physical regions. Furthermore, when data needs to be erased from a physical management unit, the memory management circuit 51 can issue a sequence of erase instructions for at least a portion of the physical regions within that physical management unit. These erase instruction sequences can instruct the rewritable non-volatile memory module 43 to perform erase operations on at least a portion of the physical cells within those physical regions to clear the data in those physical cells.

[0078] The rewritable non-volatile memory module 43 supports different operating modes (also known as access modes). In different operating modes, the memory management circuit 51 can set the total number of physical regions contained in (or spanned by) a single physical management unit to different values. For example, in one operating mode (also known as the first operating mode), the memory management circuit 51 can set the physical management unit to span N physical regions. In another operating mode (also known as the second operating mode), the memory management circuit 51 can set the physical management unit to span M physical regions. The first operating mode differs from the second operating mode, and N is greater than M. Thus, in different operating modes, the memory management circuit 51 can access the rewritable non-volatile memory module 43 based on physical management units of different sizes.

[0079] For example, in the first operating mode, the memory management circuit 51 can access multiple physical cells in the N physical regions of the rewritable non-volatile memory module 43 through a physical management unit spanning N physical regions. In the second operating mode, the memory management circuit 51 can access multiple physical cells in the M physical regions of the rewritable non-volatile memory module 43 through a physical management unit spanning M physical regions. Alternatively, from another perspective, in different operating modes (i.e., the first operating mode and the second operating mode), the same physical region in the chip enable regions CE(0) to CE(E) can be accessed through a physical management unit spanning N physical regions or a physical management unit spanning M physical regions.

[0080] Figure 8 This is a schematic diagram of the entity management unit used in different operating modes as shown in the exemplary embodiments of the present invention.

[0081] Please refer to Figure 8 In the first operating mode, the memory management circuit 51 can use the physical management unit 81 to access the rewritable non-volatile memory module 43. The physical management unit 81 includes (or spans) physical regions 811(0) to 811(N-1). The total number of physical regions 811(0) to 811(N-1) is N. In other words, in the first operating mode, the physical management unit 81 can span N dies, N chip enable regions, or N planes inside the rewritable non-volatile memory module 43. Therefore, in the first operating mode, the memory management circuit 51 can continuously write data (also referred to as first data) into the N physical regions 811(0) to 811(N-1) included in the physical management unit 81.

[0082] On the other hand, in the second operating mode, the memory management circuit 51 can use the physical management unit 82 to access the rewritable non-volatile memory module 43. The physical management unit 82 includes (or spans) physical regions 821(0) to 821(M-1). The total number of physical regions 821(0) to 821(M-1) is M. In other words, in the second operating mode, the physical management unit 82 can span M dies, M chip enable regions, or M planes inside the rewritable non-volatile memory module 43, and N is greater than M. Therefore, in the second operating mode, the memory management circuit 51 can continuously write data (also referred to as second data) into the M physical regions 821(0) to 821(M-1) included in the physical management unit 82.

[0083] It should be noted that, Figure 8 The physical regions 811(0) to 811(N-1) and 821(0) to 821(M-1) in the rewritable non-volatile memory module 43 can be completely different or at least partially identical physical regions. For example, assume that physical regions 811(0) and 821(0) are the same physical region in the rewritable non-volatile memory module 43. In the first operating mode, this physical region can be accessed through the physical management unit 81, while in the second operating mode, this physical region can be accessed through the physical management unit 82.

[0084] In one exemplary embodiment, the total number of entity regions included (or spanned) by the entity management unit can be changed accordingly in response to a change in operating mode. For example, if the operating mode is switched from a first operating mode to a second operating mode, the memory management circuit 51 can change the entity management unit used from entity management unit 81 to entity management unit 82. Alternatively, if the operating mode is switched back from the second operating mode to the first operating mode, the memory management circuit 51 can change the entity management unit used from entity management unit 82 back to entity management unit 81.

[0085] In one exemplary embodiment, it is assumed that the rewritable non-volatile memory module 43 is preset to a first operating mode. In the first operating mode, the memory management circuit 51 can detect a specific event (also referred to as a target event). Upon detecting the target event, in response to the target event, the memory management circuit 51 can switch the operating mode of the rewritable non-volatile memory module 43 from the first operating mode to a second operating mode. Then, the memory management circuit 51 can, based on the entity management unit corresponding to the second operating mode (e.g., ...), ... Figure 8The memory management circuit 51 accesses the rewritable non-volatile memory module 43 via the entity management unit 82. Furthermore, upon completion of a target event, in response to the completion of the target event, the memory management circuit 51 can revert the operating mode from the second operating mode to the first operating mode. Then, the memory management circuit 51 can access the rewritable non-volatile memory module 43 based on the entity management unit (e.g., the entity management unit 82) corresponding to the first operating mode. Figure 8 The entity management unit 81 accesses the rewritable non-volatile memory module 43. In an exemplary embodiment, the event processing performance of the memory management circuit 51 for a target event can be improved by changing the operating mode of the rewritable non-volatile memory module 43 and / or the total number of entity regions spanned by the entity management unit.

[0086] In one exemplary embodiment, the target event includes one of a power-off event, a power-on event, and a table write event. A power-off event includes a normal or unexpected power outage of the memory storage device 10. A power-on event includes powering on the memory storage device 10. A table write event includes writing (i.e., storing) table data into the rewritable non-volatile memory module 43. For example, the table data includes a logical-to-entity mapping table or other management tables. Furthermore, the types of target events can be increased or decreased according to practical needs, and the present invention is not limited thereto.

[0087] In particular, after a target event is detected, the event processing performance of the memory management circuit 51 for the target event can be improved by reducing the total number of entity regions spanned by the entity management unit. For example, after a power outage and / or power-on event, the memory management circuit 51 often automatically performs data cleanup in the background. At this time, by reducing the total number of entity regions spanned by the entity management unit, data in the rewritable non-volatile memory module 43 can be read, written, copied, and / or moved more quickly, thereby improving the event processing performance of the memory management circuit 51 for power outage and / or power-on events. Furthermore, the amount of table data to be updated in a table write event is often small. Therefore, by reducing the total number of entity regions spanned by the entity management unit, the data update performance performed by the memory management circuit 51 for table data write events can also be improved.

[0088] In one exemplary embodiment, the target event may also reflect that the total number of idle physical units in the rewritable non-volatile memory module 43 is less than a threshold. Idle physical units do not store valid data. For example, an idle physical unit refers to... Figure 6The idle areas 602 contain physical units 610(A+1) to 610(B). In one exemplary embodiment, a data merging operation can be triggered (i.e., initiated) in response to the total number of idle physical units falling below a threshold. For example, the data merging operation may include a garbage collection operation. Therefore, upon detecting a target event, the memory management circuitry 51 may perform the data merging operation based on a second operating mode.

[0089] Figure 9 This is a schematic diagram illustrating data storage based on a first operating mode according to an exemplary embodiment of the present invention.

[0090] Please refer to Figure 9 In general, the memory management circuit 51 can receive data (also referred to as first data) 901 from the host system 11. For example, data 901 may be included in one or more write instructions. Based on data 901 (or write instructions), the memory management circuit 51 can send at least one sequence of write instructions to the rewritable non-volatile memory module 43 to instruct the rewritable non-volatile memory module 43 to store data 901 based on a first operating mode. For example, based on this sequence of write instructions, the rewritable non-volatile memory module 43 can write data 901 sequentially into physical regions 911(0) to 911(N-1) in the physical management unit 91. For example, multiple data segments of data 901 may be written sequentially or in parallel into multiple physical cells in physical regions 911(0) to 911(N-1).

[0091] Figure 10 This is a schematic diagram illustrating the data merging operation performed based on a second operating mode, according to an exemplary embodiment of the present invention.

[0092] Please refer to Figure 10Assume that the entity management unit 1010, which is the source unit of valid data, originally stores data based on a first operating mode. For example, the entity management unit 1010 operating in the first operating mode includes entity regions 1011(0) to 1011(N-1). After initiating the data consolidation operation, the memory management circuit 51 can send a read instruction sequence to the rewritable non-volatile memory module 43 to instruct the rewritable non-volatile memory module 43 to collect data 1001 from entity regions 1011(0) to 1011(N-1) in the entity management unit 1010. For example, data 1001 contains valid data. Then, the memory management circuit 51 can send at least one write instruction sequence to the rewritable non-volatile memory module 43 to instruct the rewritable non-volatile memory module 43 to store the collected valid data into entity management units 1020(0) to 1020(K), which are the target units, based on a second operating mode. For example, the memory management circuit 51 can store the collected data 1001 (i.e., valid data) in the entity regions 1021(0) to 1021(M-1) of the entity management unit 1020(0) and the entity regions 1022(0) to 1022(M-1) of the entity management unit 1020(K) based on the second operating mode.

[0093] It should be noted that the total number of entity regions (i.e., M) included (or spanned) by the single entity management unit 1020(i) as the target unit is different from (e.g., less than) the total number of entity regions (i.e., N) included (or spanned) by the single entity management unit 1011(j) as the source unit. In an exemplary embodiment, by reducing the total number of entity regions included (or spanned) by a single entity management unit, the execution efficiency of the data merging operation can be improved (e.g., improving the storage efficiency of valid data). Furthermore, if the data merging operation is initiated in conjunction with a power-off event or a power-on event, the improved execution efficiency of the data merging operation also contributes to improved system stability.

[0094] In one exemplary embodiment, Figure 10 The data read and write directions can also be opposite. For example, in one exemplary embodiment, after storing data to certain physical regions based on a second operating mode, the memory management circuit 51 can read this data from these physical regions and then store it in other physical regions based on a first operating mode.

[0095] In one exemplary embodiment, the memory management circuit 51 can determine, based on the type of data to be stored, which specific entity management unit among the multiple entity management units to store the data according to the second operating mode. This further reduces the write amplification factor (WAF) on the rewritable non-volatile memory module 43 caused by each small data write operation.

[0096] Figure 11 This is a schematic diagram illustrating data storage based on a second operation mode and data type, as shown in an exemplary embodiment of the present invention.

[0097] Please refer to Figure 11 Assume the data to be stored includes a first type of data 1101 and a second type of data 1102. In the second operating mode, the memory management circuit 51 can send a write instruction sequence to the rewritable non-volatile memory module 43 to instruct the first type of data 1101 and the second type of data 1102 to be stored in the physical management units 1120(0) and 1120(F), respectively. For example, the first type of data 1101 can be continuously stored in the physical regions 1121(0) to 1121(M-1) of the physical management unit 1120(0) based on the second operating mode, and the second type of data 1102 can be continuously stored in the physical regions 1122(0) to 1122(M-1) of the physical management unit 1120(F) based on the second operating mode. In one exemplary embodiment, compared to using a preset entity management unit, by reducing the total number of entity regions included (or spanned) by the entity management unit, the write amplification factor can still be effectively suppressed even when data content is frequently updated for specific types of data. Furthermore, by reducing the total number of entity regions included (or spanned) by the entity management unit, the data write efficiency for small data can also be effectively improved.

[0098] In one exemplary embodiment, the different types of data written based on the second operating mode may include different types of tabular data. For example, Figure 11 The first type of data 1101 may include a logic-to-entity mapping table corresponding to a certain logical range, while the second type of data 1102 may include a logic-to-entity mapping table corresponding to another logical range, etc., and the present invention does not limit how the data to be stored is classified.

[0099] It should be noted that, in Figure 11In one exemplary embodiment, for entity management unit 1110, which is pre-operated in a first operating mode, after storing first type data 1101 and second type data 1102 based on a second operating mode, entity management unit 1120(N), which is pre-included in entity management unit 1110, may remain idle. Entity management unit 1120(N) includes entity regions 1123(0) to 1123(M-1). In particular, entity management unit 1120(N) being idle means that entity management unit 1120(N) has not been written to while at least entity management units 1120(0) and 1120(F) have stored data. Subsequently, other types of data may also be stored in entity management unit 1120(N) based on the second operating mode.

[0100] From another perspective, in Figure 11 In one exemplary embodiment, a single entity management unit 1110 operating in a first operating mode is pre-defined as being split into multiple entity management units 1120(0) to 1120(N) operating in a second operating mode, and the total number of entity management units 1120(0) to 1120(N) can be more or less. For different types of data, in each data write operation, only a portion of the entity management units 1120(0) to 1120(N) will be written to. Compared to using the complete entity management unit 1110 to perform data writing, using the split entity management units 1120(0) to 1120(N) to perform data writing separately can improve data writing efficiency and / or effectively suppress the write amplification factor.

[0101] Figure 12 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention.

[0102] Please refer to Figure 12 In step S1201, the operating mode of the rewritable non-volatile memory module is determined. If the determined operating mode is the first operating mode, in step S1202, the entity management unit is set to span N entity regions. Alternatively, if the determined operating mode is the second operating mode, in step S1203, the entity management unit is set to span M entity regions, where N is greater than M. In step S1204, the rewritable non-volatile memory module is accessed based on the set entity management unit.

[0103] However, Figure 12 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 12 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 12The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0104] In summary, the memory management method, memory storage device, and memory control circuit unit proposed in the exemplary embodiments of the present invention can dynamically determine the size of the physical management unit (i.e., the total number of physical regions spanned by the physical management unit) according to different operating scenarios. The determined physical management unit can be used to access the rewritable non-volatile memory module. By using the flexibly configured physical management unit to access the rewritable non-volatile memory module, the management flexibility and performance of the rewritable non-volatile memory module can be improved.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a rewritable non-volatile memory module, the memory management method includes: In the first operating mode, the entity management unit is configured to span a first number of dies, chip enable regions, or planes in the rewritable non-volatile memory module. In the second operating mode, the entity management unit is configured to span a second number of the dies, the chip enable regions, or the planes in the rewritable non-volatile memory module, and the first number is greater than the second number; and The rewritable non-volatile memory module is accessed based on the entity management unit.

2. The memory management method according to claim 1 further includes: Detect target events; as well as In response to the target event, the operating mode of the rewritable non-volatile memory module is switched from the first operating mode to the second operating mode.

3. The memory management method according to claim 2 further includes: In response to the completion of the target event, the operation mode is restored from the second operation mode to the first operation mode.

4. The memory management method according to claim 2, wherein the target event includes one of a power-off event, a power-on event, and a table write event.

5. The memory management method according to claim 4, wherein the target event further reflects that the total number of idle entity units in the rewritable non-volatile memory module is less than a threshold value, and the idle entity units do not store valid data, wherein the idle entity unit includes at least one entity page in the rewritable non-volatile memory module that does not store the valid data.

6. The memory management method according to claim 1, wherein the step of accessing the rewritable non-volatile memory module based on the physical management unit includes: In the first operating mode, the first data is continuously written into the first number of physical regions in the rewritable non-volatile memory module; as well as In the second operating mode, the second data is continuously written into the second number of physical regions in the rewritable non-volatile memory module, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

7. The memory management method according to claim 1, further comprising: Initiate the data merging operation. The data merging operation mentioned above includes: Collect valid data from the first number of physical regions in the rewritable non-volatile memory module operating in the first operating mode; and Based on the second operating mode, the valid data is stored in the second number of physical regions in the rewritable non-volatile memory module, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

8. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; Rewritable non-volatile memory module; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: In the first operating mode, the entity management unit is configured to span a first number of dies, chip enable regions, or planes in the rewritable non-volatile memory module. In the second operating mode, the entity management unit is configured to span a second number of the dies, the chip enable regions, or the planes in the rewritable non-volatile memory module, and the first number is greater than the second number; and The rewritable non-volatile memory module is accessed based on the entity management unit.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Detect target events; and In response to the target event, the operating mode of the rewritable non-volatile memory module is switched from the first operating mode to the second operating mode.

10. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: In response to the completion of the target event, the operation mode is restored from the second operation mode to the first operation mode.

11. The memory storage device of claim 9, wherein the target event includes one of a power-off event, a power-on event, and a table write event.

12. The memory storage device of claim 11, wherein the target event further reflects that the total number of idle entity units in the rewritable non-volatile memory module is less than a threshold value, and the idle entity units do not store valid data, wherein the idle entity unit comprises at least one entity page in the rewritable non-volatile memory module that does not store the valid data.

13. The memory storage device of claim 8, wherein the operation of the memory control circuit unit accessing the rewritable non-volatile memory module based on the physical management unit includes: In the first operating mode, it is indicated that first data is continuously written into the first number of physical regions in the rewritable non-volatile memory module; as well as In the second operating mode, it is indicated that second data is continuously written into the second number of physical regions in the rewritable non-volatile memory module, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

14. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Initiate the data merging operation. The data merging operation mentioned above includes: Instruction to collect valid data from the first number of physical regions in the rewritable non-volatile memory module operating in the first operating mode; as well as The instruction is to store the valid data into the second number of physical regions in the rewritable non-volatile memory module based on the second operating mode, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

15. A memory control circuit unit, characterized in that, The memory control circuit unit is used to control a rewritable non-volatile memory module, and includes: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: In the first operating mode, the entity management unit is configured to span a first number of dies, chip enable regions, or planes in the rewritable non-volatile memory module. In the second operating mode, the entity management unit is configured to span a second number of the dies, the chip enable regions, or the planes in the rewritable non-volatile memory module, and the first number is greater than the second number; and The rewritable non-volatile memory module is accessed based on the entity management unit.

16. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Detect target events; and In response to the target event, the operating mode of the rewritable non-volatile memory module is switched from the first operating mode to the second operating mode.

17. The memory control circuit unit according to claim 16, wherein the memory management circuit is further configured to: In response to the completion of the target event, the operation mode is restored from the second operation mode to the first operation mode.

18. The memory control circuit unit of claim 16, wherein the target event includes one of a power-off event, a power-on event, and a table write event.

19. The memory control circuit unit of claim 18, wherein the target event further reflects that the total number of idle entity units in the rewritable non-volatile memory module is less than a threshold value, and the idle entity units do not store valid data, wherein the idle entity units comprise at least one entity page in the rewritable non-volatile memory module that does not store the valid data.

20. The memory control circuit unit of claim 15, wherein the operation of the memory management circuit to access the rewritable non-volatile memory module based on the physical management unit includes: In the first operating mode, it is indicated that first data is continuously written into the first number of physical regions in the rewritable non-volatile memory module; as well as In the second operating mode, it is indicated that second data is continuously written into the second number of physical regions in the rewritable non-volatile memory module, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

21. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Initiate the data merging operation. The data merging operation mentioned above includes: Instruction to collect valid data from the first number of physical regions in the rewritable non-volatile memory module operating in the first operating mode; as well as The instruction is to store the valid data into the second number of physical regions in the rewritable non-volatile memory module based on the second operating mode, and each physical region corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

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