Method, device and medium for estimating wire net delay of programmable logic device
By dividing the FPGA into regions and calculating the net path delay, the problem of inaccurate net delay estimation in the prior art is solved, achieving more accurate placement and routing timing consistency and improving the efficiency of FPGA design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PANGO MICROSYST CO LTD
- Filing Date
- 2022-12-02
- Publication Date
- 2026-07-31
AI Technical Summary
Existing net delay estimation methods are not accurate enough in FPGA calculations, which affects the timing optimization of the placement process.
The programmable logic device is divided into several regions, the programmable interconnects and layout resources in each region are obtained, the network path delay is calculated, the network path is adapted according to timing requirements, and the results are stored to provide a reference for the routing stage.
It improves the accuracy of network delay estimation, ensures consistency in layout and wiring timing, reduces wiring process time, and lowers errors.
Smart Images
Figure CN115859883B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuit technology and relates to a method, apparatus, device and medium for estimating the net delay of a programmable logic device. Background Technology
[0002] Placement and routing are key processes in the design of programmable logic devices using design software. FPGA (Field Programmable Gate Array) is one of the main types of commonly used programmable logic devices. Taking FPGA as an example, the purpose of placement is to place the design cells in the FPGA design netlist onto the programmable logic modules of the FPGA. The purpose of routing is to configure the design nets in the design netlist through the programmable interconnects in the FPGA after placement. The design nets are used to connect the design cells.
[0003] To improve FPGA design performance, the FPGA placement and routing processes require timing drivers to be calculated. The quality of the timing drivers is determined by the delay of the design nets. Since the placement process does not have routing information for programmable interconnects, delay estimation is performed. Therefore, the accuracy of the placement process delay estimation is the most important factor affecting FPGA performance.
[0004] The traditional delay estimation method is to run a large number of test cases, fit a distance-delay estimation formula based on the actual delay and distance of the net when using the test cases, and use the fitted estimation formula to calculate the delay in the layout and routing processes.
[0005] However, while calculating net delay based on the fitted estimation formula is simple to implement, in FPGA devices, because the delay and distance of programmable interconnects have a discrete relationship, it is difficult to generate an accurate mathematical model of the delay-distance relationship, especially when the programmable interconnect traces are long. In this case, the net is composed of many cascaded programmable interconnects. In the actual routing process, the net is a combination of different types of programmable interconnects, and the resources of each type of programmable interconnect are limited. Therefore, the actual net delay has a large degree of randomness. This also makes it impossible to fit a relatively accurate length-delay estimation formula in the placement process. That is, the structure calculated by the traditional delay estimation method still has a large error, which has an adverse impact on the timing optimization of the placement process. Summary of the Invention
[0006] The purpose of this application is to provide a method, apparatus, device and medium for estimating the net delay of a programmable logic device, so as to solve the technical problem that the delay calculated by the existing net delay estimation method is not accurate enough.
[0007] To solve the above-mentioned technical problems, the technical solution of this application is as follows:
[0008] This application provides a method for estimating the net delay of a programmable logic device, including:
[0009] The programmable logic device is divided into several regions, and the programmable interconnects and layout resources already laid out in the regions are obtained.
[0010] The network path composed of the programmable interconnects in the region is determined based on the location of the layout resources in the region, and the delay of each network path is calculated. The network path is used to provide wiring resources for any two layout resources that have a connection relationship in the region.
[0011] The network path is adapted between the layout resources according to the network timing requirements between the layout resources that have a connection relationship within the region, and the delay of the network path is used as the network delay between the layout resources.
[0012] Further, the step of calculating the delay of each of the net paths includes:
[0013] Obtain the type of each programmable interconnect in the net path, and determine the delay of the programmable interconnect of different types;
[0014] The delay of each of the programmable interconnects is summed to determine the delay of the net path.
[0015] Further, the step of adapting the net path among the layout resources according to the net timing requirements between the layout resources with connectivity within the region includes:
[0016] The net timing margin between the layout resources is determined based on the difference between the net timing requirements between the layout resources and the net setting delay between the layout resources;
[0017] The net path with the least latency is adapted to the layout resources with the least net timing margin, until all the layout resources in the region are adapted to the net path.
[0018] Furthermore, the method for estimating the net delay of the programmable logic device further includes:
[0019] When the location of the resources within the region changes, the net delay estimation method for the programmable logic device described above is re-executed.
[0020] Furthermore, when re-executing the net delay estimation method for the programmable logic device described above, the step of adapting the net path between the layout resources according to the net timing requirements between the layout resources with interconnections within the region includes:
[0021] The net timing margin between the layout resources is determined based on the net timing requirements between the layout resources and the difference in net path delay between two layout resources;
[0022] The net path with the minimum latency is adapted to the layout resources with the minimum net timing margin, until all layout resources within the region are adapted with the net path. Further, after the step of adapting the net path between layout resources according to the net timing requirements between layout resources with connectivity within the region, and using the delay of the net path as the net delay between layout resources, the method further includes:
[0023] The adaptation results of the net path are stored to provide the net path adaptation results for the routing stage of the programmable logic device.
[0024] Based on the above-described method for estimating the net delay of a programmable logic device, this application also provides a device for estimating the net delay of a programmable logic device, comprising:
[0025] The region partitioning module is used to divide the programmable logic device into several regions and obtain all programmable interconnects within the regions;
[0026] The wire path integration module is used to determine all wire paths composed of programmable interconnects in the area based on the location of the layout resources in the area, and to calculate the delay of each wire path. The wire path is used to provide wiring resources for any two layout resources that have a connection relationship in the area.
[0027] The delay estimation module is used to adapt the network path between the layout resources according to the network timing requirements between the layout resources that have a connection relationship within the region.
[0028] Furthermore, the net delay estimation device of the programmable logic device further includes:
[0029] A storage module is used to store the adaptation results of the net path, and to provide the net path adaptation results for the routing stage of the programmable logic device.
[0030] Based on the above-described method for estimating the network delay of a programmable logic device, this application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of the delay estimation method for the programmable logic device as described in any of the above claims.
[0031] Based on the above-described method for estimating the net delay of a programmable logic device, this application also provides a computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the delay estimation method for the programmable logic device as described in any of the above claims.
[0032] Compared to existing technologies, the advantages of this application are as follows:
[0033] The net delay estimation method for programmable logic devices provided in this application divides the programmable logic device into several regions, determines the total number of programmable interconnects in each region, and further obtains all net paths composed of programmable interconnects in the region based on the location of the layout resources. Appropriate net paths are allocated to two layout resources according to net timing requirements, and the delay of the net path is used as the estimation result. Since the programmable interconnects in the region are taken into account, the net delay can be estimated more accurately.
[0034] Furthermore, the net delay estimation method for programmable logic devices provided in this application estimates the net delay in real time based on the positional changes of layout resources during the placement process, and simulates the net contention and decongestion process in the routing process, so that the placement process can estimate a more accurate net delay based on the estimated total usage of programmable interconnects.
[0035] Furthermore, the net delay estimation method for programmable logic devices provided in this application can transmit the usage information of programmable interconnects generated by timing estimation to the routing module, thereby accelerating the routing speed and further ensuring the consistency of layout and routing timing. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 A flowchart illustrating a method for estimating the net delay of a programmable logic device provided in an embodiment of this application.
[0038] Figure 2 This is a simplified schematic diagram of the internal structure of an FPGA provided in an embodiment of this application.
[0039] Figure 3 Another flowchart of the net delay estimation method for programmable logic devices provided in the embodiments of this application.
[0040] Figure 4 This is a simplified schematic diagram of the FPGA architecture provided in the embodiments of this application.
[0041] Figure 5 This is a schematic diagram of an apparatus for a delay estimation method for a programmable logic device provided in an embodiment of this application.
[0042] Figure 6 This is a schematic diagram of another apparatus for a delay estimation method for a programmable logic device provided in an embodiment of this application.
[0043] Figure 7 A schematic diagram of a computer device provided in an embodiment of this application.
[0044] Figure 8 This is a schematic diagram of a computer storage medium provided in an embodiment of this application. Detailed Implementation
[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0046] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0047] FPGA (Field Programmable Gate Array) is one of the main types of commonly used programmable logic devices. It mainly consists of configurable logic modules (CLM), input / output blocks (IOB), and programmable interconnect modules (SRB). Among them, the programmable interconnect is the core structure of the FPGA. This structure contains a large number of programmable switch interconnect networks, which can complete the interconnection of port signals between programmable logic modules. The following embodiments illustrate the wire network delay estimation method of programmable logic devices using FPGA as an example.
[0048] Figure 1 A flowchart of the net delay estimation method for a programmable logic device provided in the embodiments of this application is shown below. Figure 1 As shown, the net delay estimation method for programmable logic devices provided in this application includes:
[0049] Step S1: Divide the programmable logic device into several regions and obtain the programmable interconnects within each region.
[0050] In FPGAs, programmable logic modules and programmable interconnect resources are arranged in regular arrays. That is, the number of programmable interconnect resources in an FPGA is deterministic. Therefore, if an FPGA is divided into several regions, the total number of programmable interconnect resources available in each region can be determined. The purpose of this application is to estimate the net delay of an FPGA during the placement process. The net delay of an FPGA refers to the delay of the programmable interconnects used to connect two placement resources after routing. Therefore, when the number of programmable interconnects in a region is determined, the net delay between two placement resources can also be determined.
[0051] It should be clarified that, for FPGAs, although the total number of internal programmable interconnect resources can be determined, directly obtaining the net paths based on the total number of programmable interconnect resources will result in the inability to calculate the net paths composed of programmable interconnects within the FPGA due to the large number of programmable interconnects. In addition, the programmable interconnect resources of FPGAs are in a regular array, which also includes many duplicate programmable interconnect resources. If the net paths are obtained directly based on the total number of programmable interconnect resources, many duplicate net paths will also be obtained. Therefore, it is necessary to perform regional calculations to avoid redundant calculations.
[0052] Step S2: Determine all net paths consisting of programmable interconnects within the area based on the location of the layout resources, and calculate the delay of each net path. The net path is used to provide routing resources for any two layout resources with a connection relationship within the area, that is, the net path is the routing resource in the routing process.
[0053] Because the FPGA has already expressed each functional module in hardware language before the placement process, and converted the functional modules described in hardware language into a design netlist for interconnecting basic logic units such as lookup tables, flip-flops, AND gates, and OR gates through logic synthesis, the basic logic units that make up the functional module are the placement resources of the FPGA placement process. In the FPGA, the connection relationship between placement resources can be obtained from the design netlist. Therefore, when the total amount of programmable interconnect resources in the region is determined in step S1 of this application embodiment, all the net paths composed of programmable interconnects in the region can be further determined according to the position of the placement resources in the region.
[0054] It should be clarified that the design netlist can only represent the connection relationship between layout resources. At this time, the position of the layout resources in the FPGA is not determined. The net path is the routing resource of the FPGA, which represents the specific connection of the layout resources in the FPGA. Therefore, in this embodiment, the position of the layout resources in the region is determined first, and then all the net paths in the region are obtained according to the specific position of the layout resources. In this embodiment, the net delay is estimated in the FPGA layout process, so the position of the layout resources in the region is determined by the layout process.
[0055] In some embodiments, the specific steps for calculating the delay of each wire path in step S2 include:
[0056] Step S21: Obtain the type of each programmable interconnect in the net path and determine the delay of different types of programmable interconnects.
[0057] Step S22: Accumulate the delay of each programmable interconnect to determine the delay of the net path.
[0058] Figure 2 This is a simplified schematic diagram of the internal structure of an FPGA provided in an embodiment of this application. The array of programmable logic modules in the FPGA is called a TILE. A TILE includes multiple programmable logic modules and a programmable interconnect module, such as... Figure 2 As shown, SRB represents a programmable relay box, and CLM represents a configurable logic module. Programmable logic units within a configurable logic module are connected to other configurable logic modules via programmable relay boxes. R is as follows... Figure 2The simplified diagram of the FPGA's internal structure illustrates that a TILE is reduced to a programmable interconnect and a programmable logic module. In an FPGA, programmable interconnects can be categorized into different types based on their span. These classifications based on span include:
[0059] A single line refers to the interconnection of adjacent programmable logic modules, i.e., those spaced one TILE apart. Figure 2 As shown, two adjacent programmable interconnects in the horizontal or vertical direction represent a line.
[0060] Two-wire refers to the interconnection of programmable logic modules with a distance of two TILEs, such as... Figure 2 As shown, a programmable interconnect line spaced one TILE horizontally or vertically represents a two-wire interconnect.
[0061] Four-wire refers to the interconnection of programmable logic modules spaced four times apart. Figure 2 Four lines are not shown, but similar to one-line and two-line, a programmable interconnect with a horizontal or vertical spacing of 3 TILE represents a four-line interconnect.
[0062] The definition of "longline" may vary depending on the FPGA architecture design, but it typically refers to the interconnection of programmable logic modules spaced 8-16 TILEs apart. Figure 2 The four lines are not shown, but it should be clear that the definition of the long line is the same as that of the first, second, and fourth lines.
[0063] Theoretically, programmable interconnects of the same type have the same delay. However, the larger the span of a programmable interconnect, the greater its delay. That is, long line delay > four-line delay > two-line delay > one-line delay. Therefore, the embodiments of this application can calculate the delay of a net path based on the type of programmable interconnects contained in the net path.
[0064] It should be clear that, in fact, for FPGAs, even programmable interconnects of the same type may have small delay errors, or the delays of programmable interconnects of the same type in different directions (horizontal and vertical directions) may also have small delay errors. However, such errors are negligible compared to the delays between different types of programmable interconnects. Furthermore, if higher accuracy is desired, delay errors caused by different directions can still be obtained, and the total delay of the net path can be calculated by accumulating the results in steps S21 and S22.
[0065] Step S3: Adapt net paths between layout resources according to the net timing requirements between any two layout resources with connectivity within the region, and use the delay of the net path as the net delay between layout resources.
[0066] In FPGAs, circuit performance is related to net delay. When other parameters affecting circuit performance (such as device delay and clock delay) are ignored, generally, the smaller the net delay, the higher the circuit performance; conversely, the larger the net delay, the lower the circuit performance, indicating poor timing. FPGA designs have performance requirements, and timing analysis tools analyze the circuit's performance based on these requirements, calculating the delay requirements for each path, i.e., the net timing requirements. During placement and routing, the actual net delay is optimized to meet these requirements as much as possible.
[0067] In this embodiment, since all net paths within the region have been obtained, it is only necessary to allocate appropriate net paths to two connected layout resources according to the net timing requirements, so that the net paths can meet the net timing requirements. Because this embodiment ultimately needs to estimate the net delay between all layout resources within the region, when allocating net paths, this embodiment will allocate them sequentially within the region. That is, the higher the net timing requirement, the lower the delay of the allocated net path, so as to ensure that the net delay between all layout resources within the region meets the net timing requirements.
[0068] It should be clear that in the embodiments of this application, the purpose of allocating net paths to two layout resources with a connection relationship is to use the delay of the net path as an estimation result. The FPGA does not necessarily use the estimated net path for routing in the routing process. The result is only for reference in the routing process.
[0069] In some embodiments, step S3, which involves adapting net paths between layout resources based on net timing requirements between interconnected layout resources within a region, specifically includes:
[0070] Step S31: Determine the net timing margin between layout resources based on the difference between the net timing requirements between layout resources and the net setting delay between layout resources.
[0071] Timing margin equals net timing requirement minus net delay. When the actual net delay is greater than the net timing requirement, a timing violation will occur, meaning that the performance cannot meet the design requirements. In this embodiment, net delay is a parameter to be estimated. Therefore, in order to calculate timing margin, designers will set an initial value as the net setting delay between two placement resources when designing the FPGA. Usually, this initial value is set by the designer based on experience, or the designer can also perform an estimation before the FPGA implementation of the placement process using a rough delay estimation method, and use the estimation result as the net setting delay.
[0072] Step S32: Adapt the net path with the shortest latency to the layout resources with the shortest timing margin, until all layout resources in the area are adapted with net paths. The smaller the timing margin, the closer the timing requirements are to the net set latency. In order to ensure that the net latency between all layout resources in the area meets the net timing requirements, the net path with the shortest latency should be assigned to the two layout resources with the shortest timing margin.
[0073] In some embodiments, the net delay estimation method for programmable logic devices provided in this application further includes:
[0074] When the location of resources within the area changes, steps S1 through S3 are executed again.
[0075] It should be clear that during the placement process of an FPGA, the position of the placement resources within the area may change at any time as the placement process runs. The net path that has been estimated above will also need to be re-estimated due to the change in the position of the placement resources. That is, the net delay estimation method for programmable logic devices provided in this application embodiment is dynamically running during the placement process.
[0076] In other embodiments, the location of the layout resources may change, but their location usually does not exceed the area already divided in step S1, so when re-estimating, it is only necessary to re-execute step S3.
[0077] In some embodiments, when the location of a layout resource changes, step S3, which involves adapting the net path between layout resources based on the net timing requirements between layout resources with connectivity within the region, specifically includes:
[0078] The net timing margin between two layout resources is determined based on the net timing requirements between the layout resources and the difference in net path delay between the two layout resources.
[0079] The net path with the least latency is adapted to the layout resources with the least net timing margin until all layout resources in the area are adapted with net paths.
[0080] When re-estimating the net path, you only need to calculate the timing margin based on the net timing requirements and the previously estimated net path delay.
[0081] In some embodiments, Figure 3 Another flowchart of the net delay estimation method for programmable logic devices provided in the embodiments of this application is shown below. Figure 3As shown, after step S3, which allocates net paths to two connected layout resources based on the net timing requirements between them within the region and uses the delay of the net path as the net delay between the two layout resources, the method further includes:
[0082] Step S4: Store the adaptation results of the net path to provide the net path adaptation results for the routing stage of the programmable logic device.
[0083] The net delay estimation method for programmable logic devices provided in this application not only estimates the net delay during the placement process, but also retains the estimated results from the placement stage to the routing process for reference. This not only speeds up routing but also further ensures the consistency of placement and routing timing results. It should be clear that when the net delay is determined, it means that the connection relationship of the programmable interconnects is determined. Furthermore, the congestion caused by the programmable interconnects in the area can also be determined. Therefore, the results estimated during the placement stage include not only the net delay but also the congestion that the net path may cause.
[0084] The net delay estimation method for programmable logic devices provided in this application divides the programmable logic device into several regions, thereby determining the total number of programmable interconnects in each region. Based on the location of the layout resources and the connection relationship of the designed nets, the method further calculates all net paths composed of programmable interconnects in the region. Appropriate net paths are allocated to two layout resources according to net timing requirements. Compared with the prior art, this method can estimate more accurate net delay.
[0085] Furthermore, the net delay estimation method for programmable logic devices provided in this application estimates the net delay in real time based on the positional changes of layout resources during the layout process, and simulates the net contention and decongestion process in the routing process, enabling the layout process to estimate a more accurate net delay based on the estimated total usage of programmable interconnects.
[0086] The following is based on Figure 4 The method for estimating the net delay of a programmable logic device provided in the embodiments of this application is illustrated by example. Figure 4 A simplified schematic diagram of the FPGA architecture provided in the embodiments of this application, as shown below. Figure 4 As shown, the simplified programmable logic module (CLM) in this embodiment includes only 4 flip-flops, and the programmable interconnect (SRB) is simplified to only one-wire and two-wire interconnect resources. A TILE is simplified to consist of a programmable logic module and a programmable interconnect.
[0087] For ease of illustration, assume that the delay of the first line is 5 and the delay of the second line is 8, and that programmable interconnects of the same type have the same delay in the horizontal and vertical directions.
[0088] Suppose we want to estimate the latency of net1 between trigger FF0 of TILE_0_0 and trigger FF0 of TILE_2_0, the latency of net2 between trigger FF1 of TILE_0_0 and trigger FF1 of TILE_2_0, and the latency of net3 between trigger FF2 of TILE_0_0 and trigger FF2 of TILE_2_0, and assume that net1 has the smallest timing margin and net3 has the largest timing margin; for ease of explanation, assume that the layout resources in this area only include those described above.
[0089] In such Figure 4 Within the area shown, all possible net paths are obtained. In this embodiment, the net paths include:
[0090] Net path 1: From TILE_0_0 to TILE_2_0, the delay of net path 1 is 8;
[0091] Net path 2: Line 1 from TILE_0_0 to TILE_1_0, Line 1 from TILE_1_0 to TILE_2_0, line delay is 5+5=10;
[0092] Network path 3: Line 1 TILE_0_0 to TILE_0_1, Line 2 TILE_0_1 to TILE_2_1, Line 1 TILE_2_1 to TILE_2_0, line delay is 5+8+5=18;
[0093] Net path 4: Line 1 from TILE_0_0 to TILE_0_1, Line 1 from TILE_0_1 to TILE_1_1, Line 1 from TILE_1_1 to TILE_2_1, Line 1 from TILE_2_1 to TILE_2_0, Line delay is 5+5+5+5=20;
[0094] To facilitate the explanation of the net delay estimation method for programmable logic devices provided in this application embodiment, only four net paths are listed here for illustration, but it is easy to see that... Figure 4 There are far more than four wire paths between TILE_0_0 and TILE_2_0 within the area shown.
[0095] It should be clarified that, for ease of explanation, such as Figure 4 The schematic diagram shown illustrates the connection of programmable interconnects. However, in reality, the FPGA placement process does not involve the actual connection of programmable interconnects. But when estimating latency, the connection relationship between placement resources can be obtained from the FPGA design netlist.
[0096] As shown above, when estimating net delay, net paths are first assigned to net1 with the smallest timing margin. Net path 1 has the smallest delay, so the delay of net path 1 is used as the estimated delay result of net1. Next, net paths are assigned to net2. Net path 2 has the smallest delay, so the delay of net path 2 is used as the estimated delay result of net2. Finally, net paths are assigned to net3. Net path 3 has the smallest delay, so the delay of net path 3 is used as the estimated delay result of net3.
[0097] It should be understood that the delay estimation examples in the embodiments of this application are only for the purpose of explaining the principle. In the actual layout process, when performing delay estimation, a corresponding algorithm will be designed based on the net delay estimation method provided in the embodiments of this application to improve the running speed of the software.
[0098] Based on the above-described method for estimating the net delay of programmable logic devices, this application also provides a net delay estimation device 30 for programmable logic devices, such as... Figure 5 As shown, the device includes:
[0099] The region partitioning module 100 is used to divide the programmable logic device into several regions and obtain all programmable interconnects within each region;
[0100] The net path integration module 200 is used to determine all net paths consisting of programmable interconnects in the area based on the location of the layout resources in the area, and to calculate the delay of each net path. The net path is used to provide wiring resources for any two layout resources that have a connection relationship in the area.
[0101] The delay estimation module 300 is used to adapt the net path between layout resources according to the net timing requirements between layout resources with connection relationships in the region.
[0102] In some embodiments, such as Figure 6 As shown, this application embodiment also provides a net delay estimation device 40 for a programmable logic device. In addition to a region partitioning module 100, a net path integration module 200, and a delay estimation module 300, the device 40 also includes:
[0103] The storage module 400 is used to store the adaptation results of the net path, providing the net path adaptation results for the routing stage of the programmable logic device.
[0104] For further details regarding the implementation of the above technical solution by each module in the above-mentioned net delay estimation device for programmable logic devices, please refer to the description in the net delay estimation method for programmable logic devices provided in the above embodiments, which will not be repeated here.
[0105] Based on the above-described method for estimating the net delay of programmable logic devices, this application also provides a computer device 50, such as... Figure 7 As shown, it includes a memory 51, a processor 52, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the delay estimation method for the programmable logic device provided in the above embodiments.
[0106] Based on the above-described method for estimating the net delay of programmable logic devices, this application also provides a computer-readable storage medium 60, such as... Figure 8 As shown, the computer-readable storage medium 60 stores a computer program 61, which, when executed by a processor, implements the steps of the delay estimation method for the programmable logic device provided in the above embodiments.
[0107] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.
Claims
1. A method for estimating the net delay of a programmable logic device, characterized in that, include: The programmable logic device is divided into several regions, and the programmable interconnects within the regions are obtained; The network path composed of the programmable interconnects in the region is determined based on the location of the layout resources in the region, and the delay of each network path is calculated. The network path is used to provide wiring resources for two layout resources that have a connection relationship in the region. According to the timing requirements of the nets between the layout resources that have a connection relationship within the region, the net path is adapted between the layout resources, and the delay of the net path is used as the net delay between the layout resources. The step of determining the network path composed of the programmable interconnects within the region based on the location of the resources within the region includes: Based on the connection relationships between the layout resources, the location of the layout resources, and the programmable interconnects within the region, determine all net paths composed of the programmable interconnects within the region; The step of adapting the net path between the layout resources according to the net timing requirements between the layout resources with connectivity within the region includes: The net timing margin between the layout resources is determined based on the difference between the net timing requirements between the layout resources and the net setting delay between the layout resources; The net path with the least latency is adapted to the layout resources with the least net timing margin, until all the layout resources in the region are adapted to the net path.
2. The method for estimating the net delay of a programmable logic device as described in claim 1, characterized in that, The step of calculating the delay of each of the net paths includes: Obtain the type of each programmable interconnect in the net path, and determine the delay of the programmable interconnect of different types; The delay of each of the programmable interconnects is summed to determine the delay of the net path.
3. The method for estimating the net delay of a programmable logic device as described in claim 1, characterized in that, Also includes: When the location of the resources within the region changes, the net delay estimation method for the programmable logic device as described in claim 1 is re-executed.
4. The method for estimating the net delay of a programmable logic device as described in claim 3, characterized in that, The step of adapting the net path between the layout resources according to the net timing requirements between the layout resources with connectivity within the region includes: The net timing margin between the layout resources is determined based on the net timing requirements between the layout resources and the difference in net path delay between two layout resources; The net path with the least latency is adapted to the layout resources with the least net timing margin, until all the layout resources in the region are adapted to the net path.
5. The method for estimating the net delay of a programmable logic device as described in claim 1, characterized in that, After the step of adapting the net path between the layout resources according to the net timing requirements between the layout resources with connectivity within the region, and using the delay of the net path as the net delay between the layout resources, the method further includes: The adaptation results of the net path are stored to provide the net path adaptation results for the routing stage of the programmable logic device.
6. A wire delay estimation device for a programmable logic device, characterized in that, include: The region partitioning module is used to divide the programmable logic device into several regions and obtain all programmable interconnects within the regions; The wire path integration module is used to determine all wire paths composed of programmable interconnects in the area based on the location of the layout resources in the area, and to calculate the delay of each wire path. The wire path is used to provide wiring resources for any two layout resources that have a connection relationship in the area. The delay estimation module is used to adapt the net path between the layout resources according to the net timing requirements between the layout resources that have a connection relationship in the region, and use the delay of the net path as the net delay between the layout resources. The network path integration module is used to determine and obtain all network paths composed of the programmable interconnects within the region based on the location of the resources within the region, including: Based on the connection relationships between the layout resources, the location of the layout resources, and the programmable interconnects within the region, determine all net paths composed of the programmable interconnects within the region; The delay estimation module is used to adapt the network path between the layout resources according to the network timing requirements between the layout resources with connectivity within the region, including: The net timing margin between the layout resources is determined based on the difference between the net timing requirements between the layout resources and the net setting delay between the layout resources; The net path with the least latency is adapted to the layout resources with the least net timing margin, until all the layout resources in the region are adapted to the net path.
7. The net delay estimation device for a programmable logic device as described in claim 6, characterized in that, Also includes: A storage module is used to store the adaptation results of the net path, and to provide the net path adaptation results for the routing stage of the programmable logic device.
8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the delay estimation method for the programmable logic device as described in any one of claims 1 to 5.
9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the delay estimation method for the programmable logic device as described in any one of claims 1 to 5.