A dessert search method based on load traction, an electronic device and a storage medium

Abstract

The application provides a dessert search method based on load pulling, an electronic device and a storage medium. For a transistor that needs to be pulled, preset pulling simulation conditions and a power backoff range; based on the preset pulling simulation conditions, a source impedance point corresponding to a maximum output power is determined; the source impedance point corresponding to the maximum output power is set as the source impedance of the transistor, the third-order intermodulation characteristics of the transistor at each load impedance point are calculated, and the dessert position at each load impedance point is determined; according to the dessert position at each load impedance point, the transistor output characteristic information at the input power corresponding to each dessert position is calculated; and the optimal load impedance point is determined. Compared with the prior art, the linear degree in the backoff range is synchronously monitored and the dessert is searched, and the dessert at each load impedance point in the preset backoff range is found, and the dessert position and its depth under different impedances are displayed in the form of an impedance circle diagram.

Description

Technical Field

[0001] This invention relates to the field of high linearity power amplifier design technology, and more specifically, to a sweet spot search method, electronic device, and storage medium based on load pulling. Background Technology

[0002] Linearity is a crucial performance indicator in RF power amplifier design. To improve linearity, power back-off is often employed to minimize the clipping of the RF output signal waveform and reduce distortion; however, this approach comes at the cost of efficiency. To address this issue, numerous linearization techniques have been proposed to improve linearity while minimizing efficiency loss. These techniques fall into two main categories. The first involves adding external functional circuitry to the existing power amplifier; however, this approach introduces problems such as increased cost, size, bandwidth, and even further efficiency degradation due to the additional circuitry. The second category focuses on improving the power amplifier design architecture by enhancing transistor linearity. This method primarily addresses input power, harmonic impedance, and bias point selection. By choosing the optimal bias and harmonic matching impedance, it ultimately improves overall power amplifier linearity while maintaining efficiency. Among these, the linearity optimization method based on the third-order intermodulation sweet spot of transistors utilizes the third-order intermodulation minimum in the power sweep curve to reduce power back-off and thus ensure efficiency, making it an ideal solution for high-linearity power amplifier design.

[0003] The third-order intermodulation sweet spot is characterized by a trend of decreasing and then increasing intermodulation near a certain input power point in the power scan curve as the input power increases. Essentially, it is a phase cancellation phenomenon between the large-signal and small-signal third-order intermodulation components. Regarding sweet spot research, in 1999, NB DeCarvalho et al. from the University of Aveiro, Portugal, proposed a transistor-level behavioral model, achieving the first prediction of sweet spot characteristics [NB DeCarvalho and JC Pedro, "Large- and small-signal IMD behavior of microwave power amplifiers," IEEE Transactions on Microwave Theory and Techniques[, vol.47, no. 12, pp. 2364-2374, Dec. 1999.], and applied it to the study of the principle of dessert production and its control methods. In 2005, Yong-Sub Lee et al. from Pohang University of Science and Technology in South Korea conducted research on the temperature correlation of desserts in LDMOS RF power amplifiers [Yong-Sub Lee, Seung-Yup Lee and Yoon-Ha Jeong, "Effects of temperature on the IMD sweet spots in an LDMOSFET RF power amplifier," , 2005 Asia-Pacific Microwave Conference Proceedings [Y.-S. Lee, M.-W. Lee, S.-W. Jung and Y.-H. Jeong, "AnalogPredistortion Power Amplifier Using IMD Sweet Spots for WCDMA Applications," 2005, pp. 1-4.], analyzed the mechanism of temperature influence on the position of sweet spots and its bias correlation. In 2007, the authors further applied sweet spots to the design of an analog predistortion amplifier [Y.-S. Lee, M.-W. Lee, S.-W. Jung and Y.-H. Jeong, "AnalogPredistortion Power Amplifier Using IMD Sweet Spots for WCDMA Applications," 2007 Asia-Pacific Microwave Conference [2007, pp. 1-4.] This study utilizes the sweet spot effect to eliminate third- and fifth-order intermodulation components, thereby improving the linearity of power amplifiers under WCDMA signal excitation. In 2017, PE de Falco et al. from the University of Bristol, UK, conducted research on the sweet spot effect in the response of Class AB amplifiers [PE de Falco, J. Birchall and L. Smith, "Hitting the Sweet Spot: A Single-Ended PowerAmplifier Exploiting Class AB Sweet Spots and Optimized Third HarmonicTermination," (2007, pp. 1-4). IEEE Microwave Magazine [, vol. 18, no. 1, pp. 63-70, Jan.-Feb.2017.], The authors achieved a 44% power-added efficiency in two-tone mode at -30 dBc under third-order intermodulation by optimizing the third harmonic termination impedance of the transistor to control the sweet spot.

[0004] While the existing technologies described above provide the mechanisms for sweet spot generation and their control methods, they still cannot be integrated with the load-pulling methods of traditional power amplifier designs. Furthermore, the variable bias-based sweet spot control method requires repeated adjustments to achieve the optimal sweet spot, resulting in poor design efficiency. Therefore, how to combine sweet spot search with load-pulling technology to achieve highly efficient sweet spot control is a pressing issue that needs to be addressed in high-linearity designs based on transistor sweet spot technology. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a transistor sweet spot search method that can be used in chip design, which can further improve the linearity of transistors based on traditional load-pull design methods, and can be used to guide the design of high linearity power amplifiers.

[0006] A first aspect of the present invention provides a dessert search method based on load traction, the method comprising:

[0007] Step 1: For the transistors that need to be pulled, preset the pulling simulation conditions and power back-off range;

[0008] Step 2: Based on the preset traction simulation conditions, perform source traction and load traction with the maximum output power as the target, and determine the source impedance point corresponding to the maximum output power.

[0009] Step 3: Take the source impedance point corresponding to the maximum output power as the source impedance of the transistor. At the same time, determine the impedance scanning point according to the impedance scanning range in the preset traction simulation conditions in Step 1. Then, take each impedance scanning point as the load impedance of the transistor, perform harmonic balance simulation, calculate the third-order intermodulation characteristics of the transistor at each load impedance point, and determine the sweet spot position at each load impedance point.

[0010] Step 4: Based on the sweet spot position at each load impedance point, calculate the output power, power-added efficiency, and sweet spot depth at each sweet spot position corresponding to the input power.

[0011] Step 5: Compare the output power, power-added efficiency, sweet spot position and sweet spot depth at each load impedance point to determine the optimal load impedance point.

[0012] Preferably, the preset traction simulation conditions and power back-off range for the transistors that need to be pulled include: for the transistors that need to be pulled, preset simulation conditions for source pulling and load pulling using their large-signal model; the simulation conditions include: frequency, dual-tone frequency interval, static gate-source and drain-source bias voltage, saturated input power point, horizontal and vertical coordinates of the load pulling scan circle center, number of load pulling scan points, and load pulling scan radius.

[0013] Preferably, the step of determining the source impedance point corresponding to the maximum output power by performing source traction and load traction based on preset traction simulation conditions and with the maximum output power as the target includes:

[0014] Step 2-1: Based on the load traction scanning center, number of scanning points, and scanning radius, generate a source impedance scanning point distribution map under the rule of ensuring the same number of points in the direction parallel to and perpendicular to the zero impedance line in the Smith chart and that the impedance points in each direction are equally distributed; perform harmonic balance simulation at each impedance point, calculate the output power of the transistor, and select the source impedance point corresponding to the maximum output power.

[0015] Step 2-2: Set the source impedance point selected in Step 2-1 as the source impedance of the transistor, and take each impedance point in the impedance scanning point distribution diagram generated in Step 2-1 as the load impedance of the transistor. Perform harmonic balance simulation, calculate the output power of the transistor at each point, and select the load impedance point corresponding to the maximum output power.

[0016] Step 2-3: Set the load impedance point selected in Step 2-2 as the load impedance of the transistor, repeat Step 2-1, and find the source impedance corresponding to the maximum output power for subsequent sweet spot load pulling.

[0017] Preferably, the calculation of the third-order intermodulation characteristics of the transistor at each load impedance point, and the determination of the sweet spot position at each load impedance point, includes:

[0018] The input power range corresponding to the third-order intermodulation characteristic at each impedance point is the power back-off range; the third-order intermodulation characteristic is calculated by averaging the upper and lower sideband components of the third-order intermodulation.

[0019] Based on the calculated third-order intermodulation characteristics at each load impedance point, the sweet spot is found by searching for the third-order intermodulation minimum within the power back-off range, and the input power corresponding to the sweet spot is determined as the sweet spot position.

[0020] Preferably, the step of calculating the output power, power-added efficiency, and sweet spot depth at each sweet spot position based on the sweet spot position at each load impedance point includes:

[0021] Based on the sweet spot position at each load impedance point, the output power and power-added efficiency at the corresponding input power at that position are calculated using commercial SPICE simulation software.

[0022] The sweet spot depth at each load impedance point is calculated using the following steps:

[0023] Step 4-1: Determine the sweet spot. If there is no sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is 0, then set the sweet spot depth of the point to 0. If there is a sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is not 0, then retrieve the third-order intermodulation characteristic within the power back-off range corresponding to the impedance point.

[0024] Step 4-2: Calculate the first-order differential based on the third-order intermodulation characteristics at this impedance point, and find the input power range where the differential is less than 0. Determine the start and end input power values ​​for this range. P sp_start and P sp_stop ;

[0025] Step 4-3: Use commercial SPICE simulation software to calculate the input power respectively. P sp_start -3dB and P sp_stop + The third-order intermodulation characteristic at 3dB is calculated, and based on the two input power values ​​and their third-order intermodulation characteristics, the slope of the straight line passing through the two data points is calculated respectively. K IMD3_sp and intercept b IMD3_sp Based on this, and using the slope and intercept of the straight line, a hypothesis about the input power is constructed. P in Third-order intermodulation P IMD3_sp curve equation P IMD3_sp = K IMD3_sp × P in + b IMD3_sp ;

[0026] Step 4-4: Substitute the input power corresponding to the dessert into the curve equation to calculate the power at the dessert's location. P IMD3_sp This represents the dessert depth corresponding to that dessert.

[0027] Furthermore, a second aspect of the present invention provides an electronic device comprising: one or more processors, and a memory for storing one or more computer programs; the computer programs being configured to be executed by the one or more processors, the programs including steps for performing the load-driven dessert search method described above.

[0028] Furthermore, a third aspect of the present invention provides a storage medium storing a computer program; the program is loaded and executed by a processor to implement the steps of the load-driven dessert search method as described in any of the preceding claims.

[0029] In this invention, for the transistor requiring traction, preset traction simulation conditions and power back-off range are defined. Based on the preset traction simulation conditions, source traction and load traction are performed with the maximum output power as the target, determining the source impedance point corresponding to the maximum output power. The source impedance point corresponding to the maximum output power is used as the source impedance of the transistor. Simultaneously, based on the impedance scanning range in the preset traction simulation conditions, impedance scanning points are determined, and each impedance scanning point is sequentially used as the load impedance of the transistor for harmonic balance simulation. The third-order intermodulation characteristics of the transistor at each load impedance point are calculated, and the sweet spot position at each load impedance point is determined. Based on the sweet spot position at each load impedance point, the output power, power-added efficiency, and sweet spot depth at each sweet spot position are calculated according to the input power. By comparing the output power, power-added efficiency, sweet spot position, and sweet spot depth at each load impedance point, the optimal load impedance point is determined. Compared to existing technologies, on the one hand, by presetting the power back-off range, the linearity at each input power point within the power range under different load impedances is calculated, achieving synchronous monitoring of linearity and sweet spot search within the back-off range. On the other hand, by combining load traction technology, the sweet spot at each impedance point within the preset back-off range is found. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of the dessert search method based on load traction disclosed in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the source traction and load traction impedance scanning point range in the Smith chart disclosed in the embodiments of the present invention;

[0033] Figure 3 This is a schematic diagram of the dessert search rules disclosed in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of dessert depth calculation disclosed in an embodiment of the present invention;

[0035] Figure 5It is an impedance circle diagram drawn in the Smith circle diagram disclosed in the embodiments of the present invention;

[0036] Figure 6 This is an impedance circle diagram drawn from a Smith chart under specific parameters disclosed in an embodiment of the present invention;

[0037] Figure 7 These are the power scan curves corresponding to each load impedance point in Table 1 disclosed in the embodiments of the present invention;

[0038] Figure 8 This is a flowchart of the overall technical solution disclosed in the embodiments of the present invention. Detailed Implementation

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0041] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0042] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0043] It should be noted that "multiple" as mentioned in this article refers to two or more.

[0044] The implementation details of the technical solutions in the embodiments of this application are described in detail below:

[0045] This embodiment provides a dessert search method based on load traction, such as... Figure 1 As shown, the method includes:

[0046] Step S1: For the transistors that need to be pulled, preset the traction simulation conditions and power back-off range.

[0047] Specifically, in this embodiment, for the transistor that needs to be pulled, simulation conditions for source pulling and load pulling using its large-signal model are preset, including: frequency. f Dual-tone frequency interval ∆ f Static gate-source and drain-source bias voltages V gs and V ds Saturated input power point P in-3dB Load-driven traction scanning center horizontal / vertical coordinates x_center / y_center Load traction scan points N_lp Load traction scan radius R_lp .

[0048] In addition, the amount of power to be backed up needs to be set in order to determine the power back-off range. BO The power back-off range is... P in-3dB - BO ~ P in-3dB .

[0049] Step S2: Based on the preset traction simulation conditions, perform source traction and load traction with the maximum output power as the target, and determine the source impedance point corresponding to the maximum output power.

[0050] Specifically, in this embodiment, based on preset traction simulation conditions, this embodiment will carry out source traction and load traction with the goal of maximum output power in the following steps.

[0051] Step S2-1: Based on the load traction scanning center, number of scanning points, and scanning radius, and in accordance with the rule of ensuring the same number of points in the directions parallel to and perpendicular to the zero impedance line in the Smith chart, and that the impedance points in each direction are equally distributed, a source impedance scanning point distribution map is generated; harmonic balance simulation is performed at each impedance point to calculate the transistor's output power, and the source impedance point corresponding to the maximum output power is selected.

[0052] Specifically, in this embodiment, the fixed load impedance is 50 ohms. Based on the load traction scanning center, number of scanning points, and scanning radius set in step 1, a source impedance scanning point distribution map is generated in the Smith chart, ensuring the same number of points are taken in both directions parallel and perpendicular to the zero impedance line, and that impedance points are evenly distributed in each direction. For example... Figure 2 The diagram shown illustrates the range of source-pull and load-pull impedance scanning points in the Smith chart of this embodiment. Based on this, commercial SPICE simulation software was used to perform harmonic balance simulations at each impedance point, calculating the transistor's output power and selecting the source impedance point corresponding to the maximum output power.

[0053] Step S2-2: Set the source impedance point selected in step S2-1 as the source impedance of the transistor, and take each impedance point in the impedance scanning point distribution diagram generated in step 2-1 as the load impedance of the transistor. Perform harmonic balance simulation, calculate the output power of the transistor at each point, and select the load impedance point corresponding to the maximum output power.

[0054] Specifically, in this embodiment, the impedance is set as the source impedance of the transistor, and respectively... Figure 2 Each impedance point is used as the load impedance of the transistor. The commercial SPICE simulation software is used to perform harmonic balance simulation, calculate the output power of the transistor at each point, and select the load impedance point corresponding to the maximum output power.

[0055] Step S2-3: Set the load impedance point selected in step S2-2 as the load impedance of the transistor, repeat step S2-1, and find the source impedance corresponding to the maximum output power for subsequent sweet spot load pulling.

[0056] Specifically, in this embodiment, this point is used as the load impedance of the transistor. Step S2-1 is repeated to find the source impedance corresponding to the maximum output power, which is used for subsequent sweet spot load pulling.

[0057] Step S3: The source impedance point corresponding to the maximum output power is used as the source impedance of the transistor. At the same time, the impedance scanning point is determined according to the impedance scanning range in the preset traction simulation conditions in step S1. Each impedance scanning point is used as the load impedance of the transistor in sequence to perform harmonic balance simulation, calculate the third-order intermodulation characteristics of the transistor at each load impedance point, and determine the sweet spot position at each load impedance point.

[0058] Preferably, the calculation of the third-order intermodulation characteristics of the transistor at each load impedance point and the determination of the sweet spot position at each load impedance point includes: the input power range corresponding to the third-order intermodulation characteristics at each impedance point is the power back-off range; the third-order intermodulation characteristics are calculated by averaging the upper and lower sideband components of the third-order intermodulation; based on the calculated third-order intermodulation characteristics at each load impedance point, the sweet spot is found by finding the third-order intermodulation minimum value within the power back-off range, and the input power corresponding to the sweet spot is determined as the sweet spot position.

[0059] Specifically, in this embodiment, the maximum output power determined in step S2 is used as the source impedance of the transistor, and simultaneously, the maximum output power is sequentially... Figure 2 Each impedance point is used as the load impedance of the transistor. Harmonic balance simulation is performed using commercial SPICE simulation software to calculate the third-order intermodulation characteristics of the transistor. The input power range corresponding to the third-order intermodulation characteristics at each impedance point is the power back-off range determined in step 1, with a step size of 1 dB. It should be noted that the third-order intermodulation characteristics in this patent are calculated by averaging the upper and lower sideband components of the third-order intermodulation.

[0060] Based on the calculated third-order intermodulation characteristics at each load impedance point, the sweet spot is located by finding the third-order intermodulation minimum within the power back-off range, thus determining the input power corresponding to the sweet spot, i.e., the sweet spot location. For example... Figure 3 The above is a schematic diagram of the dessert search rules in this embodiment, wherein, Figure 3 (a) shows the case where a sweet spot exists. If there is no minimum value within the power back-off range, it is determined that there is no sweet spot at that impedance point, i.e. Figure 3 In the case shown in (b), the sweet spot position of the impedance point is set to 0.

[0061] Step S4: Based on the sweet spot position at each load impedance point, calculate the output power, power-added efficiency, and sweet spot depth at each sweet spot position corresponding to the input power.

[0062] Preferably, the step of calculating the output power, power-added efficiency, and sweet spot depth corresponding to the input power at each sweet spot position based on the sweet spot position at each load impedance point includes: calculating the output power and power-added efficiency corresponding to the input power at each position using commercial SPICE simulation software based on the sweet spot position at each load impedance point.

[0063] The sweet spot depth at each load impedance point is calculated using the following steps:

[0064] Step S4-1: Determine the sweet spot. If there is no sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point (i.e., the sweet spot position is 0), then set the sweet spot depth of that point to 0. If there is a sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point (i.e., the sweet spot position is not 0), then retrieve the third-order intermodulation characteristic within the power back-off range corresponding to that impedance point.

[0065] Specifically, in this embodiment, a sweet spot determination is performed. If there is no sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is 0, then the sweet spot depth at that point is set to 0. If there is a sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is not 0, then the third-order intermodulation characteristic within the power back-off range corresponding to that impedance point in step S3 is retrieved. Specifically, as... Figure 4 The diagram shown illustrates the calculation of dessert depth in this example.

[0066] Step S4-2: Calculate the first-order differential based on the third-order intermodulation characteristics at the impedance point, and find the input power range where the differential is less than 0. Determine the start and end input power values ​​for this range. P sp_start and P sp_stop ;

[0067] Step S4-3: Use commercial SPICE simulation software to calculate the input power respectively. P sp_start -3dB and P sp_stop + The third-order intermodulation characteristic at 3dB is calculated, and based on the two input power values ​​and their third-order intermodulation characteristics, the slope of the straight line passing through the two data points is calculated respectively. K IMD3_sp and intercept b IMD3_sp Based on this, and using the slope and intercept of the straight line, a hypothesis about the input power is constructed. P in Third-order intermodulation P IMD3_sp curve equation P IMD3_sp = K IMD3_sp × P in + b IMD3_sp ;

[0068] Step S4-4: Substitute the input power corresponding to the dessert into the curve equation to calculate the position of the dessert. P IMD3_sp This represents the dessert depth corresponding to that dessert.

[0069] Furthermore, in this embodiment, after calculating the output power, power-added efficiency, and sweet spot depth at each impedance point, a pie chart of sweet spot position, sweet spot depth, output power, and power-added efficiency is further executed.

[0070] In this process, the calculated results of the sweet spot position, output power at the sweet spot position, power-added efficiency, and sweet spot depth at each load impedance point in steps S3 and S4 are associated with each impedance point position, and the sweet spot position corresponding to the preset simulation conditions in step S1 is obtained by using the contour plot method in the Smith chart. P in_sp ), output power ( P out ), power added efficiency ( PAE ) and dessert depth ( deltaIMD3 ) Circular diagram, such as Figure 5 The figure shown is the impedance circle plot drawn in the Smith chart of this embodiment, wherein, Figure 5 (a) is a circular diagram showing the location of the desserts. Figure 5 (b) is a circular diagram showing the depth of the dessert. Figure 5 (c) is a pie chart showing the output power at the dessert location. Figure 5 (d) is a power-added efficiency pie chart for the dessert location.

[0071] Figure 5 In the figure, different colors correspond to different values ​​for dessert position, dessert depth, output power, and power-added efficiency. The relationship between the values ​​of each indicator and the colors is shown in the rectangular color bars on the right side of the figure. (The dessert position impedance diagram is used as an example.) P in_sp For example, in the diagram, the sweet spot position of the impedance point in the yellow area corresponds to a higher input power, while when the load impedance is the impedance point in the blue area, the transistor's third-order intermodulation does not have a sweet spot within the preset power back-off range. Figure 5 (a) The impedance pie chart corresponding to the dessert location is shown, with each contour line corresponding to a different dessert location. Similar to the dessert location impedance pie chart, the other three impedance pie charts reflect the distribution of output power, power-added efficiency, and dessert depth index at each impedance point under the condition of input power corresponding to the dessert location.

[0072] Step S5: Compare the output power, power-added efficiency, sweet spot position and sweet spot depth at each load impedance point to determine the optimal load impedance point.

[0073] In one embodiment, based on actual circuit design specifications, and while ensuring that there are design margins for transistor output power, power-added efficiency, and linearity, the impedance point that can balance these specifications is selected by comparing the output power, power-added efficiency, sweet spot position, and sweet spot depth at each load impedance point, and is determined as the optimal load impedance point.

[0074] For example, at a frequency of 3.5 GHz, a frequency spacing of 10 MHz, and an offset of... V gs =-2.65 V, V ds =48 V, with a sweet spot search performed using a transistor large-signal model under the condition of a 7 dB back-off from the saturation power point (20 dBm) as the input power scan range, the results are as follows: Figure 6 The impedance circle plot shown above, plotted under specific parameters using the Smith chart, depicts the sweet spot position, sweet spot depth, output power, and power-added efficiency. To compare the various output characteristics of the transistor at different impedance points, this embodiment selects three impedance points for comparison, labeled m1, m2, and m3. Figure 6 (a) is a circular diagram showing the location of the desserts. Figure 6 (b) is a circular diagram showing the depth of the dessert. Figure 6 (c) is a pie chart showing the output power at the dessert location. Figure 6 (d) Power-added efficiency pie chart of dessert location.

[0075] For a clearer comparison Figure 6 The output characteristics at the three impedance points are shown in Table 1. The impedance values, output power, power-added efficiency, sweet spot location and sweet spot depth values ​​corresponding to each point are presented in this embodiment.

[0076] Table 1 Comparison of output power, power-added efficiency, sweet spot position and depth at each impedance point

[0077]

[0078] like Figure 6 As shown in Table 1, points m1 and m2 are both close to the impedance points corresponding to the peak sweet spot depth. However, the sweet spot appears 1 dB earlier at impedance point m1 than at impedance point m2. This means that if m1 is used as the load impedance, a 5 dB back-off from the saturation point is required to reach the sweet spot, while m2 only requires 4 dB. Therefore, choosing point m2 compared to m1 provides an additional 1 dB increase in output power and a 1.2% increase in efficiency. For impedance point m3, the power back-off is further reduced compared to points m1 and m2; however, due to its greater distance from the optimal power and efficiency impedance points, the output power and efficiency are lower than at points m1 and m2. Figure 6 Based on the comparison results in Table 1, point m2 can be considered the optimal load impedance point for high linearity design.

[0079] To verify the above comparison results, this embodiment further examines the fixation on Figure 6 The power sweep curves at the three load impedance points are as follows: Figure 7 The table shown is the power scan curve corresponding to each load impedance point in Table 1 of this embodiment. Figure 7 (a) is a graph of the third-order intermodulation curve; Figure 7 (b) is a graph showing the output power and power-added efficiency.

[0080] like Figure 7 As shown, the locations and depths of the sweet spots at the three load impedance points are basically consistent with those in Table 1. For output power and power-added efficiency, the differences between the curves corresponding to m1 and m2 are also small, and the values ​​are better than those corresponding to m3, which is consistent with the comparison results in Table 1. These results further verify the accuracy of the load-driven transistor sweet spot search method in this patent.

[0081] In summary, as Figure 8 The diagram shows the overall flowchart of the technical solution in this embodiment. After starting, the following steps are executed sequentially: presetting traction simulation conditions and power backoff range; performing source traction and load traction with the maximum output power as the target; calculating third-order intermodulation and searching for the sweet spot within the power backoff range; calculating the output power, power-added efficiency, and sweet spot depth at each impedance point; plotting a circle graph of sweet spot location, sweet spot depth, output power, and power-added efficiency; and determining the optimal sweet spot depth, power backoff value, and load impedance based on the impedance circle graph. This embodiment uses a load traction method to find the impedance point where the sweet spot will appear; based on the impedance circle graph obtained from the load, within the range where the sweet spot appears, the depth of the sweet spot is changed by selecting different impedance points, thus achieving control over the sweet spot.

[0082] Compared to existing technologies, this embodiment addresses the problem that traditional load traction can only find the optimal third-order intermodulation characteristics at a single input power point and cannot simultaneously view the linearity characteristics after power back-off. This patent achieves synchronous monitoring of linearity and sweet spot search within the back-off range by presetting the power back-off range and calculating the linearity at each input power point under different load impedances.

[0083] On the other hand, in order to address the problem that the traditional method of sweet spot control based on variable bias in transistor linearity optimization can only optimize sweet spot characteristics but does not have a sweet spot search function, this patent combines load traction technology to realize the function of finding sweet spots at each impedance point within a preset back-off range and displaying the position and depth of sweet spots at different impedances in the form of an impedance circle diagram.

[0084] A second aspect of this embodiment provides an electronic device comprising: one or more processors, and a memory for storing one or more computer programs; the computer programs being configured to be executed by the one or more processors, the programs including steps for performing the load-driven dessert search method described above.

[0085] Furthermore, a third aspect of this embodiment provides a storage medium storing a computer program; the program is loaded and executed by a processor to implement the steps of the load-driven dessert search method as described in any of the preceding embodiments.

[0086] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.

[0088] The units described as separate components may or may not be physically separate. As will be appreciated by those skilled in the art, the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0089] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0090] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or grid device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dessert search method based on load traction, characterized in that, The method includes: Step 1: For the transistors that need to be pulled, preset the pulling simulation conditions and power back-off range; Step 2: Based on the preset traction simulation conditions, perform source traction and load traction with the maximum output power as the target, and determine the source impedance point corresponding to the maximum output power. Step 3: Set the source impedance point corresponding to the maximum output power as the source impedance of the transistor. Simultaneously, determine the impedance scanning point based on the impedance scanning range preset in the traction simulation conditions of Step 1. Then, sequentially use each impedance scanning point as the load impedance of the transistor to perform harmonic balance simulation, calculate the third-order intermodulation characteristic of the transistor at each load impedance point, and determine the sweet spot position at each load impedance point. This includes: the input power range corresponding to the third-order intermodulation characteristic at each impedance point is the power back-off range; the third-order intermodulation characteristic is calculated by averaging the upper and lower sideband components of the third-order intermodulation; based on the calculated third-order intermodulation characteristic at each load impedance point, find the sweet spot by searching for the third-order intermodulation minimum value within the power back-off range, and determine the input power corresponding to the sweet spot as the sweet spot position. Step 4: Based on the sweet spot position at each load impedance point, calculate the output power, power-added efficiency, and sweet spot depth at each sweet spot position corresponding to the input power. Step 5: Compare the output power, power-added efficiency, sweet spot position and sweet spot depth at each load impedance point to determine the optimal load impedance point; The sweet spot depth at each load impedance point is calculated using the following steps: Step 4-1: Determine the sweet spot. If there is no sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is 0, then set the sweet spot depth of the point to 0. If there is a sweet spot in the third-order intermodulation characteristic of the transistor at the load impedance point, i.e., the sweet spot position is not 0, then retrieve the third-order intermodulation characteristic within the power back-off range corresponding to the impedance point. Step 4-2: Calculate the first-order differential based on the third-order intermodulation characteristics at this impedance point, and find the input power range where the differential is less than 0. Determine the starting and ending input power values ​​P for this range. sp_start and P sp_stop ; Step 4-3: Use commercial SPICE simulation software to calculate the input power P. sp_start -3dB and P sp_stop The third-order intermodulation characteristic at +3dB is used to calculate the slope K of the straight line passing through the two data points based on the two input power values ​​and their third-order intermodulation characteristics. IMD3_sp and intercept b IMD3_sp Based on this, and according to the slope and intercept of the straight line, a hypothesis about the input power P is constructed. in The third-order intermodulation P IMD3_sp The curve equation P IMD3_sp =K IMD3_sp ×P in +b IMD3_sp ; Step 4-4: Substitute the input power corresponding to the dessert into the curve equation to calculate P at the dessert location. IMD3_sp This represents the dessert depth corresponding to that dessert.

2. The dessert search method based on load traction according to claim 1, characterized in that, The pre-set simulation conditions and power back-off range for transistors that need to be pulled include: for transistors that need to be pulled, pre-setting simulation conditions for source pulling and load pulling using their large-signal model; the simulation conditions include: frequency, dual-tone frequency interval, static gate-source and drain-source bias voltage, saturated input power point, horizontal and vertical coordinates of the load pulling scan circle center, number of load pulling scan points, and load pulling scan radius.

3. The dessert search method based on load traction according to claim 2, characterized in that, The method, based on preset traction simulation conditions, performs source traction and load traction with the maximum output power as the target, and determines the source impedance point corresponding to the maximum output power, including: Step 2-1: Based on the load traction scanning center, number of scanning points, and scanning radius, generate a source impedance scanning point distribution map under the rule of ensuring the same number of points in the direction parallel to and perpendicular to the zero impedance line in the Smith chart and that the impedance points in each direction are equally distributed; perform harmonic balance simulation at each impedance point, calculate the output power of the transistor, and select the source impedance point corresponding to the maximum output power. Step 2-2: Set the source impedance point selected in Step 2-1 as the source impedance of the transistor, and take each impedance point in the impedance scanning point distribution diagram generated in Step 2-1 as the load impedance of the transistor. Perform harmonic balance simulation, calculate the output power of the transistor at each point, and select the load impedance point corresponding to the maximum output power. Step 2-3: Set the load impedance point selected in Step 2-2 as the load impedance of the transistor, repeat Step 2-1, and find the source impedance corresponding to the maximum output power for subsequent sweet spot load pulling.

4. The dessert search method based on load traction according to claim 3, characterized in that, The step of calculating the output power and power-added efficiency at each sweet spot position based on the sweet spot position at each load impedance point includes: Based on the sweet spot position at each load impedance point, the output power and power-added efficiency at the corresponding input power are calculated using commercial SPICE simulation software.

5. An electronic device, the electronic device comprising: One or more processors, a memory for storing one or more computer programs; characterized in that the computer programs are configured to be executed by the one or more processors, the programs including steps for performing the load-driven dessert search method as described in any one of claims 1-4.

6. A storage medium storing a computer program; characterized in that, The program is loaded and executed by a processor to implement the steps of the load-driven dessert search method as described in any one of claims 1-4.

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