Memory devices, memory systems including memory devices, and methods of operating the same

Abstract

Embodiments of the present disclosure relate to a memory device, a memory system including the same, and an operating method thereof. The memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of pages coupled with a plurality of word lines, respectively. The peripheral circuit is configured to perform a program loop including a program pulse operation of applying a program voltage to a selected word line and a verify operation of applying at least one verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines. The control logic is configured to increase a level of the verify pass voltage applied to at least one of the unselected word lines whenever the peripheral circuit performs a next program loop when threshold voltages of memory cells included in a page coupled with the selected word line are greater than a reference level.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0125825, filed on September 23, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this teaching generally relate to electronic devices, and more specifically to memory devices, memory systems including memory devices, and methods of operating memory devices. Background Technology

[0004] A memory system is a device configured to store data in response to control by a host device such as a computer or smartphone. A memory system may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices or non-volatile memory devices.

[0005] Volatile memory devices can retain data as long as power is supplied, but may lose stored data when power is lost. Volatile memory devices can include, for example, static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices refer to memory devices that do not lose data even when there is no power supply. Non-volatile memory can include, for example, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0007] Various embodiments relate to memory devices that prevent the generation of underprogrammed memory cells, memory systems including memory devices, and methods for operating memory devices.

[0008] According to one embodiment of this disclosure, a memory device may include a memory block, peripheral circuitry, and control logic. The memory block includes a plurality of pages, each coupled to a plurality of word lines. The peripheral circuitry is configured to execute a programming cycle, the programming cycle including: a programming pulse operation applying a programming voltage to a selected word line corresponding to an address among the plurality of word lines; and a verification operation applying at least one verification voltage corresponding to the programming voltage to the selected word line and applying a verification pass voltage to an unselected word line. The control logic is configured to control the peripheral circuitry to repeatedly execute a next programming cycle including the programming pulse operation and the verification operation until a pass signal is received, indicating that the programming pulse operation has passed according to the verification operation. The control logic is further configured to: when a threshold voltage of a memory cell included in a page coupled to the selected word line is greater than or equal to a reference level, each time the peripheral circuitry executes a next programming cycle, increase the level of the verification pass voltage applied to at least one unselected word line among the unselected word lines.

[0009] According to one embodiment of this disclosure, a memory system may include a memory device comprising a plurality of pages respectively coupled to a plurality of word lines. The memory system may further include a memory controller configured to, upon receiving a programming command and an address, control the memory device to repeatedly execute a programming cycle including a programming pulse operation and a verification operation. The programming pulse operation includes applying a programming voltage to a selected word line corresponding to an address among the plurality of word lines and applying a programming pass voltage to an unselected word line. The verification operation includes applying a verification voltage to the selected word line and applying a verification pass voltage to the unselected word line. The memory controller may also be configured to, each time the memory device executes a programming cycle, increase the level of the programming voltage applied to the selected word line and the level of the verification pass voltage applied to the unselected word line until a pass signal is received, indicating that the programming pulse operation has passed according to the verification operation.

[0010] According to one embodiment of this disclosure, a method of operating a memory device including a memory block may include receiving a programming command and an address. The method may further include sequentially performing a programming pulse operation and a verification operation during a first programming cycle. The programming pulse operation includes applying a programming voltage to a selected word line corresponding to an address among a plurality of word lines respectively coupled to a plurality of pages included in the memory block. The verification operation includes applying a verification voltage corresponding to the programming voltage to the selected word line and applying a verification pass voltage to an unselected word line. The method may further include sequentially performing a programming pulse operation in which the level of the programming voltage is increased and a verification operation in which the level of the verification pass voltage is increased during a second programming cycle when a threshold voltage of a memory cell included in a page coupled to a selected word line is greater than or equal to a reference level and less than a target level higher than the reference level. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0012] Figure 2 This is a diagram illustrating the structure of a memory device according to an embodiment of the present disclosure;

[0013] Figure 3 This is a diagram illustrating the structure of a memory block according to an embodiment of the present disclosure;

[0014] Figures 4A to 4D This is a diagram illustrating the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure;

[0015] Figure 5 This is a diagram illustrating selected and unselected word lines according to an embodiment of the present disclosure;

[0016] Figure 6 This is a diagram illustrating a programming loop according to an embodiment of the present disclosure;

[0017] Figure 7 This is a diagram illustrating a structure for verifying the voltage according to an embodiment of the present disclosure;

[0018] Figure 8A This is a diagram illustrating the verification of the condition under which the voltage is changed according to an embodiment of the present disclosure;

[0019] Figure 8B This is a diagram illustrating the change in voltage as an increase is applied, according to an embodiment of the present disclosure.

[0020] Figure 9 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure;

[0021] Figure 10 This is a detailed diagram illustrating the operation of a memory device according to an embodiment of the present disclosure;

[0022] Figure 11 This is a diagram illustrating the structure of a memory controller according to an embodiment of the present disclosure;

[0023] Figure 12 This is a block diagram illustrating a memory card to which a memory system according to an embodiment of the present disclosure is applied;

[0024] Figure 13 It is a block diagram illustrating a solid-state drive (SSD) system to which a memory system according to an embodiment of the present disclosure is applied; and

[0025] Figure 14 This is a block diagram illustrating a user system to which a memory system according to an embodiment of the present disclosure is applied. Detailed Implementation

[0026] The specific structural or functional descriptions of examples of embodiments of the concept disclosed in this specification are merely illustrative for the purpose of describing examples of embodiments of the concept, and examples of embodiments of the concept may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0027] Figure 1 This is a block diagram illustrating a memory system 10 according to an embodiment of the present disclosure.

[0028] The memory system 10 can operate in response to a request from the host 20. More specifically, the memory system 10 can perform operations corresponding to a request received from the host 20. For example, when the memory system 10 receives data and a request from the host 20 instructing the storage of the data, the memory system 10 can store the data in the memory system 10. In another example, when the memory system 10 receives a request from the host 20 instructing the retrieval of data, the memory system 10 can provide the host 20 with the data stored in the memory system 10. The memory system 10 can be coupled to the host 20 via various communication methods.

[0029] The memory system 10 can be implemented as one of various types of storage devices depending on the communication standard or data storage scheme. For example, the memory system 10 can be implemented as any of the following storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro-MMC storage device, secure digital (SD), mini-SD or micro-SD storage device, universal serial bus (USB) storage device, universal flash memory (UFS) device, PCMCIA storage device, peripheral component interconnect (PCI) storage device, PCI Express (PCI-E) storage device, network attached storage device (NAS), and wireless network storage device. However, these are merely examples and this disclosure is not limited thereto. The memory system 10 can be implemented as a variety of other types of storage devices.

[0030] The host 20 can be one of various electronic devices, such as a desktop computer, laptop computer, mobile phone, smartphone, game console, and wearable device. The host 20 can request the memory system 10 to store, retrieve, or delete data via communication according to various communication protocols.

[0031] The memory system 10 can serve as the main memory device or auxiliary memory device of the host 20. The memory system 10 can be located inside or outside the host 20.

[0032] The memory system 10 may include a memory device 100 and a memory controller 200. One or more memory devices 100 may be present. The memory device 100 and the memory controller 200 may be coupled to each other through a channel through which commands, addresses, or data are exchanged.

[0033] Memory device 100 can store data. Memory device 100 can be implemented as various types of semiconductor memory devices. Examples of memory used by memory device 100 may include: NAND flash memory, vertical NAND flash memory, NOR flash memory, static random access memory (SRAM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics dynamic random access memory (GDRAM), Rambus dynamic random access memory (RDRAM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), phase-change memory (PCM), spin-transfer torque magnetoresistive RAM (STT-RAM), and resistive RAM (ReRAM). In the following, for ease of illustration, it is assumed that memory device 100 is a NAND flash memory device using NAND flash memory.

[0034] Memory device 100 may include multiple memory blocks. Each memory block may include multiple pages. Each page may include multiple memory cells. Memory cells may store data in units of bits. For example, the threshold voltage of a memory cell may vary depending on the amount of charge stored therein. The threshold voltage of a memory cell may indicate the bit value of the data stored in the memory cell. A page may include memory cells on which programming operations for storing data or read operations for retrieving stored data are performed. A memory block may include memory cells on which erase operations for erasing data are performed.

[0035] The memory controller 200 can control the regular operation of the memory device 100. For example, the memory controller 200 can control the memory device 100 to perform programming operations for storing data, reading operations for requesting stored data, or erasing operations for erasing stored data.

[0036] For example, for programming operations, memory controller 200 can provide programming commands, addresses, and data to memory device 100. The address can refer to a physical address. When memory device 100 receives programming commands, addresses, and data from memory controller 200, memory device 100 can perform a programming operation to store data in the page determined by the address. For read operations, memory controller 200 can provide read commands and addresses to memory device 100. When memory device 100 receives read commands and addresses from memory controller 200, memory device 100 can perform a read operation to provide the data stored in the page determined by the address to memory controller 200. For erase operations, memory controller 200 can provide erase commands and addresses to memory device 100. When memory device 100 receives erase commands and addresses from memory controller 200, memory device 100 can perform an erase operation to erase the data stored in the memory block determined by the address.

[0037] According to one embodiment, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to a request received from the host 20. For example, when the memory controller 200 receives a request from the host 20 to store, read, or erase data, the memory controller 200 can generate a command corresponding to the received request. However, the memory controller 200 can also receive commands directly from the host 20. Additionally, when the memory controller 200 receives a logical address from the host 20, the memory controller 200 can translate the logical address into a physical address of a memory block or page included in the memory device 100. The memory controller 200 can then transmit the physical address along with the command to the memory device 100. Hereinafter, the physical address will be simply referred to as an "address".

[0038] According to another embodiment, regardless of the request from host 20, memory controller 200 can control memory device 100 to perform programming, reading, or erasing operations. For example, memory controller 200 can control memory device 100 to perform wear leveling, read recycling, or garbage collection. Therefore, memory controller 200 can generate commands, addresses, and data and transmit them to memory device 100.

[0039] During programming operations, the memory device 100 may apply a programming voltage such that the threshold voltage of the memory cell reaches a target level corresponding to the data to be stored. The target level may be a verification level among verification voltages used to verify the programming state corresponding to the data to be stored. However, the threshold voltage of the memory cell may be programmed to be lower than the target level. As a result, there may be memory cells with threshold voltages lower than the target level. Memory cells with threshold voltages lower than the target level may be referred to as underprogrammed memory cells. When underprogrammed memory cells exist in the memory device 100, erroneous data may be output or errors may occur during read operations. More specifically, the higher the target level, the more frequently underprogramming may occur.

[0040] According to one embodiment of this disclosure, a memory device 100 for preventing the generation of underprogrammed memory cells, a memory system 10 including the memory device 100, and a method of operating the same can be provided. A more detailed description will follow with reference to the accompanying drawings.

[0041] Figure 2 This is a diagram illustrating the structure of a memory device 100 according to an embodiment of the present disclosure.

[0042] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0043] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have the same structure. In the following description, for ease of explanation, one of the multiple memory blocks BLK1 to BLKz (BLKz) will be described.

[0044] A memory block BLKz can include multiple pages. Each page can include multiple memory cells. In other words, a memory block BLKz can include multiple memory cells.

[0045] Multiple memory cells can be arranged in a two-dimensional plane or can have a three-dimensional vertical structure. Each memory cell can be a semiconductor memory device. According to one embodiment, the memory cell can be a non-volatile memory device. The threshold voltage of the memory cell can belong to one of a plurality of programming states. The programming states can indicate a voltage range (or segment), and a specific value of data can be mapped to a programming state according to a data storage scheme or Gray code. The number of programming states can vary depending on the data storage scheme. For example, a memory cell can store data according to various data storage schemes, including a single-level cell (SLC) storage scheme for storing 1 bit of data, a multi-level cell (MLC) storage scheme for storing 2 bits of data, a three-level cell (TLC) storage scheme for storing 3 bits of data, and a four-level cell (QLC) storage scheme for storing 4 bits of data.

[0046] The memory block BLKz can be coupled to the address decoder 121 of the peripheral circuitry 120 via row lines RL. Row lines RL can include multiple word lines. A page in the memory block BLKz can be coupled to one word line. In other words, the memory cells included in a page of the memory block BLKz can be coupled to one word line. Each page included in the memory block BLKz can be coupled to bit lines BL1 to BLm. Bit lines BL1 to BLm can be coupled to page buffers PB1 to PBm of the peripheral circuitry 120, respectively. (Refer to...) Figure 3 To describe the structure of memory block BLKz in more detail.

[0047] The peripheral circuitry 120 can operate in response to the control logic 130. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming, reading, or erasing operations.

[0048] Programming operations can be performed using an incremental step pulse programming (ISPP) method in which the programming voltage is gradually increased. More specifically, the peripheral circuit 120 can execute a programming cycle that includes programming pulse operations and verification operations. The programming pulse operations and verification operations can be performed sequentially. Based on the result of the verification operation, the peripheral circuit 120 can either execute the next programming cycle or terminate the operation after the programming voltage level is increased.

[0049] A programming pulse operation can refer to the operation of adjusting the threshold voltage of a memory cell included in a selected page so that the memory cell can have a predetermined programming state. A verification operation can be performed to verify whether the programming pulse operation passed or failed. For example, a successful programming pulse operation may mean that the threshold voltage of the memory cell included in the selected page is greater than or equal to a target level, while a failed programming pulse operation may mean that at least one threshold voltage of the memory cell included in the selected page is lower than the target level.

[0050] For example, a programming pulse operation may include applying a programming voltage to a selected page or a selected word line. Additionally, the programming pulse operation may include applying a programming pass voltage to an unselected page or an unselected word line simultaneously with the programming voltage applied to the selected page or word line. The programming voltage may be applied to increase the threshold voltage of the memory cell. The programming pass voltage may be applied to create a path for current to flow therein. The programming voltage may have a higher voltage level than the programming pass voltage.

[0051] For example, a verification operation may include applying a verification voltage to a selected page or a selected word line. Additionally, the verification operation may include applying a verification pass voltage to an unselected page or an unselected word line simultaneously with the verification voltage applied to the selected page or selected word line. The verification voltage may be applied to determine whether a programming pulse operation (or programming operation) passes or fails. The verification pass voltage may be applied to create a path for current to flow therein. The verification voltage may have a lower voltage level than the verification pass voltage.

[0052] Among multiple word lines, the selected word line can be determined by an address, and among multiple pages, the selected page can be coupled to the selected word line. The address can include at least one of a block address and a page address. Additionally, an unselected word line can refer to the remaining word lines among the multiple word lines coupled to the memory block coupled to the selected word line, excluding the selected word line, and an unselected page can refer to the page coupled to the unselected word line among the multiple pages included in the memory block coupled to the selected word line.

[0053] According to one embodiment, the peripheral circuitry 120 may include an address decoder 121, a voltage generator 122, a read and write circuitry 123, a data input / output circuitry 124, and a sensing circuitry 125.

[0054] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. For example, refer to Figure 2 and Figure 3The row line RL may include a drain select line DSL, multiple word lines WL1 to WL16, a source select line SSL, and a source line SL. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0055] Address decoder 121 can operate in response to control of control logic 130. For example, address decoder 121 can receive address ADDR from control logic 130. Address decoder 121 can decode the block address or page address included in the received address ADDR. The page address can indicate a row address. Address decoder 121 can apply an operating voltage Vop provided from voltage generator 122 to a selected memory block BLK1 to BLKz determined by the block address. Address decoder 121 can apply an operating voltage Vop provided from voltage generator 122 to a selected page determined by the page address among the pages included in the selected memory block determined by the block address. The operating voltage Vop can include at least one of the following: programming voltage, verification voltage, programming pass voltage, verification pass voltage, read voltage, read pass voltage, and first and second erase voltages.

[0056] According to one embodiment, during a programming pulse operation, the address decoder 121 may apply a programming voltage to a selected page (or selected word line) defined by a page address within a selected memory block (or a word line coupled to the selected memory block) defined by a block address, and may apply a programming pass voltage to an unselected page (or unselected word line). The programming voltage may have a higher voltage level than the programming pass voltage. During a programming verification operation, the address decoder 121 may apply a verification voltage to a selected page (or selected word line) defined by a page address within a selected memory block (or a word line coupled to the selected memory block) defined by a block address, and may apply a verification pass voltage to an unselected page (or unselected word line). The verification voltage may have a lower voltage level than the verification pass voltage.

[0057] According to one embodiment, during a read operation, the address decoder 121 may apply a read voltage to a selected page (or selected word line) within a selected memory block defined by a block address, and may apply a read pass voltage to an unselected page (or unselected word line). The read voltage may have a voltage level lower than the read pass voltage. In another example, during an erase operation, the address decoder 121 may apply a first erase voltage to a word line coupled to a selected memory block, and may apply a second erase voltage having a voltage level higher than the first erase voltage to a substrate in which memory cells within the selected memory block are stacked.

[0058] Voltage generator 122 can generate various types of operating voltages Vop using external power supplied to memory device 100. The external power can be an auxiliary power supply included in memory system 10, or it can be power supplied from host 20. For example, voltage generator 122 can generate programming voltage, verification voltage, programming pass voltage, verification pass voltage, read voltage, read pass voltage, and first and second erase voltages using the external power supplied to memory device 100.

[0059] Voltage generator 122 can operate in response to control of control logic 130. For example, when voltage generator 122 receives operation signal OPSIG from control logic 130, voltage generator 122 can transmit the operation voltage Vop corresponding to operation signal OPSIG to address decoder 121.

[0060] The read and write circuitry 123 may include multiple page buffers PB1 to PBm. These page buffers PB1 to PBm may be coupled to the memory cell array 110 via their respective corresponding bit lines BL1 to BLm. For example, each page buffer PB1 to PBm may be commonly coupled via a bit line to a memory cell indicating a predetermined column within each of the multiple memory blocks BLK1 to BLKz. Each page buffer PB1 to PBm may temporarily store data DATA. Each page buffer PB1 to PBm may be implemented as various types of memory devices, such as latching circuitry.

[0061] The read and write circuit 123 can operate in response to the control of the control logic 130. For example, when the read and write circuit 123 receives the buffer control signal PBSIGNALS from the control logic 130, the read and write circuit 123 can apply a voltage corresponding to the data DATA to the memory cell array 110 through multiple bit lines BL1 to BLm, or can read the data DATA stored in the memory cell array 110 through multiple bit lines BL1 to BLm.

[0062] Data input / output circuit 124 can be coupled to read and write circuit 123 via data line DL. Data input / output circuit 124 may include multiple input / output buffers that receive input data DATA. Data input / output circuit 124 can operate in response to control of control logic 130. For example, when data input / output circuit 124 receives a control signal from control logic 130, data input / output circuit 124 can transmit data DATA to read and write circuit 123 via data line DL, or output data DATA to memory controller 200 via a channel.

[0063] Sensing circuit 125 can generate a reference voltage in response to the enable bit VRYBIT signal received from control logic 130. As a result of comparing the reference voltage with the sensed voltage VPB received from read and write circuit 123, sensing circuit 125 can output a pass signal PASS or a failure signal FAIL. The pass signal PASS indicates that a programming pulse operation or read operation has passed. The failure signal FAIL indicates that a programming pulse operation or read operation has failed.

[0064] According to one embodiment, during a programming pulse operation, a data input / output circuit 124 can receive data DATA to be stored in a selected page from a memory controller 200. The data input / output circuit 124 can transfer the data DATA to a plurality of page buffers PB1 to PBm included in the read and write circuit 123. Each page buffer PB1 to PBm can receive data DATA from the data input / output circuit 124. Each page buffer PB1 to PBm can temporarily store the received data DATA. Additionally, when a programming voltage is applied to the selected page and a programming pass voltage is applied to an unselected page, each page buffer PB1 to PBm can apply a voltage corresponding to the data DATA to a bit line coupled to one of the plurality of bit lines BL1 to BLm.

[0065] During the verification operation, when a verification voltage is applied to the selected page and a verification pass voltage is applied to the unselected page, multiple page buffers PB1 to PBm can sense the voltage or current in multiple bit lines BL1 to BLm. Multiple page buffers PB1 to PBm can store sensing data corresponding to the sensed voltage or current. Multiple page buffers PB1 to PBm can transmit the sensed voltage VPB corresponding to the sensed data to sensing circuit 125. Sensing circuit 125 can output a pass signal PASS or a failure signal FAIL. When control logic 130 receives the pass signal PASS from sensing circuit 125, control logic 130 can output the pass signal PASS to memory controller 200. Additionally, when control logic 130 receives the pass signal PASS from sensing circuit 125, control logic 130 can control read and write circuit 123 to erase the data DATA stored in each of the page buffers PB1 to PBm. On the other hand, when the control logic 130 receives a failure signal FAIL from the sensing circuit 125, the control logic 130 can control the peripheral circuit 120 to execute the next programming pulse operation by increasing the level of the programming voltage.

[0066] According to one embodiment, during a read operation, when a read voltage is applied to the selected page and a read pass voltage is applied to the unselected page, multiple page buffers PB1 to PBm can sense voltage or current in multiple bit lines BL1 to BLm. The multiple page buffers PB1 to PBm can store data DATA corresponding to the sensed voltage or current. Data DATA can refer to the data DATA stored in the selected page. The multiple page buffers PB1 to PBm can transmit data DATA to a data input / output circuit 124 via a data line DL. The data input / output circuit 124 can receive data DATA from the multiple page buffers PB1 to PBm via the data line DL. The data input / output circuit 124 can output data DATA to a memory controller 200.

[0067] Control logic 130 can control the general operation of memory device 100. Control logic 130 can be implemented as hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry that operates according to an algorithm and / or executes control logic code. Control logic 130 can control peripheral circuitry 120 to perform programming, reading, or erasing operations based on commands CMD and addresses ADDR received from memory controller 200. Command CMD can be a programming command, a reading command, or an erasing command. Control logic 130 can be coupled to peripheral circuitry 120. For example, peripheral circuitry 130 may include address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125.

[0068] According to one embodiment, control logic 130 can provide peripheral circuitry 120 with various signals corresponding to commands CMD and addresses ADDR received from memory controller 200. Command CMD can be a programming command, a read command, or an erase command. For example, control logic 130 can generate an operation signal OPSIG, a buffer control signal PBSIGNALS, and an enable bit VRYBIT. Control logic 130 can output the operation signal OPSIG to voltage generator 122, the address ADDR to address decoder 121, the buffer control signal PBSIGNALS to read and write circuitry 123, and the enable bit VRYBIT to sensing circuitry 125. Additionally, control logic 130 can determine whether the operation is successful or unsuccessful based on a pass signal PASS or a failure signal FAIL received from sensing circuitry 125.

[0069] According to one embodiment, when control logic 130 receives a programming command and address, control logic 130 can control peripheral circuit 120 to perform a programming operation. The programming operation can be performed using the ISPP method, which gradually increases the programming voltage.

[0070] More specifically, when control logic 130 receives a programming command and address, control logic 130 can control peripheral circuit 120 to execute a programming loop that includes programming pulse operations and verification operations. The programming pulse operations and verification operations can be executed sequentially. For example, the verification operation can be performed after the programming pulse operation.

[0071] As a result of the verification operation, control logic 130 can control peripheral circuit 120 to execute the next programming cycle in which the programming voltage level is executed, or it can terminate the operation. More specifically, control logic 130 can receive a failure signal FAIL or a pass signal PASS from the sensing circuit 125 of peripheral circuit 120 according to the verification operation.

[0072] According to one embodiment, when control logic 130 receives a failure signal FAIL indicating that a programming pulse operation has failed, control logic 130 can control peripheral circuitry 120 to execute the next programming cycle. The next programming cycle may include programming pulse operations and verification operations executed sequentially. The programming voltage level for the programming pulse operations included in the next programming cycle may be increased to be greater than or equal to the programming voltage level in the previous programming cycle. Additionally, the verification pass voltage level for the verification operation included in the next programming cycle may be maintained or increased.

[0073] According to one embodiment, when control logic 130 receives a pass signal PASS indicating that the programming pulse operation has been completed, control logic 130 can terminate the programming operation.

[0074] The control logic 130 may include an operation controller 131 and a voltage register 133.

[0075] The operation controller 131 can control the peripheral circuit 120 to perform programming, reading or erasing operations according to the command CMD and the address ADDR.

[0076] During programming, the operation controller 131 can control the peripheral circuit 120 to execute a programming cycle that includes programming pulse operations and verification operations. The operation controller 131 can control the peripheral circuit 120 to repeat the next programming cycle until the operation controller 131 receives a pass signal (PASS) indicating that the programming pulse operation has passed. In other words, the operation controller 131 can control the peripheral circuit 120 to repeat the next programming cycle until the programming pulse operation passes.

[0077] More specifically, for example, as a result of the verification operation, the operation controller 131 can terminate the programming operation when it receives a pass signal (PASS), and can control the peripheral circuit 120 to execute the next programming cycle when it receives a failure signal (FAIL). When the peripheral circuit 120 executes the next programming cycle, the operation controller 131 can control the peripheral circuit 120 to terminate the programming operation when it receives a pass signal (PASS) and then execute the next programming cycle when it receives a failure signal (FAIL), based on the verification operation. As described above, whenever the operation controller 131 receives a failure signal (FAIL), the operation controller 131 can control the peripheral circuit 120 to execute the next programming cycle. The programming cycle can be repeated within a predetermined number of times.

[0078] Each time the next programming cycle is repeated, the operation controller 131 can increase the level of the programming voltage for the programming pulse operation. The operation controller 131 can control the peripheral circuit 120 to execute the programming pulse operation for the next programming cycle in which the programming voltage level increases. In other words, the programming voltage level can gradually increase as the number of programming cycles increases.

[0079] Even if the threshold voltage of a memory cell does not reach the target level (or target state) due to source line bouncing, it may be determined that the programming pulse operation has passed. For example, when the current or voltage of the source line changes due to source line bouncing, the threshold voltage of the memory cell may be determined to be at a different level. As a result, the reliability of the verification operation may deteriorate, and the reliability of the data may also deteriorate.

[0080] To prevent underprogramming, the operation controller 131 can increase the verification pass voltage level of the verification operation each time the next programming cycle is repeated. The operation controller 131 can control the peripheral circuit 120 to execute the verification operation of the next programming cycle in which the verification pass voltage level increases. In other words, the verification pass voltage level can gradually increase as the number of programming cycles increases.

[0081] According to one embodiment, when the threshold voltage of a memory cell included in a page coupled to the selected word line is greater than or equal to a reference level, the operation controller 131 may increase the level of the verification pass voltage applied to the unselected word line.

[0082] The reference level can be one of the predetermined verification levels among the verification voltages. The verification level of the verification voltage can be preset to verify the programming status of the memory cell to which the programming pulse operation is performed. The reference level and the verification level can be stored in the voltage register 133.

[0083] The reference level can be set as a verification level to distinguish between high and low programming states. Higher programming states may increase the likelihood of underprogramming. For programming cycles with high programming states, the verification pass voltage level can be gradually increased.

[0084] For example, when the data storage scheme corresponds to a multi-level cell, the reference level can be set to the verification level of the verification voltage used to verify the third programming state, which is the second highest among the first to fourth programming states. In another example, when the data storage scheme corresponds to a three-level cell, the reference level can be set to the verification level of the verification voltage used to verify the sixth programming state, which is the third highest among the first to eighth programming states. However, these are just examples, and the reference level can vary.

[0085] When the threshold voltage of the memory cell included in the page coupled to the selected word line is greater than or equal to the reference level, the operation controller 131 may increase the level of the verification pass voltage applied to one of the unselected word lines.

[0086] According to one embodiment, applying an increased level of verification pass voltage to at least one unselected word line may include at least one adjacent word line among a plurality of word lines located within a predetermined distance based on the position of the selected word line. The predetermined distance may be a value obtained by multiplying a predetermined number by an offset value. The offset value may be the distance between two adjacent word lines. The predetermined number may be a natural number of 1 or greater. For example, when the predetermined number is 1 and the Nth word line is selected, the operation controller 131 may increase the level of the verification pass voltage applied to each of the (N-1)th and (N+1)th word lines adjacent to the Nth word line. For example, when the predetermined number is 2 and the Nth word line is selected, the operation controller 131 may increase the level of the verification pass voltage applied to each of the (N-2)th, (N-1)th, (N+1)th, and (N+2)th word lines adjacent to the Nth word line. However, this is merely an example, and the predetermined number may vary.

[0087] According to one embodiment, at least one unselected word line to which an increased level of verification pass voltage is applied may be any of the remaining word lines other than the selected word line. When the threshold voltage of a memory cell included in a page coupled to the selected word line is greater than or equal to a reference level, the operation controller 131 may increase the level of the verification pass voltage applied to the remaining word lines other than the selected word line. For example, when a memory block includes 100 pages (or there are 100 word lines coupled to the pages), the operation controller 131 may increase the level of the verification pass voltage applied to each of the 99 word lines other than the selected word line.

[0088] According to one embodiment, when the threshold voltage of a memory cell included in a page coupled to the selected word line is less than a reference level, the operation controller 131 can maintain the level of the verification pass voltage. The operation controller 131 can control the peripheral circuitry 120 to perform a verification operation in the next programming cycle in which the level of the verification pass voltage is maintained. For programming cycles with a low programming state, the level of the verification pass voltage can be maintained.

[0089] According to one embodiment, the operation controller 131 can adjust the voltage increment based on the number of pages that have been programmed among a plurality of pages included in the memory block. The voltage increment can indicate the extent to which the level of the verification pass voltage applied to an unselected word line increases in the next programming cycle. When the threshold voltage of a memory cell included in a page coupled to a selected word line is greater than or equal to a reference level, the operation controller 131 can increase the level of the verification pass voltage by a voltage increment each time the next programming cycle is executed.

[0090] According to one embodiment, when the ratio of the number of programmed pages to the total number of pages is less than a reference value, the operation controller 131 can maintain the value of the voltage increase. In other words, when the ratio is less than the reference value, the operation controller 131 can apply a predetermined value as the value of the voltage increase. The ratio can refer to the degree to which programming operations are performed on a memory block. The reference value can refer to the basis for adjusting the value of the voltage increase based on the programming progress of a memory block. The reference value can be preset. For example, the reference value can be 0.7% or 70%. However, the reference value can vary.

[0091] According to one embodiment, when the ratio of the number of programmed pages to the total number of pages is greater than or equal to a reference value, the operation controller 131 can maintain the voltage increase value based on the difference between the ratio and the reference value. For example, when the ratio is greater than or equal to the reference value, the operation controller 131 can increase the voltage increase value proportionally to the difference between the ratio and the reference value.

[0092] According to one embodiment, when the ratio of the number of programmed pages to the total number of pages is less than a reference value, the operation controller 131 can adjust the voltage increase to a value obtained by multiplying the difference between the ratio and the reference value by a first gradient. Additionally, when the ratio of the number of programmed pages to the total number of pages is greater than or equal to the reference value, the operation controller 131 can adjust the voltage increase to a value obtained by multiplying the difference between the ratio and the reference value by a second gradient. The second gradient may have a larger value than the first gradient.

[0093] According to one embodiment, when the threshold voltage of a memory cell included in a page coupled to a selected word line is greater than or equal to a reference verification voltage having a level lower than the target verification voltage, the operation controller 131 may, each time the operation controller 131 executes a programming cycle, increase the level of the verification pass voltage applied to the word lines coupled to the programmed page in the unselected word lines by a first increment. Additionally, the operation controller 131 may increase the level of the verification pass voltage applied to the word lines coupled to the erased page in the unselected word lines by a second increment. The value of the second increment may be less than the value of the first increment. However, this is merely an example. The second increment may be changed to be greater than or equal to the value of the first increment.

[0094] According to one embodiment, the operation controller 131 can control the peripheral circuitry 120 to apply a programming voltage to an unselected word line during programming pulse operation.

[0095] Voltage register 133 can store voltage information. The voltage information may include information relating to the voltage levels used in each of the multiple programming cycles. According to one embodiment, the voltage information may include the levels of the programming voltage, verification voltage, and verification pass voltage for each of the multiple programming cycles. Additionally, the voltage information may also include the level of the programming pass voltage for each of the multiple programming cycles. The voltage information may be presented in tabular form. However, this is only one embodiment. The voltage information can be modified to various types of information.

[0096] According to the modification, at least one operation of each of the operation controller 131 and voltage register 133 can be performed by a separate configuration outside of control logic 130.

[0097] According to the above embodiments of this disclosure, the generation of underprogrammed memory cells can be prevented or avoided.

[0098] Figure 3 This is a diagram illustrating the structure of a memory block BLKz according to an embodiment of the present disclosure.

[0099] refer to Figure 3 The memory block BLKz can include multiple strings. Since multiple strings can have the same configuration, the string ST coupled to the first bit line BL1 will be described as an example.

[0100] One end of string ST can be coupled to a first bit line BL1, which is one of the bit lines BL1 to BLn. The other end of string ST can be coupled to a source line SL. In other words, a source line SL can be coupled to multiple strings, and a bit line can be coupled to a single string.

[0101] The string ST may include a source selection transistor SST coupled in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MCn, and a drain selection transistor DST. According to one embodiment, the string ST may include at least one source selection transistor SST, at least one drain selection transistor DST, and a... Figure 3 The memory cells shown are MC1 to MCn, which are multiple memory cells.

[0102] The gate of the source-select transistor SST can be coupled to the source-select line SSL, and the gate of the drain-select transistor DST can be coupled to the drain-select line DSL. The source of the source-select transistor SST can be coupled to the source line SL, and the drain of the drain-select transistor DST can be coupled to the first bit line BL1.

[0103] The gates of multiple memory cells MC1 to MCn can be coupled to multiple word lines WL1 to WLn respectively. Memory cells MC1 to MCn can be coupled in series between the source selection transistor SST and the drain selection transistor DST.

[0104] A memory block BLKz can include multiple pages. A page PG can be defined as a group of memory cells commonly coupled to the same word line. A page PG can be a group of memory cells corresponding to a unit used to perform a programming or read operation. A memory block BLKz can be a group of memory cells corresponding to a unit used to perform an erase operation.

[0105] A page PG can store page data. Page data can include data bits corresponding to the number of memory cells MC1 to MCn included in the page PG. For example, in a single-level cell scheme where one memory cell stores 1 bit of data, each of the multiple memory cells MC1 to MCn included in the page PG can store 1 bit of data. In other words, a page PG can store one page of data. In another example, in a multi-level cell scheme where one memory cell stores 2 bits of data, each of the multiple memory cells MC1 to MCn included in the page PG can store 2 bits of data. In other words, a page PG can store two pages of data. Similarly, in a three-level cell scheme where one memory cell stores 3 bits of data, a page PG can store three pages of data. In a four-level cell scheme where one memory cell stores 4 bits of data, a page PG can store four pages of data. In the following text, for ease of explanation, it can be assumed that the data storage scheme corresponds to a multi-level cell scheme.

[0106] Figures 4A to 4D This is a diagram illustrating the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure.

[0107] Figure 4A This is a diagram illustrating the threshold voltage of a memory cell to which an erase operation is performed.

[0108] refer to Figure 4A The erase state can refer to the zeroth programming state PV0 among a plurality of programming states. Each programming state can have a predetermined voltage range. According to one embodiment, the plurality of programming states can have voltage ranges distinguished based on verification levels VVRF1 to VVRF3. The voltage range of the erase state can be the smallest among the plurality of programming states. For example, the voltage range of the erase state can have a level smaller than the verification levels VVRF1 to VVRF3 of the verification voltage. Each of the plurality of programming states can indicate a predetermined value of data.

[0109] Figure 4AThe illustration shows three verification voltages. However, this is only one example. The number of verification voltages or programming states can vary depending on the memory cell storage scheme (such as single-level cell scheme, multi-level cell scheme, and three-level cell scheme).

[0110] Figure 4B and Figure 4C The diagram illustrates the threshold voltage of a memory cell to which programming operations are performed. (Reference) Figure 4B Programming operations can be performed based on a multi-level unit scheme. (See reference) Figure 4C The programming operations can be performed according to the three-level unit scheme.

[0111] According to one embodiment, for such Figure 4B The multi-level cell scheme shown includes multiple programming states, which may include a zero programming state PV0 to a third programming state PV3. The zero programming state PV0 may be an erase state. The threshold voltage of the memory cell included in the selected page can be adjusted by a programming operation, so that the memory cell can have one of the programming states PV0 to PV3 according to the page data.

[0112] According to one embodiment, according to as Figure 4C The three-level cell scheme shown includes multiple programming states, which may include programming states PV0 to PV7 (programming state 0). Programming state PV0 can be an erase state. The threshold voltage of the memory cell included in the selected page can be adjusted by programming operations, so that the memory cell can have one of the programming states PV0 to PV7 according to the page data.

[0113] The verification voltage used to verify multiple programming states can be adjusted to one of multiple levels.

[0114] According to one embodiment, according to as Figure 4B In the multi-level cell scheme shown, to verify the zeroth to third programming states PV0 to PV3, the verification voltage can be adjusted to one of the first to third verification levels VVRF1 to VVRF3. The programming state of the memory cell can be determined using a verification voltage with a predetermined verification level. For example, a memory cell with a threshold voltage smaller than the verification level applied to the word line coupled to the memory cell can be turned on, and a memory cell with a threshold voltage greater than or equal to the verification level can be turned off.

[0115] When the threshold voltage of the memory cell is less than the first verification level VVRF1, the memory cell may have a zero programming state PV0. When the threshold voltage of the memory cell is greater than or equal to the first verification level VVRF1 and less than the second verification level VVRF2, the memory cell may have a first programming state PV1. When the threshold voltage of the memory cell is greater than or equal to the second verification level VVRF2 and less than the third verification level VVRF3, the memory cell may have a second programming state PV2. When the threshold voltage of the memory cell is greater than or equal to the third verification level VVRF3, the memory cell may have a third programming state PV3. The values ​​of the first to third verification levels VVRF1 to VVRF3 may be larger in that order. Additionally, the programming states may be higher in the order from zero to third programming states PV0 to PV3.

[0116] According to one embodiment, according to as Figure 4C The three-level cell scheme shown allows the verification voltage to be adjusted to one of the verification levels VVRF1 to VVRF7 (from the first to the seventh verification levels) to verify the zeroth to seventh programming states PV0 to PV7. The programming states of the memory cells can be referenced above. Figure 4B A similar approach is described, using a verification voltage to determine this.

[0117] According to one embodiment, programming operations can be performed using an ISPP method in which the programming voltage is gradually increased. More specifically, the programming operation may include multiple programming cycles. Each programming cycle may include a programming pulse operation and a verification operation. The memory device 100 may repeat the next programming cycle until the programming pulse operation is determined to be passed. As the programming voltage is repeatedly applied to the selected word line, the threshold voltage of the memory cell coupled to the selected word line may gradually increase. In other words, the programming state of the memory cell may also gradually increase. For example, the memory device 100 may repeat the programming cycle such that each memory cell having a zero programming state PV0 can have a threshold voltage as shown in the image. Figure 4B The zeroth programming state PV0 to the third programming state PV3 shown.

[0118] Figure 4D This diagram illustrates the threshold voltage of a memory cell that has been programmed according to a multi-level cell scheme. (Reference) Figure 4D For example, it can be assumed that memory cells that are programmed using the first programming state PV1 and the second programming state PV2 as target programming states are programmed, while memory cells that are programmed using the third programming state PV3 as target programming state are underprogrammed.

[0119] More specifically, when a first memory cell 410 has a threshold voltage less than the third verification level VVRF3, a programming pulse operation may be determined to pass due to source line jumping caused by overcurrent being discharged to the common source line CSL. More specifically, this phenomenon may occur frequently in the high programming state during programming. The programming operation may terminate without executing the next programming cycle when the memory cell has an underprogrammed state PV3'. The memory cell with the underprogrammed state PV3' may include a first memory cell 410 having a threshold voltage less than the third verification level VVRF3 and a second memory cell 420 having a threshold voltage greater than or equal to the third verification level VVRF3. The first memory cell 410 may be simply referred to as the "slow cell," and the second memory cell 420 may be simply referred to as the "fast cell."

[0120] The minimum threshold voltage level of a memory cell having a first programming state PV1 can be greater than or equal to a first verification level VVRF1. A first read margin m1 can refer to the difference between the first verification level VVRF1 and the first read voltage VR1. The first read level VR1 can be a predetermined level for reading data corresponding to the first programming state PV1. The first read level VR1 can be less than the first verification level VVRF1.

[0121] The minimum threshold voltage level of a memory cell with a second programming state PV2 can be greater than or equal to the second verification level VVRF2. The second read margin m2 can refer to the difference between the second verification level VVRF2 and the second read level VR2 of the read voltage. The second read level VR2 can be a predetermined level for reading data corresponding to the second programming state PV2. The second read level VR2 can be less than the second verification level VVRF2.

[0122] The minimum threshold voltage level VU of a memory cell with an underprogrammed state PV3' can be less than the third verification level VVRF3. The third read margin m3 can refer to the difference between the minimum level VU and the third read level VR3 of the read voltage. The third read level VR3 can be a predetermined level for reading data corresponding to the third programming state PV3. The third read level VR3 can be less than the third verification level VVRF3.

[0123] The third read margin m3 of a memory cell whose threshold voltage distribution is abnormally controlled can have a lower value than the first read margin m1 and the second read margin m2 of a memory cell whose threshold voltage distribution is normally controlled. As the memory cell deteriorates over time or with an increase in the number of operations, the third read margin m3 can gradually decrease. Data reliability may be more easily degraded.

[0124] The above embodiments are based on a multi-level element scheme. However, this description also applies to three-level and four-level element schemes.

[0125] In this disclosure, the verification pass voltage applied to the unselected word line can be gradually increased during the verification operation to prevent an underprogrammed state.

[0126] Figure 5 This is a diagram illustrating selected and unselected word lines according to an embodiment of the present disclosure. Figure 5 The illustration shows a memory cell coupled to a bit line among the memory cells included in a memory block, but does not show memory cells coupled to other bit lines.

[0127] refer to Figure 5 Multiple word lines WL1 to WLz can be coupled to memory cells MC1 to MCz respectively, and memory cells MC1 to MCz are collectively coupled to a bit line BL. Each memory cell among the multiple memory cells MC1 to MCz can be included in each page. Each page can be coupled to the same word line and includes a memory cell coupled to another word line.

[0128] Programming operations can be performed sequentially on memory cells MC1 to MCz, which are respectively coupled to multiple word lines WL1 to WLz. For example, refer to... Figure 5 Programming operations can be sequentially performed on the first to (n-1)th memory cells MC1 to MCn-1 among the memory cells MC1 to MCz included in the memory block, which are coupled to the first to (n-1)th word lines WL1 to WLn-1. The nth to zth memory cells MCn to MCz among the memory cells MC1 to MCz included in the memory block, which are coupled to the nth to zth word lines WLn to WLz, can have a zero-programming state (i.e., an erase state).

[0129] Subsequently, the nth word line WLn can be selected by address among multiple word lines WL1 to WLz. For example, the selected word line Sel.WL can be the nth word line WLn. The selected page Sel.PG coupled to the selected word line Sel.WL can include the nth memory cell MCn. The unselected word line Unsel.WL can include the remaining word lines coupled to the memory block among the multiple word lines WL1 to WLz, excluding the selected word line Sel.WL. For example, the unselected word line Unsel.WL can include the first to (n-1)th word lines WL1 to WLn-1 and the (n+1)th to zth word lines WLn+1 to WLz.

[0130] When memory device 100 receives a programming command and an address, memory device 100 can execute a programming cycle that includes programming pulse operations and verification operations. It can be assumed that the address indicates the selected word line Sel.WL or the selected page Sel.PG.

[0131] More specifically, the memory device 100 can perform a programming pulse operation by applying a programming voltage to the selected word line Sel.WL and a programming pass voltage to the unselected word line Unsel.WL. Subsequently, the memory device 100 can perform a verification operation by applying a verification voltage to the selected word line Sel.WL and a verification pass voltage to the unselected word line Unsel.WL.

[0132] When a programming pulse operation fails via a verification operation, the memory device 100 may execute the next programming cycle, which includes both the programming pulse operation and the verification operation.

[0133] More specifically, the memory device 100 can increase the level of the programming voltage. The memory device 100 can perform a programming pulse operation that applies a programming voltage to the selected word line Sel.WL and applies a programming voltage to the unselected word line Unsel.WL. In other words, a programming voltage with an increased level can be applied to the selected word line Sel.WL.

[0134] Additionally, when the threshold voltage of a memory cell included in a selected page coupled to the selected word line Sel.WL is greater than or equal to a reference level, the memory device 100 may increase the level of the verification pass voltage applied to at least one of the unselected word lines Unsel.WL. For example, the reference level may be a predetermined verification level among verification voltages used to verify multiple programming states. The memory device 100 may perform a verification operation that applies a verification voltage to the selected word line Sel.WL and applies a verification pass voltage to the unselected word line Unsel.WL. In other words, during the verification operation, a verification pass voltage having the same level as before may be applied to the unselected word line Unsel.WL, or a verification pass voltage having an increased level than before may be applied to at least some of the unselected word lines Unsel.WL.

[0135] Associated with the verification operation, a verification pass voltage with an increased level can be applied to at least one of the unselected word lines in Unsel.WL.

[0136] According to one embodiment, at least one unselected word line to which a verification pass voltage with an increased level is applied may include at least one adjacent word line among a plurality of word lines WL1 to WLz coupled to a memory block, located within a predetermined distance based on the position of the selected word line Sel.WL. The predetermined distance may be a value obtained by multiplying a predetermined number by an offset value. The offset value may be the distance between two adjacent word lines. The predetermined number may be a natural number of 1 or greater. For example, when the predetermined number is 1, at least one unselected word line may include the (n-1)th word line WLn-1 and the (n+1)th word line WLn+1 closest to the nth word line WLn corresponding to the selected word line Sel.WL. More specifically, when the predetermined number is 1, the memory device 100 can determine the first adjacent page APG1 and the second adjacent page APG2 that are most adjacent to the selected page Sel.PG, which is the nth word line WLn coupled as the selected word line Sel.WL, and can determine the (n-1)th word line WLn-1 coupled to the first adjacent page APG1 and the (n+1)th word line WLn+1 coupled to the second adjacent page APG2 as at least one unselected word line.

[0137] Memory device 100 may apply a verification voltage to the selected word line Sel.WL during a verification operation. When memory device 100 applies a verification voltage to the selected word line Sel.WL, memory device 100 may also apply a verification pass voltage with an increased level to the (n-1)th word line WLn-1 and the (n+1)th word line WLn+1 of the unselected word lines Unsel.WL, and may apply a verification pass voltage with a maintained level.

[0138] According to one embodiment, at least one unselected word line to which an increased level of verification pass voltage is applied may be one of the remaining word lines among a plurality of word lines WL1 to WLz coupled to the memory block, excluding the nth word line WLn corresponding to the selected word line Sel.WL. In other words, at least one unselected word line may be the entirety of the unselected word lines Unsel.WL. The memory device 100 may increase the level of the verification pass voltage applied to the unselected word line Unsel.WL. During verification operation, the memory device 100 may apply an increased level of verification pass voltage to the unselected word line Unsel.WL, while the memory device 100 applies a verification voltage to the selected word line Sel.WL.

[0139] According to one embodiment, when the threshold voltage of a memory cell is greater than or equal to a reference level, the memory device 100 will apply an incremental change to the level of the verification pass voltage applied to the unselected word line Unsel.WL.

[0140] More specifically, memory device 100 may increase the level of the verification pass voltage applied to the unselected word line Unsel.WL, coupled to the word line of the programmed page, by a first increment. Additionally, memory device 100 may increase the level of the verification pass voltage applied to the unselected word line Unsel.WL, coupled to the erased page, by a second increment. The erased page may include a memory cell having a zero-programmed state PV0.

[0141] For example, refer to Figure 5 The level of the verification pass voltage applied to the first to (n-1)th word lines WL1 to WLn-1 can increase by a first increment, and the level of the verification pass voltage applied to the (n+1)th to (z)th word lines WLn+1 to WLz can increase by a second increment. The value of the second increment can be less than the value of the first increment. However, this is only an example. The second increment can have a value greater than the first increment.

[0142] The verification pass voltage with a first increase in level can be applied to some or all of the first to (n-1)th word lines WL1 to WLn-1. Additionally, the verification pass voltage with a second increase in level can be applied to some or all of the (n+1)th to zth word lines WLn+1 to WLz.

[0143] More specifically, for example, memory device 100 may apply a verification voltage with a level that increases by a first increment to the (n-1)th word line WLn-1 coupled to the first adjacent page APG1, the first adjacent page APG1 being the closest among the programmed pages to the selected page Sel.PG coupled to the nth word line WLn, the nth word line WLn being the selected word line Sel.WL. Memory device 100 may also apply a verification voltage with its level maintained to the remaining programmed pages other than the first adjacent page APG1.

[0144] In parallel, memory device 100 may apply a verification voltage with a level that increases by a second increment to the (n+1)th word line WLn+1 coupled to the second adjacent page APG2, the second adjacent page APG2 being the closest among the erased pages to the selected page Sel.PG coupled to the nth word line WLn, the nth word line WLn being the selected word line Sel.WL. Memory device 100 may also apply a verification voltage with a maintained level to the remaining erased pages excluding the second adjacent page APG2.

[0145] When the programming pulse operation passes the verification operation, the memory device 100 may terminate the programming operation.

[0146] The above embodiments are merely examples. The number of word lines included in at least one unselected word line to which a verification pass voltage with an increased level is applied, as well as the positional relationship between them, can vary.

[0147] Figure 6 This is a diagram illustrating a programming loop according to an embodiment of the present disclosure.

[0148] refer to Figure 6 The memory device 100 can sequentially execute multiple programming loops PL1, PL2, PL3, ..., PLn-1, PLn, PLn+1, ... according to a predetermined order, until the selected memory cell reaches the target state in the programming state. In the programming state, the target state can be determined based on the data to be stored.

[0149] Each of the multiple programming cycles PL1, PL2, PL3, ..., PLn-1, PLn, PLn+1, ... may include: a programming pulse operation PGM that applies a programming voltage to bring the memory cell to a target state, and a verification operation VERIFY that applies a verification voltage to determine whether the memory cell has reached the target state. Among the multiple programming states, the target state can be determined based on the data to be stored.

[0150] For example, a memory cell with a first programming state PV1 as the target state can be verified using a verification voltage with a first verification level VVRF1, a memory cell with a second programming state PV2 as the target state can be verified using a verification voltage with a second verification level VVRF2, and a memory cell with a third programming state PV3 as the target state can be verified using a verification voltage with a third verification level VVRF3. However, this is only an example, and multiple verification voltages can be applied for more accurate verification.

[0151] According to one embodiment, when the target state is the third programming state PV3, the memory device 100 can sequentially execute multiple programming loops PL1, PL2, PL3, ..., PLn-1, PLn, PLn+1, ... until the selected memory cell reaches the target state, i.e., the third programming state PV3. In other words, the memory device 100 can sequentially execute multiple programming loops PL1, PL2, PL3, ..., PLn-1, PLn, PLn+1, ... until the threshold voltage of the selected memory cell is greater than or equal to the third verification level VVRF3 corresponding to the target level. The target level can correspond to the target state. In the following description, the second verification level VVRF2 among the multiple verification levels VVRF1, VVRF2, and VVRF3 will be set as a reference level.

[0152] More specifically, the memory device 100 can sequentially execute the programming pulse operation PGM and the verification operation VERIFY included in the first programming cycle PL1.

[0153] To increase the threshold voltage of the selected memory cell, the programming pulse operation PGM of the first programming cycle PL1 can apply a programming voltage to the selected word line Sel.WL coupled to the selected memory cell, and can apply a programming pass voltage to the unselected word line Unsel.WL. The programming voltage can have a first programming level VPGM1. The programming pass voltage can have a programming pass level VPA.

[0154] The VERIFY operation of the first programming cycle PL1 can apply at least one verification voltage to the selected word line Sel.WL coupled to the selected memory cell, and can apply a verification pass voltage to the unselected word line Unsel.WL. The at least one verification voltage can include at least one of a voltage having a first verification level VVRF1, a voltage having a second verification level VVRF2, and a voltage having a third verification level VVRF3. The verification voltage can be determined by the programming state. The verification pass voltage can have a first verification pass level VPB1.

[0155] When the threshold voltage of the memory cell is greater than or equal to the third verification level VVRF3 of the verification voltage, the memory device 100 can determine that the programming pulse operation PGM has passed. When the threshold voltage of the memory cell is less than the third verification level VVRF3 of the verification voltage, the memory device 100 can determine that the programming pulse operation PGM has failed.

[0156] Additionally, the memory device 100 may repeatedly execute the next programming cycle, such as the second programming cycle PL2, the third programming cycle PL3, ..., until the programming pulse operation PGM is determined to have passed according to the verification operation VERIFY.

[0157] For example, when it is determined that the programming pulse operation PGM has failed based on the verification operation VERIFY, the memory device 100 may sequentially execute the programming pulse operation PGM and the verification operation VERIFY included in the second programming cycle PL2.

[0158] According to one embodiment, whenever the programming cycle is repeated, the memory device 100 can gradually increase the programming voltage level to, for example, a first programming level VPGM1, a second programming level VPGM2, a third programming level VPGM3, ..., a (n-1)th programming level VPGMn-1, an nth programming level VPGMn, and a (n+1)th programming level VPGMn+1.

[0159] According to one embodiment, whenever the programming cycle is repeated, the memory device 100 can maintain the programming pass voltage level at, for example, the programming pass level VPA.

[0160] According to one embodiment, when the next programming cycle is executed, the memory device 100 can perform a verification operation using at least one of a voltage having a first verification level VVRF1, a voltage having a second verification level VVRF2, and a voltage having a third verification level VVRF3.

[0161] For example, when a memory cell is determined to have a zero-programmed state PV0 through a verification operation, a verification voltage with a first verification level VVRF1 can be applied to the selected word line Sel.WL during the verification operation of the next programming cycle. Before or after applying the verification voltage with the first verification level VVRF1, at least one of a verification voltage with a second verification level VVRF2 and a verification voltage with a third verification level VVRF3 can be additionally applied to the selected word line Sel.WL.

[0162] In another example, when a memory cell is determined to have a first programming state PV1 through a verification operation, a verification voltage with a second verification level VVRF2 can be applied to the selected word line Sel.WL during the verification operation of the next programming cycle. Before or after the verification voltage with the second verification level VVRF2 is applied, at least one of a verification voltage with a first verification level VVRF1 and a verification voltage with a third verification level VVRF3 can be additionally applied to the selected word line Sel.WL.

[0163] In another example, when a memory cell is determined to have a second programming state PV2 through a verification operation, a verification voltage with a third verification level VVRF3 can be applied to the selected word line Sel.WL during the verification operation of the next programming cycle. Before or after the verification voltage with the third verification level VVRF3 is applied, at least one of a verification voltage with a first verification level VVRF1 and a verification voltage with a second verification level VVRF2 can be additionally applied to the selected word line Sel.WL.

[0164] According to one embodiment, when the threshold voltage of the selected memory cell is greater than or equal to a reference level, the memory device 100 can gradually increase the level of the verification pass voltage to, for example, the (n-1)th verification pass level VPBn-1, the nth verification pass level VPBn, the (n+1)th verification pass level VPBn+1, ... each time the next programming cycle is executed. In this way, the threshold voltage level of memory cells that are identified as higher than the actual level due to the reduction in sense current flowing in the string caused by source line switching can be compensated. For example, when the level of the verification pass voltage applied to the unselected word line Unsel.WL increases, the sense current can increase. As a result, the threshold voltage level of memory cells coupled to the selected word line Unsel.WL can be identified as a smaller value. The verification pass voltage with the increased level can be applied to some or all of the unselected word lines Unsel.WL.

[0165] According to one embodiment, when the next programming cycle is executed because the threshold voltage of the selected memory cell is less than a reference level, the memory device 100 can maintain the level of the verification pass voltage at, for example, a first verification pass level VPB1, a second verification pass level VPB2, a third verification pass level VPB3, ..., and a (n-1)th verification pass level VPBn-1. The first verification pass level VPB1, the second verification pass level VPB2, the third verification pass level VPB3, ..., and the (n-1)th verification pass level VPBn-1 can be the same level. Therefore, the level of the verification pass voltage can be selectively applied based on the programming state of the memory cell or the threshold voltage.

[0166] Figure 7 This is a diagram illustrating the verification of voltage changes according to an embodiment of the present disclosure. Figure 7 It is a graph showing the voltage over time or according to the verification cycle of the programming.

[0167] refer to Figure 7 The memory device 100 can sequentially execute multiple programming cycles until a programming operation or programming pulse operation passes. In the following, it can be assumed that, according to the verification operation of the (n-1)th programming cycle PLn-1, the threshold voltage of the memory cell is sensed to be a reference level or greater.

[0168] In the programming loop preceding the (n-1)th programming loop PLn-1, the memory device 100 can determine, based on a verification operation, that the threshold voltage of the memory cell coupled to the selected word line is less than a reference level and less than a target level. In the (n-1)th programming loop PLn-1, the memory device 100 can determine, based on a verification operation, that the threshold voltage of the memory cell coupled to the selected word line is greater than or equal to a reference level and less than a target level.

[0169] The memory device 100 can execute the nth programming cycle PLn after the (n-1)th programming cycle PLn-1. More specifically, the memory device 100 can increase the level of the verification pass voltage of the verification operation included in the nth programming cycle PLn by a voltage increase amount V_shift. During the execution of the programming cycle, the memory device 100 can linearly increase the level of the verification pass voltage. In other words, the memory device 100 can increase the level of the verification pass voltage based on a fixed value of the voltage increase amount V_shift. On the other hand, when executing the programming cycle, the memory device 100 can non-linearly increase the level of the verification pass voltage. In other words, the memory device 100 can increase the level of the verification pass voltage based on a change in the voltage increase amount V_shift. The value of the voltage increase amount V_shift can be preset and stored in the memory device 100.

[0170] According to one embodiment, in a programming loop segment where the threshold voltage of a memory cell is less than a reference level, the memory device 100 can maintain the level of the verification pass voltage. In another embodiment, in a programming loop segment where the threshold voltage of a memory cell is less than a reference level, as the programming loop executes, the memory device 100 can increase the level of the verification pass voltage by an increment lower than the voltage increase V_shift.

[0171] Figure 8A This is a diagram illustrating the verification of a condition under which the voltage is changed according to an embodiment of the present disclosure.

[0172] refer to Figure 8A According to one embodiment of this disclosure, the verification voltage level can be determined based on a comparison of a threshold voltage of the memory cell with a reference level or a comparison of the programming state of the memory cell with a reference programming state. The reference level or reference programming state can be predetermined according to the data storage scheme. For example, considering the frequency of underprogramming in each programming state of the memory cell, a reference programming state can be preset by performing a programming operation while the verification voltage level remains constant.

[0173] According to one embodiment, when the data storage scheme is a multi-level cell (MLC) scheme, the reference programming state can be set to the second programming state PV2 among multiple programming states PV0 to PV3. The reference level can be the verification level of the verification voltage used to verify the second programming state PV2, which serves as the reference programming state.

[0174] According to one embodiment, when the data storage scheme is a three-level cell (TLC) scheme, the reference programming state can be set to the fifth programming state PV5 among a plurality of programming states PV0 to PV7. The reference level can be the verification level of the verification voltage used to verify the fifth programming state PV5, which serves as the reference programming state.

[0175] However, the examples of the reference level or reference programming state described above are merely embodiments and various modifications can be made.

[0176] Figure 8B This is a diagram illustrating the change in the amount of increase in voltage during verification according to an embodiment of the present disclosure.

[0177] refer to Figure 8B In (1) and (2), memory device 100 can adjust the value of voltage increment V_shift based on the number of pages that have been programmed among the multiple pages included in the memory block. The number of pages that have been programmed among the multiple pages included in the memory block can indicate the programming progress of the memory block. Voltage increment V_shift can indicate the degree to which the verification pass voltage level increases. As the value of voltage increment V_shift increases, the difference between the verification pass voltage level in the previous programming cycle and the verification pass voltage level in the next programming cycle can increase.

[0178] When the threshold voltage of a memory cell coupled to the selected word line is greater than or equal to a reference level, the memory device 100 can increase the level of the verification pass voltage applied to the selected word line by a voltage increase amount V_shift. The sense current flowing in the string can vary according to the programming progress of the memory block. In other words, when the memory block is programmed to a degree greater than a predetermined degree, underprogramming can be effectively prevented by increasing the level of the verification pass voltage.

[0179] According to one embodiment, when the ratio of the number of programmed pages to the total number of pages is less than a reference value, the memory device 100 can maintain the value of the voltage increase V_shift. For example, the reference value can be a predetermined value, such as... Figure 8BThe 60% shown in (1) and (2) is just an example. However, this is only one example. The reference value can be set to a value different from 60%, or the voltage increase V_shift can increase linearly or non-linearly even when the ratio is less than the reference value.

[0180] According to one embodiment, when the ratio of the number of programmed pages to the total number of pages is greater than or equal to a reference value, the memory device 100 can adjust the value of the voltage increase V_shift based on the difference between the ratio and the reference value. For example, when the ratio is greater than... Figure 8B As shown in (1) and (2), at 60%, the value of the voltage increase V_shift can be adjusted to be proportional to the difference between the ratio and the reference value. However, this is only an example. The reference value can be set to a value different from 60%, or the voltage increase V_shift can be increased non-linearly.

[0181] More specifically, for example, it can be assumed that when a memory block comprises 100 pages (i.e., pages 1 to 100), ten pages (i.e., pages 1 to 10) are programmed, and the programming operation is performed on page 11, which corresponds to the selected page.

[0182] A second value, V_shift_2, corresponding to 10%, can be applied as the value of the voltage increment V_shift, where 10% is the ratio of the number of pages that have been programmed to the total number of pages. The memory device 100 can repeat the programming cycle until the threshold voltage of the memory cell included in the 11th page reaches a target level or higher. When the threshold voltage of the memory cell included in the 11th page is greater than or equal to a reference level, each time the memory device 100 executes the next programming cycle, the memory device 100 can increase the level of the verification pass voltage applied to the selected word line coupled to the 11th page by the second value V_shift_2 of the voltage increment V_shift.

[0183] In another example, it can be assumed that when the memory block comprises 100 pages (i.e., pages 1 to 100), 80 pages (i.e., pages 1 to 80) are programmed, and the programming operation is performed on page 81, which corresponds to the selected page.

[0184] Memory device 100 may use a ninth value V_shift_9 corresponding to 80% as the value of the voltage increment V_shift, where 80% is the ratio of the number of pages that have been programmed to the total number of pages. Memory device 100 may repeat the programming cycle until the threshold voltage of the memory cell included in page 81 reaches a target level or higher. When the threshold voltage of the memory cell included in page 81 is greater than or equal to a reference level, each time memory device 100 executes the next programming cycle, memory device 100 may increase the level of the verification pass voltage applied to the selected word line coupled to page 81 by the ninth value V_shift of the voltage increment V_shift.

[0185] According to one embodiment of this disclosure, a memory device 100 can be provided to prevent the generation of underprogrammed memory cells. Additionally, the reliability of the verification operation used to verify programming pulse operations can be improved.

[0186] Figure 9 This is a diagram illustrating the operation of a memory device 100 according to an embodiment of the present disclosure.

[0187] refer to Figure 9 The method of operating the memory device 100 may include: receiving a programming command at step S910; sequentially performing a programming pulse operation and a verification operation in a first programming cycle at step S920; and performing a programming pulse operation and a verification operation using an increased verification voltage during a second programming cycle at step S930.

[0188] More specifically, the memory device 100 may receive a programming command at step S910. The memory device 100 may receive an address along with the programming command. Additionally, the memory device 100 may receive data to be stored in a memory block.

[0189] According to one embodiment, the method of operating the memory device 100 may further include: storing information relating to the levels of programming voltage, verification voltage, and verification pass voltage for each of a plurality of cycles including first and second programming cycles.

[0190] Additionally, at step S920, the memory device 100 may sequentially perform a programming pulse operation and a verification operation in the first programming cycle. During the programming pulse operation, a programming voltage may be applied to a selected word line determined by an address among a plurality of word lines coupled to a plurality of pages included in the memory block. During the verification operation, a verification voltage corresponding to the programming voltage may be applied to the selected word line, and a verification pass voltage may be applied to an unselected word line.

[0191] According to one embodiment, the method of operating the memory device 100 may further include: applying a programming voltage to an unselected word line during a programming pulse operation.

[0192] According to one embodiment, the method of operating the memory device 100 may further include: during a first programming cycle, sensing a threshold voltage of a memory cell included in a page coupled to a selected word line based on a verification operation.

[0193] Additionally, at step S930, when the threshold voltage of the memory cell included in the page coupled to the selected word line is greater than or equal to the reference level and less than the target level which is greater than or equal to the reference level, the memory device 100 may sequentially perform a programming pulse operation using the increased programming voltage level and a verification operation using the increased verification pass voltage in the second programming cycle.

[0194] According to one embodiment, the method of operating the memory device 100 may further include: during a second programming cycle, sequentially performing a programming pulse operation using an increased programming voltage level and performing a verification operation using a held verification pass voltage level.

[0195] According to one embodiment, the method of operating the memory device 100 may further include adjusting the amount of increase in the verification pass voltage based on the number of programmed pages among a plurality of pages included in the memory block.

[0196] Adjusting the increase in voltage for verification can include: maintaining the increase at a constant value when the ratio of the number of programmed pages to the number of pages is less than a reference value; and adjusting the increase proportionally to the difference between the ratio and the reference value when the ratio is greater than or equal to the reference value.

[0197] According to one embodiment, the method of operating the memory device 100 may further include: when the threshold voltage of a memory cell included in a page coupled to a selected word line is greater than or equal to a reference level and less than a target level, during a third programming cycle, sequentially performing a programming pulse operation using an increased programming voltage level and performing a verification operation using an increased verification pass voltage level.

[0198] According to one embodiment, the method of operating the memory device 100 may further include: outputting a pass signal for a programming operation corresponding to a programming command when a threshold voltage of a memory cell included in a page coupled to a selected word line is greater than or equal to a target level. In other words, the programming operation can be terminated.

[0199] Figure 10 This is a detailed diagram illustrating the operation of a memory device 100 according to an embodiment of the present disclosure.

[0200] refer to Figure 10 At step S1010, memory device 100 may receive a programming command. Memory device 100 may receive an address along with the programming command. Additionally, memory device 100 may receive data to be stored in a memory block.

[0201] When the memory device 100 receives a programming command, it can perform the programming operation corresponding to the programming command. In other words, the memory device 100 can execute the m-th programming loop at step S1020. More specifically, at step S1021, the memory device 100 can apply a programming voltage to the selected word line determined by the address, and can apply a programming pass voltage to the unselected word lines in parallel. Subsequently, at step S1023, the memory device 100 can apply a verification voltage to the selected word line, and can apply a verification pass voltage to the unselected word lines in parallel.

[0202] The memory device 100 can terminate the programming operation when the programming operation has been completed (S1030, Yes). The memory device 100 can output a pass signal indicating that the programming operation has been completed.

[0203] In one embodiment, when the programming operation fails (S1030, No), the memory device 100 may use the (m+1)th programming cycle at step S1040 to increase the voltage level.

[0204] For example, when the programming operation fails (S1030, No), and if the threshold voltage of at least one memory cell coupled to the selected word line is greater than or equal to the reference level (S1041, Yes), then at step S1043, the memory device 100 may increase the level of the programming voltage and the level of the verification pass voltage applied during the (m+1)th programming cycle.

[0205] For example, when the programming operation fails (S1030, No), and if the threshold voltage of at least one memory cell coupled to the selected word line is less than the reference level (S1041, No), then at step S1045, the memory device 100 may increase the level of the programming voltage applied during the (m+1)th programming cycle.

[0206] Figure 11 This is a diagram illustrating the structure of a memory controller 200 according to an embodiment of the present disclosure.

[0207] refer to Figure 11 The memory controller 200 may include a host interface 210, a flash translation layer (FTL) 220, a processor 230, a memory interface 240, a buffer memory 250, and an error correction circuit 260.

[0208] Host interface 210 can communicate with host 20 according to various types of communication specifications. For example, host interface 210 can perform communication according to various types of communication specifications such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), and Universal Asynchronous Receiver / Transmitter (UART).

[0209] Host interface 210 can receive various requests from host 20. Examples of these requests may include: a read request instructing the storage of data, a read request instructing the output of stored data, and an erase request instructing the erasure of stored data. Host interface 210 can transmit the received requests to processor 230.

[0210] Host interface 210 can receive data and logical addresses from host 20. Additionally, host interface 210 can transfer the received data to buffer memory 250. Host interface 210 can transfer the received logical addresses to flash translation layer 220 or processor 230.

[0211] The flash translation layer 220 can store an address mapping table, which represents the mapping relationship between logical addresses and physical addresses. When the flash translation layer 220 receives a logical address from the host 20, it can transmit the physical address of the memory device 100 corresponding to the received logical address to the processor 230.

[0212] Processor 230 can control the routine operation of memory controller 200. When power is supplied to memory device 100, processor 230 can execute instructions. Instructions may be, for example, firmware (FW). Firmware (FW) may include a host interface layer (HIL) and a flash memory interface layer (FIL). The host interface layer can control communication between host 20 and host interface 210. In other words, the operation of host interface 210 can be controlled by the host interface layer (HIL). The flash memory interface layer can control communication between memory interface 240 and memory device 100. Processor 230 and flash memory translation layer 220 may be provided separately. However, this is only an example. The operation of flash memory translation layer 220 can be performed by processor 230.

[0213] The memory interface 240 can exchange commands, addresses, and data between the memory controller 200 and the memory device 100 via a channel. For example, the memory interface 240 can transmit commands and addresses output from the processor 230 and data output from the buffer memory 250 to the memory device 100 via a channel. The memory interface 240 can also transmit data received from the memory device 100 to the buffer memory 250 via a channel.

[0214] For example, memory interface 240 can transfer programming commands, addresses, and data stored in buffer memory 250 to memory device 100. Memory device 100 can store the data in pages of memory blocks corresponding to the addresses. In another example, memory interface 240 can transfer read commands and addresses to memory device 100. Memory interface 240 can receive data stored in pages of memory blocks corresponding to the addresses from memory device 100. In another example, memory interface 240 can transfer erase commands and addresses to memory device 100. Memory device 100 can erase the stored data from memory blocks corresponding to the addresses.

[0215] Buffer memory 250 can temporarily store data received from host 20. Data received from host 20 can be stored in memory device 100 in response to programming commands. For example, buffer memory 250 can store data received from host 20. After buffer memory 250 stores the received data in memory device 100, the data stored in buffer memory 250 can be erased. For example, when buffer memory 250 receives a pass signal from memory device 100 indicating that a programming operation has passed, buffer memory 250 can erase the data stored in buffer memory 250.

[0216] Buffer memory 250 may include static random access memory (static RAM) that retains stored information as long as power is supplied, or dynamic RAM (DRAM) that requires periodic refreshing to retain stored information. According to one embodiment, a region of buffer memory 250 may be configured as working memory or may be used as cache memory. According to one embodiment, firmware may be stored in a region of buffer memory 250. Firmware stored in buffer memory 250 may be driven by processor 230. However, this is only an example. Memory controller 200 may also include at least one of working memory, cache memory, and memory for storing firmware, provided separately from buffer memory 250.

[0217] Error correction circuit 260 can use error correction codes to perform an encoding operation to generate parity bits for data to be transferred to memory device 100. Error correction circuit 260 can perform the encoding operation for each block of data into which the data is divided. The data can have a size corresponding to a page, and the block data can have a size corresponding to a block. Parity bits can refer to codes used to detect or correct errors in the data. For example, parity bits can be inserted at the beginning or end of the data bits of the actual data. In another example, parity bits can be inserted at positions corresponding to powers of 2 (such as 1, 2, 4, 8, 16, ...), and the data bits of the actual data can be arranged in the remaining positions.

[0218] Error correction circuit 260 can perform a decoding operation to detect and correct erroneous bits in data read based on parity bits included in data read from memory device 100. For example, error correction circuit 260 can perform encoding or decoding operations based on coded modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), lattice-coded modulation (TCM), block-coded modulation (BCM), and Hamming codes. The decoding operation can be referred to as an error correction operation.

[0219] Error correction circuit 260 can use parity bits included in the data to detect error bits included in the data. For example, error correction circuit 260 can use various methods such as parity check, block check, and cyclic redundancy check (CRC) to detect error bits included in the data.

[0220] Error correction circuit 260 can correct error bits in the data when the number of error bits is less than a reference number. On the other hand, when the number of error bits in the data is greater than or equal to the reference number, error correction circuit 260 may not correct error bits in the data. The reference number can indicate the capability for error bit correction.

[0221] In the above embodiments, the levels of the programming voltage, verification voltage, and verification pass voltage can be controlled by the memory device 100. However, this is only an example. At least one of the levels of the programming voltage, verification voltage, and verification pass voltage can be controlled by the memory controller 200.

[0222] According to one embodiment, the memory controller 200 may include a voltage controller 270 and a voltage register 280.

[0223] The voltage controller 270 can adjust the level of the operating voltage of the memory device 100. For example, the voltage controller 270 can transmit a voltage control signal to the memory device 100 to adjust the level of the operating voltage of the memory device 100.

[0224] Voltage register 280 can store voltage information, including the programming voltage, verification voltage, and verification pass voltage levels for each of the multiple loops.

[0225] According to one embodiment, when processor 230 receives a programming command and an address, processor 230 can control memory device 100 to repeatedly execute a programming loop including programming pulse operations and verification operations. Processor 230 can receive programming commands and addresses from host 20. The address can be a logical address.

[0226] A programming pulse operation can refer to the operation of applying a programming voltage to a selected word line, determined by an address, and applying a programming pass voltage to an unselected word line. The selected word line can be determined by the physical address translated from the logical address. A verification operation can refer to the operation of applying a verification voltage to a selected word line and applying a verification pass voltage to an unselected word line.

[0227] Additionally, whenever a programming cycle is executed, the voltage controller 270 may increase the level of the programming voltage applied to the selected word line and the level of the verification pass voltage applied to the unselected word line until the voltage controller 270 receives a pass signal indicating that the programming pulse operation has passed.

[0228] Figure 12 This is a block diagram illustrating a memory card 2000 to which a memory system according to an embodiment of the present disclosure is applied.

[0229] refer to Figure 12 The memory card 2000 may include a memory device 2100, a memory controller 2200, and a connector 2300.

[0230] Memory device 2100 can perform programming operations to store data, reading operations to retrieve data, or erasing operations to erase data. For example, memory device 2100 may include various types of non-volatile memory, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM). Reference Figure 1 The description of memory device 100 can be applied to memory device 2100, and repeated descriptions thereof will be omitted.

[0231] Memory controller 2200 can control memory device 2100. For example, memory controller 2200 can execute instructions for controlling memory device 2100. Memory controller 2200 can control memory device 2100 to perform programming operations, read operations, or erase operations. Memory controller 2200 can transfer data or commands through communication between memory device 2100 and the host. For example, memory controller 2200 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. (Reference) Figure 1 The description of memory controller 200 is applicable to memory controller 2200. Redundant descriptions thereof will be omitted.

[0232] The memory controller 2200 can communicate with external devices via connector 2300. The memory controller 2200 can communicate with external devices (e.g., a host) according to predetermined communication specifications. For example, the memory controller 2200 can be configured to communicate with external devices via any of a variety of communication specifications such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication specifications. The memory controller 2200 and memory device 2100 can be integrated into a single semiconductor device to form a memory card. For example, memory device 2100 and memory controller 2200 can be integrated into a single semiconductor device and formed into a memory card, such as PCMCIA, compact flash (CF) card, smart media card (SM or SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro or eMMC), SD card (SD, miniSD, microSD or SDHC), universal flash (UFS), etc.

[0233] Figure 13 This is a block diagram illustrating a solid-state system drive (SSD) system 3000 to which a memory system according to an embodiment of the present disclosure is applied.

[0234] refer to Figure 13The SSD system 3000 may include multiple non-volatile memory devices 3100_1 to 3100_n, an SSD controller 3200, a signal connector 3010, an auxiliary power supply 3030, and a buffer memory 3040.

[0235] The SSD system 3000 can communicate with the host 3300 via a signal connector 3010. The signal connector 3010 can be implemented as an interface according to various types of communication methods. For example, the signal connector 3010 can be one of various communication method interfaces, such as a Serial ATA (SATA) interface, a mini-SATA (mSATA) interface, a PCI Express (PCIe) interface, and an M.2 interface.

[0236] Multiple first non-volatile memory devices 3100_1 can be coupled to the SSD controller 3200 through a first channel CH1, multiple second non-volatile memory devices 3100_2 can be coupled to the SSD controller 3200 through a second channel CH2, and multiple nth non-volatile memory devices 3100_n can be coupled to the SSD controller 3200 through an nth channel CHn. Therefore, the SSD controller 3200 can perform parallel communication with the non-volatile memory devices through independent channels.

[0237] refer to Figure 1 The description of memory device 100 may apply to each of the plurality of memory devices 3100_1 to 3100_n. Redundant descriptions thereof will be omitted. Reference Figure 1 The description of memory controller 200 can be applied to SSD controller 3200.

[0238] The SSD system 3000 can receive external power from the host 3300 via power connector 3020. An auxiliary power supply 3030 can be coupled to the host 3300 via power connector 3020. The auxiliary power supply 3030 can receive power from the host 3300 and use that power to charge the SSD system 3000. The auxiliary power supply 3030 can supply power to the SSD system 3000 when power from the host 3300 is not being supplied correctly. According to one embodiment, the auxiliary power supply 3030 can be located inside or outside the SSD system 3000. For example, the auxiliary power supply 3030 can be located on the motherboard and provide auxiliary power to the SSD system 3000.

[0239] Buffer memory 3040 can operate as a buffer memory for SSD system 3000. For example, buffer memory 3040 can temporarily store data received from host 3300, or data received from multiple non-volatile memory devices 3100_1 to 3100_n, or it can temporarily store metadata (e.g., mapping tables) of non-volatile memory devices 3100_1 to 3100_n. Buffer memory 3040 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory devices such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0240] Figure 14 This is a block diagram illustrating a user system 4000 to which a memory system according to one embodiment is applied.

[0241] refer to Figure 14 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0242] Application processor 4100 can run on components included in user system 4000, operating system (OS), or user programs. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0243] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory (RAM) (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM) or non-volatile RAM (such as PRAM, ReRAM, MRAM, and FRAM). For example, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and can then be provided as a single semiconductor package.

[0244] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0245] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory device using, for example, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. For example, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive for user system 4000.

[0246] According to one embodiment, reference Figure 1 The description of memory system 10 can be applied to memory module 4400. For example, memory module 4400 may include multiple non-volatile memory devices. (See reference...) Figure 1 The description of memory device 100 can be applied to each of a plurality of nonvolatile memory devices.

[0247] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. According to one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touchpad, touchscreen, touchball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0248] According to this disclosure, a memory device for preventing the generation of underprogrammed memory cells, a memory system including the memory device, and a method for operating the memory device can be provided. Additionally, the reliability of the verification operation used to verify the programming pulse operation can be improved.

Claims

1. A memory device, comprising: A memory block comprises multiple pages, each coupled to multiple word lines; The peripheral circuitry is configured to execute a programming cycle comprising: a programming pulse operation that applies a programming voltage to a selected word line corresponding to an address among the plurality of word lines; and a verification operation that applies at least one verification voltage corresponding to the programming voltage to the selected word line and applies a verification pass voltage to an unselected word line. as well as The control logic is configured as follows: The peripheral circuitry is controlled to repeatedly execute the next programming cycle, including the programming pulse operation and the verification operation, until a pass signal is received, indicating that the programming pulse operation has passed according to the verification operation. When the threshold voltage of a memory cell included in a page coupled to the selected word line is greater than a reference level, the level of the verification pass voltage applied to at least one of the unselected word lines is increased each time the peripheral circuit executes the next programming cycle, and The amount of increase in the verification pass voltage is adjusted based on the number of pages that have been programmed among the plurality of pages included in the memory block.

2. The memory device of claim 1, wherein the control logic is configured to: when the threshold voltage of the memory cell is less than the reference level, control the peripheral circuit to execute the next programming cycle in which the level of the verification pass voltage is maintained.

3. The memory device of claim 1, wherein the control logic is configured to: The voltage increase is adjusted based on the number of programmed pages among the plurality of pages included in the memory block; and When the threshold voltage of the memory cell is greater than the reference level, the level of the verification pass voltage is increased according to the value of the voltage increase amount whenever the peripheral circuit executes the next programming cycle.

4. The memory device of claim 3, wherein the control logic is configured to: When the ratio of the number of programmed pages to the total number of pages is less than a reference value, the voltage increase is maintained; and When the ratio is greater than the reference value, the voltage increase is adjusted based on the difference between the ratio and the reference value.

5. The memory device of claim 1, wherein the control logic is configured to: whenever the peripheral circuit executes the next programming cycle, when the threshold voltage of the memory cell is greater than the reference level: The verification pass voltage level applied to the at least one unselected word line coupled to the page that has been programmed is increased by a first increment; and The level of the verification pass voltage applied to the word line coupled to the erased page is increased by a second increment, the second increment being less than the first increment.

6. The memory device of claim 1, wherein the at least one unselected word line comprises at least one adjacent word line among the plurality of word lines within a predetermined distance based on the position of the selected word line.

7. The memory device of claim 1, wherein the at least one unselected word line comprises: The remaining word lines among the plurality of word lines, excluding the selected word line.

8. The memory device of claim 1, wherein the control logic includes a voltage register capable of storing verification voltage information, the verification voltage information including the level of the programming voltage for each of a plurality of programming cycles, the level of the verification voltage, and the level of the verification pass voltage.

9. The memory device of claim 1, wherein the control logic is configured to increase the level of the programming voltage whenever the peripheral circuit executes the next programming cycle, until the pass signal is received.

10. The memory device of claim 1, wherein the control logic is configured to control the peripheral circuitry to apply a programming voltage to the unselected word line during the programming pulse operation.

11. A memory system, comprising: A memory device comprising multiple pages, each coupled to multiple word lines; as well as The memory controller is configured as follows: When a programming command and address are received, the memory device is controlled to repeatedly execute a programming cycle including a programming pulse operation and a verification operation. The programming pulse operation includes applying a programming voltage to a selected word line corresponding to the address among the plurality of word lines, and applying a programming pass voltage to an unselected word line. The verification operation includes applying a verification voltage to the selected word line and applying a verification pass voltage to the unselected word line. Each time the memory device executes the programming cycle, the level of the programming voltage applied to the selected word line and the level of the verification pass voltage applied to the unselected word line are increased until a pass signal is received, the pass signal indicating that the programming pulse operation has passed according to the verification operation; and The amount of increase in the verification pass voltage is adjusted based on the number of pages that have been programmed among the plurality of pages.

12. A method of operating a memory device, the memory device comprising a memory block, the method comprising: Receive programming commands and addresses; During the first programming cycle, programming pulse operations and verification operations are performed sequentially. The programming pulse operation includes applying a programming voltage to a selected word line corresponding to the address among a plurality of word lines, the plurality of word lines being coupled to a plurality of pages included in the memory block. The verification operation includes applying a verification voltage corresponding to the programming voltage to the selected word line and applying a verification pass voltage to an unselected word line. When the threshold voltage of a memory cell included in a page coupled to the selected word line is greater than a reference level and less than a target level, the increase in the verification pass voltage is adjusted based on the number of fully programmed pages among the plurality of pages included in the memory block, the target level being higher than the reference level; and During the second programming cycle, the programming pulse operation in which the level of the programming voltage is increased and the verification operation in which the level of the verification pass voltage is increased are executed sequentially.

13. The method of claim 12, further comprising: When the threshold voltage of the memory cell is less than the reference level, during the second programming cycle, the programming pulse operation in which the level of the programming voltage is increased and the verification operation in which the level of the verification pass voltage is maintained are executed sequentially.

14. The method of claim 12, wherein adjusting the increase in the verification pass voltage comprises: When the ratio of the number of pages that have been programmed to the number of the plurality of pages is less than a reference value, the increase is kept constant. as well as When the ratio is greater than the reference value, the increase is adjusted proportionally to the difference between the ratio and the reference value.

15. The method of claim 12, further comprising: During the first programming cycle, the threshold voltage of the memory cell included in the page coupled to the selected word line is sensed according to the verification operation.

16. The method of claim 12, further comprising: When the threshold voltage of the memory cell included in the page coupled to the selected word line is greater than the reference level and less than the target level, during the third programming cycle, the programming pulse operation in which the level of the programming voltage is increased and the verification operation in which the level of the verification pass voltage is increased are executed sequentially.

17. The method of claim 12, further comprising: When the threshold voltage of the memory cell included in the page coupled to the selected word line is greater than the target level, a pass signal for the programming operation corresponding to the programming command is output.

18. The method of claim 12, further comprising storing voltage information, the voltage information including the level of the programming voltage, the level of the verification voltage, and the level of the verification pass voltage for each of a plurality of programming cycles including the first programming cycle and the second programming cycle.

19. The method of claim 12, further comprising: During the programming pulse operation, programming is applied by voltage to the unselected word line.

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