Bipolar transistor structure with emitter / collector contact to doped semiconductor well and related methods

Abstract

Embodiments of this disclosure provide a lateral bipolar transistor structure and related methods having an emitter / collector (E / C) contact to a doped semiconductor well. The bipolar transistor structure according to this disclosure may include a doped semiconductor well located above a semiconductor substrate. An insulating region is located on the doped semiconductor well. A base layer is located on the insulating region, and an emitter / collector (E / C) layer is located on the insulating region and adjacent to a first sidewall of the base layer. The E / C contact to the doped semiconductor well includes a lower portion adjacent to the insulating region and an upper portion adjacent to and electrically coupled to the E / C layer.

Description

Technical Field

[0001] This disclosure relates to bipolar transistors. Background Technology

[0002] This disclosure relates to bipolar transistors. Current technology represents an atomic-scale scaling of certain miniature devices such as logic gates, bipolar transistors, field-effect transistors (FETs), and capacitors. Circuit chips containing millions of such devices are common. The structure of a bipolar transistor defines several characteristics during operation. Conventional integrated circuits may employ vertical bipolar transistors or other types of bipolar transistors, but these types of devices may have higher costs and / or fail to meet certain required operating parameters. Various alternative configurations of bipolar transistors, particularly lateral bipolar transistors, provide sufficient electrical performance for a variety of operations, but at the expense of other physical characteristics. In some device or operating environments, certain bipolar transistor structures pose a risk of elevated operating temperatures. Summary of the Invention

[0003] The illustrative aspects of this disclosure are designed to address the problems described herein and / or other problems not discussed herein.

[0004] Embodiments of this disclosure provide a bipolar transistor structure comprising: a doped semiconductor well located above a semiconductor substrate; an insulating region located on the doped semiconductor well; a base layer located on the insulating region; an emitter / collector (E / C) layer located on the insulating region and adjacent to a first sidewall of the base layer; and an E / C contact to the doped semiconductor well, the E / C contact comprising a lower portion adjacent to the insulating region and an upper portion adjacent to and electrically coupled to the E / C layer.

[0005] Other embodiments of this disclosure provide a bipolar transistor structure comprising: a doped semiconductor well located above a semiconductor substrate; an insulating region located on the doped semiconductor well; a base layer located on the insulating region; a first emitter / collector (E / C) layer located on the insulating region and adjacent to a first sidewall of the base layer; a first E / C contact to the doped semiconductor well, the first E / C contact comprising a lower portion adjacent to the insulating region and an upper portion adjacent to and electrically coupled to the first E / C layer; a second E / C layer located on the insulating region and adjacent to a second sidewall of the base layer opposite to the first sidewall; and a second E / C contact to the second E / C layer, wherein the lower surface of the second E / C contact is located on the upper surface of the second E / C layer and above the insulating region.

[0006] Additional embodiments of this disclosure provide a method for forming a bipolar transistor structure, comprising: forming a doped semiconductor well over a semiconductor substrate; forming a base layer on an insulating layer over the doped semiconductor well; forming an emitter / collector (E / C) layer on the insulating region and adjacent to a first sidewall of the base layer; and forming an E / C contact to the doped semiconductor well, the E / C contact including a lower portion adjacent to the insulating region and an upper portion adjacent to and electrically coupled to the E / C layer. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the present disclosure in conjunction with the accompanying drawings depicting various embodiments thereof, wherein:

[0008] Figure 1 A cross-sectional view of the initial structure to be processed according to an embodiment of the present disclosure is provided.

[0009] Figure 2 A cross-sectional view of forming a first contact opening according to an embodiment of the present disclosure is provided.

[0010] Figure 3 A cross-sectional view of forming a second contact opening according to an embodiment of the present disclosure is provided.

[0011] Figure 4 A cross-sectional view of an emitter / collector (E / C) contact formed in a contact opening according to an embodiment of the present disclosure is provided.

[0012] Figure 5 A cross-sectional view of forming a base contact to form a bipolar transistor structure according to an embodiment of the present disclosure is provided.

[0013] Figure 6 Cross-sectional views of bipolar transistor structures according to other embodiments of the present disclosure are provided.

[0014] Figure 7 A plan view of a bipolar transistor structure according to an embodiment of the present disclosure is provided.

[0015] Please note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0016] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0017] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0018] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ", "and / or", and "at least one" in cases such as "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0019] Embodiments of this disclosure provide a bipolar junction transistor (BJT) structure in which an emitter / collector contact to the emitter or collector terminal of the transistor extends (e.g., through a buried insulating layer) to a doped semiconductor well located below the BJT structure. The doped semiconductor well may be located above a semiconductor substrate and may have an insulating region thereon. A base layer may be located on the insulating region, for example, such that the insulating region vertically separates the doped semiconductor well from the base layer. An E / C layer formed of a doped semiconductor material may also be located on the insulating region and adjacent to the sidewalls of the base layer. The BJT structure includes an E / C contact to the doped semiconductor well, i.e., the E / C contact may have a lower surface or sidewall in thermal communication with the doped semiconductor well. The lower portion of the E / C contact is adjacent to the insulating region, and the upper portion of the E / C contact is adjacent to and electrically coupled to the E / C layer.

[0020] Bipolar junction transistor (BJT) structures, such as those in the embodiments of this disclosure, operate using multiple "PN junctions." The term "PN" refers to two adjacent materials with different conductivity types (i.e., P-type and N-type), the conductivity type being induced by dopants within the adjacent materials. When formed in a device, a PN junction can function as a diode. A diode is a two-terminal device that behaves differently from the conductive or insulating materials between two electrical contacts. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the "forward" direction), but provides almost no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the orientation of the diode in the forward and reverse directions depends on the type and magnitude of the bias applied to the material composition of one or both terminals, which affects the size of the barrier. In the case of a junction between two semiconductor materials, the barrier will form along the interface between the two semiconductor materials.

[0021] refer to Figure 1 This document illustrates a preliminary structure 100 (hereinafter referred to as the "structure") suitable for forming a lateral bipolar transistor structure according to embodiments of the present disclosure. The preliminary structure 100 may be processed as described herein to produce one or more lateral bipolar transistor structures. However, it should be understood that in other embodiments, other techniques, process sequences, etc., may be implemented to produce the same or similar bipolar transistor structures. Figure 1A cross-sectional view of a structure 100 having a substrate 102 comprising, for example, one or more semiconductor materials is shown. The substrate 102 may include, but is not limited to, silicon, germanium, silicon germanium (SiGe), silicon carbide, or any other common IC semiconductor substrate. In the case of SiGe, the germanium concentration in the substrate 102 may differ from other SiGe-based structures described herein. A portion or all of the substrate 102 may be strained. For example, a doped semiconductor well 104 may be included on or within the substrate 102 to achieve electrical bias of a structure or component formed above the substrate 102. The doped semiconductor well 104 may have the same dopant type as the substrate 102 (e.g., p-type doping), but may have a higher doping concentration.

[0022] The preliminary structure 100 includes embedded elements for electrically isolating the active material formed thereon from other regions and / or materials on the substrate 102. An insulating region 106 may be formed over the substrate 102, for example, by forming one or more insulating materials on the doped semiconductor well via deposition and / or otherwise converting a pre-existing semiconductor material into an insulating material. The insulating region 106 may extend horizontally over the substrate 102 and the doped semiconductor well 104, and / or may be located below the site where the active material is formed, examples of which are discussed elsewhere herein. The insulating region 106 may include oxygen doping to form a dielectric insulator or buried oxide (“BOX”) layer over the substrate 102 and electrically isolate the overlying active semiconductor material. The insulating region 106 may include other elements or molecules, such as Ge, N, or Si.

[0023] The insulating region 106 may include, for example, a trench isolation region 106a and a buried insulating layer 106b adjacent to the trench isolation region 106a. The trench isolation region 106a may be included in an intermediate region horizontally located between different electroactive components and has a relatively large vertical thickness (e.g., at least about 600 nanometers (nm)) compared to other portions of the insulating region 106. The trench isolation region 106a may be embodied as or may include part of a trench isolation (TI) region for horizontally separating different regions of active material. The buried insulating layer 106b of the insulating region 106 may be as narrow as possible to provide better interaction with the overlying semiconductor material and may have a thickness of up to about 5 nm to about 500 nm in various embodiments. In some cases, multiple insulating regions 106 may be formed over the substrate 102 and / or regions with different vertical thicknesses may be formed. Each portion 106a, 106b of the insulating region 106 may be formed of any material currently known or later developed for providing electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon carbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof.

[0024] The initial structure 100 may include a base layer 110 located on a buried insulating layer 106b of an insulating region 106. The base layer 110 may include, for example, SiGe or any other semiconductor material doped to have a predetermined polarity. In the case where the doped semiconductor well 104 is n-type doped, the base layer 110 may be p-type doped to form a PN junction adjacent to the emitter / collector material as discussed herein. In other examples, the base layer 110 may be a stack of alternating components (e.g., alternating Si and SiGe layers), in which case the uppermost layer of the stack is highly doped to form the outer base region. It should also be understood that, in alternative embodiments, the base layer 110 may be n-type doped. However, the base layer 110 may extend to a predetermined height above the insulating region 106, and as discussed herein, the base layer 110 may be significantly higher than the adjacent emitter or collector material to be used within the bipolar structure. One or more spacers 112 may be adjacent to the base layer 110 to structurally and electrically separate the base layer from adjacent electroactive materials (e.g., emitter and collector layers and / or contacts formed thereto). The spacers 112 may comprise a nitride insulating material and / or any other insulating material discussed herein, such as with respect to buried insulating layer 106 or other insulating structures. For example, the spacers 112 may be formed by depositing a corresponding spacer material such that the spacer material covers any exposed surfaces and sidewalls S1, S2 of the base layer 110 before forming other materials over the substrate 102 and the adjacent base layer 110. In some implementations, the spacers 112 may comprise a single layer or two or more layers.

[0025] The preliminary structure 100 may further include a set of emitter / collector (E / C) layers 120 located on the buried insulating layer 106b. One E / C layer 120 may be adjacent to a first sidewall S1 of the base layer 110, while another E / C layer 120 may be adjacent to a second sidewall S2 of the base layer 110. The E / C layers 120 may define all or part of the active bipolar transistor material for the emitter and collector terminals of the bipolar transistor structure. The E / C layers 120 may be formed, for example, on the corresponding portions of the insulating region 106 by depositing and doping a doped semiconductor material. The E / C layers 120 may include the same material composition as the base layer 110 (e.g., doped SiGe), but with the opposite doping type (e.g., when the first base layer 110 is p-type doped, they may be n-type doped, and vice versa). The E / C layers 120 may additionally or alternatively include other electrically active semiconductor materials. The E / C layer 120 can be formed above the buried insulating layer 106b to a desired thickness. However, the height of the E / C layer 120 above the buried insulating layer 106b can be less than the height of the base layer 110 above the buried insulating layer 106b.

[0026] The preliminary structure 100 may include a set of raised emitter / collector (E / C) layers 122 located on the E / C layer 120. The raised E / C layers 122 may be formed by depositing and / or epitaxially growing silicon and / or other materials on the E / C layer 120, and may have the same doping type as the E / C layer 120. The raised E / C layer 122 may be formed, for example, by selectively growing silicon material on the upper surface of the E / C layer 120. However, the raised E / C layer 122 may have a higher dopant concentration than the underlying E / C layer 120. The higher doping concentration in the raised E / C layer 122 may increase the conductivity between the raised E / C layer 122 and any overlay contacts used to transfer current to the lateral bipolar transistor structure, and / or may facilitate silicide formation in subsequent processing. Since it is formed on the E / C layer 120, the raised E / C layer 122 can be horizontally adjacent to the spacer 112 to physically and electrically isolate the raised E / C layer 122 from the base layer 110.

[0027] The preliminary structure 100 may also include, for example, a gate structure 130 located on a trench isolation region 106a of the insulating region 106. In this configuration, the gate structure 130 may be horizontally disposed away from any material above the buried insulating layer 106b of the insulating region 106. That is, the gate structure 130 may be horizontally spaced apart from the base layer 110, E / C layer 120, raised E / C layer 122, etc., by a predetermined horizontal separation distance. The gate structure 130 may include any type of semiconductor material (e.g., those suitable for the substrate 102) and / or other types of materials that can be deposited on the insulating region 106 at selected locations. However, the gate structure 130 may be electrically inactive and therefore may be free of p-type or n-type dopants. The gate structure 130 may be formed by separate processes to form various gate structures for field-effect transistors and / or other electrically active components, but will not be converted into electrically active components in subsequent processing. For example, the gate structure 130 may remain electrically inactive by not being targeted as a metal gate replacement. However, as discussed elsewhere in this document, conductive contacts to the E / C layer 120 can be partially formed on the gate structure 130 in subsequent processing, and the gate structure 130 can act as a marker structure to facilitate the formation of conductive material when needed.

[0028] An insulating film 140 of the preliminary structure 100 may be formed on the exposed upper surfaces of the insulating region 106, the base layer 110, the raised E / C layer 122, and the gate structure 130. The insulating film 140 may be provided, for example by deposition, thermal growth, etc., as one or more insulating material bodies formed on the sidewalls of the exposed material to electrically and physically insulate the material subsequently formed on the coating material from other components. In some cases, portions of the insulating film 140 may form or define spacers 112, but in other implementations, the insulating film 140 may cover the spacers 112. The insulating film 140 may be formed, for example, by depositing a corresponding spacer material to cover any exposed surfaces and sidewalls of the underlying material in the preliminary structure 100. In some implementations, the insulating film 140 may comprise a single layer or two or more layers.

[0029] An interlayer dielectric (ILD) layer 142 may be located above the insulating film 140 and may be formed by deposition of an insulating material or other techniques. The ILD layer 142 may include the same insulating material as the insulating region 106 or may include a different electrical insulating material. After depositing the ILD layer 142, the ILD layer 142 may be planarized (e.g., using CMP) such that its upper surface is substantially coplanar and located above all underlying components of the preliminary structure 100. The preliminary structure 100 may include an insulating film 144 located on the ILD layer 142, for example, an additional layer of nitride and / or other insulating material different from the ILD layer 142. The insulating film 144 may structurally and electrically separate the preliminary structure into different layers, for example, to allow overlay metal wiring and vias to be formed over the insulating film 144 and the ILD layer 142 in subsequent processing. In the case of including the insulating film 144, an additional ILD layer 146 (including, for example, the same material as the ILD layer 142) may be formed over the insulating film 144.

[0030] Go to Figure 2 The method according to this disclosure may include forming a first opening 150 through ILD layers 142, 146, insulating film 144, insulating film 140 and further through insulating region 106 to expose a doped semiconductor well 104. The first opening 150 may be formed at a target location using a mask 152 to expose an additional ILD layer 146 and any material beneath it. The mask 152 may include any suitable mask material now known or developed later, such as a nitride hard mask. Figure 2As shown, any suitable etching process, such as reactive ion etching (RIE), removes layers 106, 140, 142, 144, 146 to expose the doped semiconductor well 104. The structure of the mask 152 can result in the upper surface and / or sidewalls of the doped semiconductor layer 104 being exposed within the first opening 150. The first opening 150 also exposes the E / C layer 120 and adjacent portions of the raised E / C layer 122 above it. The first opening 150 can also expose the upper portion and sidewalls of the gate structure 130 therein. In some cases, the gate structure 130 can be formed of a material detectable relative to the ILD layer 142, for example, for alignment and positioning of the mask 152. Therefore, the formation of the first opening 150 can be performed at any location where conductive material can be formed to couple to layers 120, 122.

[0031] Figure 2 A first silicide layer 154 is also shown formed within the first opening 150 on the E / C layer 120 and the raised E / C layer 122. The first silicide layer 154 can be formed to enhance conductivity between the raised E / C layer 122 and the conductor formed thereon. The first silicide layer 154 can be formed by forming a conductive metal (e.g., cobalt, titanium, nickel, platinum, or other materials) on the raised E / C layer 122, annealing the metal to produce a conductive silicide material (e.g., cobalt silicide, titanium silicide, etc.) on the exposed surface of the raised E / C layer 122, and removing excess conductive metal. The initially formed metal can optionally be coated onto the raised E / C layer 122, for example, to prevent the first silicide layer 154 from forming within the opening 150 on the doped semiconductor well 104 or on the E / C layer 120. The first E / C layer 122 can be formed to allow stronger electrical coupling to the overlying contact. It is understood that the silicide layer 154 can alternatively be formed in an earlier processing stage. For example, the first silicide layer 154 can be formed before the formation of the first opening 150, for example, during the formation of the preliminary structure 100, in the preliminary structure 100 ( Figure 1 It is formed inside.

[0032] Figure 3 The subsequent processing is shown, in which mask 152 ( Figure 2The first opening 150 is removed (e.g., by stripping or other mask removal techniques) and replaced with another mask 156 to cover the first opening 150, while exposing another portion of the additional ILD layer 146. The mask 156 may be a traverse layer of material that covers the first opening 150 (e.g., by material supported by the additional ILD layer 146), but in other implementations, the mask 156 may fill the first opening 150. Using the mask 156, a second opening 158 can be formed through layers 140, 142, 144, 146 to expose the raised E / C layer 122 beneath it. The second opening 158 may not extend through layers 120, 122, and therefore the doped semiconductor well 104 may not be exposed if thermal coupling to the doped semiconductor well 104 is not required. Therefore, the second opening 158 may not be as deep as the first opening 150. In an alternative implementation, the depth and shape of the second opening 158 can be similar to that of the first opening 150; therefore, the second opening 158 may optionally be formed simultaneously with the first opening 150 using a single mask. Following the second opening 158, a second silicide layer 160 can be formed on the raised E / C layer 122, for example, using the same process as that discussed herein for forming the first silicide layer 154 in the first opening 150. In other embodiments, the second silicide layer 160 may be formed prior to the formation of the second opening 158 on the preliminary structure 100 (…). Figure 1 It is formed inside.

[0033] Figure 4 The opening 150 is shown to be filled with a conductive material. Figure 2 , 3 ), 158 Figure 3 Mask 156 Figure 3The conductive material can be removed by stripping and / or other mask removal techniques, allowing conductive material to be deposited within each opening 150, 158. The first E / C contact 162 can be formed within the first opening 150, for example, by conformally depositing a refractory metal liner on the exposed surface of the first opening 150 and filling the remainder of the first opening 150 with conductors such as tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), etc., and non-metallic conductive materials (e.g., polycrystalline Si). The refractory metal liner of the first E / C contact 162 prevents electromigration degradation, short circuits to other components, etc. Due to the shape of the first opening 150, the first E / C contact 162 may include a lower portion 162a connected to the doped semiconductor well 104 (e.g., by being located on the upper surface of the doped semiconductor well 104 or adjacent to its sidewalls) and adjacent to the insulating region 106. The upper portion 162b of the first E / C contact 162 may be located on the lower portion 162a and coupled to the raised E / C layer 122, for example, through the first silicide layer 154. Alternatively, when the gate structure 130 is electrically inactive, the upper portion 162b of the first E / C contact 162 may be located on and adjacent to portions of the gate structure 130. The coupling of the first E / C contact 162 to the gate structure 130 also provides additional heat dissipation from the electrically active components to the gate structure 130. As part of the same deposition or in subsequent operations, a second (alternatively, "additional") E / C contact 164 may be formed within the second opening 158 to be electrically coupled to the second silicide layer 160. Due to the different dimensions of the openings 150 and 158, the maximum width W1 of the first E / C contact 162 may be greater than the maximum width W2 of the second E / C contact 164. With the second opening 152 ( Figure 3 In comparison, the larger width W1 of the first E / C contact 162 can result in, for example, an opening 150 ( Figure 2 , 3 The larger size of the doped semiconductor well 104 is used to place it on the doped semiconductor well 104.

[0034] Figure 5Further processes for forming base contact 166 and third silicide layer 168 as remaining components of bipolar transistor structure 170 according to embodiments of the present disclosure are illustrated. Base contact 166 can be formed in substantially the same manner as E / C contacts 162, 164, for example, by forming a mask over additional ILD layer 146 and contacts 162, 164, and removing portions of layers 140, 142, 144, 146 over base layer 110. The third silicide layer 168 can then be formed on the base layer in substantially the same manner as silicide layers 154, 160 or by any other currently known or later developed technique for forming silicides on semiconductor materials. A conductive material and a refractory metal liner are then formed over the third silicide layer 168 to create base contact 166. Thus, contacts 162, 164, 166 define conductive pathways to layers 110, 120, 122. In addition, the first E / C contact 162 may include a lower portion 162a that is thermally connected to the doped semiconductor well 104 (e.g., via a location on or adjacent to the doped semiconductor well 104).

[0035] Although the doped semiconductor well 104 does not contain any electroactive elements and / or coupling to them, the coupling from the first E / C contact 162 to the doped semiconductor well 104 can transfer heat from the bipolar transistor structure 170 to the doped semiconductor well 104 and the substrate 102. Therefore, during operation of the bipolar transistor structure 170, the first E / C contact 162 of the bipolar transistor structure 170 can dissipate heat to the substrate 102.

[0036] Figure 6 Alternative implementations of the bipolar transistor structure 170 are shown, for example, in which the first E / C contact 162 is not formed on any portion of the gate structure 130. Here, the gate structure 130 can be located at a greater horizontal distance from the E / C layer 120 than in other implementations, thus the gate structure 130 is not suitable as a marker structure. In this case, masks of different shapes and / or other techniques can still be used to form the first E / C contact 162 to locate suitable coupling to the doped semiconductor well 104. However, in other respects, the bipolar transistor structure 170 can be substantially the same as other implementations, despite the lack of coupling to the gate structure 130. Furthermore, for example, due to the coupling of the first E / C contact 162 to the doped semiconductor well 40, the maximum width W1 of the first E / C contact 162 can be greater than the maximum width W2 of the second E / C contact 162.

[0037] Go to Figure 5 and 7 ,in Figure 5 It shows along Figure 7The cross-section taken by line 5-5 in the plan view is used to discuss other illustrative structural details of the bipolar transistor structure 170. For example... Figure 7 As shown, the base layer 110 can be subdivided into an outer base region 110a and an inner base region 110b adjacent to the outer base region 110a. The inner base region 110b can be highly doped to a lesser degree than the outer base region 110a, for example, to allow for a stronger PN junction to be formed between the base layer 110 and the E / C layer 120, while allowing for stronger electrical coupling through the outer base region 110b to the base layer 110. Furthermore, the inner base region 110b can be horizontally located between the two E / C layers 120, each E / C layer being adjacent to a corresponding sidewall S1, S2 of the base layer 110. In this configuration, the base contact 166 can be located on the outer base region 110a, and additionally or alternatively, can be located on a portion of the inner base region 110b. As discussed elsewhere in this document, a portion of the first E / C contact 162 may be located on the E / C layers 120, 122 and the gate structure 130, while the second E / C contact 164 may only cover the E / C layers 120, 122.

[0038] The embodiments of this disclosure provide various technical and commercial advantages, some of which are discussed herein as examples. Compared to bipolar transistor structures lacking heat dissipation through the first E / C contact 162 to the doped semiconductor well 104 and / or substrate 102, the bipolar transistor structure 170 according to embodiments of this disclosure can provide stronger heat dissipation, thus providing a lower operating temperature. The lower operating temperature, in turn, provides a more robust operating frequency range (including maximum and threshold current frequencies) compared to conventional bipolar transistors. The reduced operating temperature via the bipolar transistor structure 170 having the first E / C contact 162 to the doped semiconductor well 104 also results in reduced current leakage compared to conventional bipolar transistors.

[0039] The methods and structures described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in package form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition described below may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0041] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0042] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A bipolar transistor structure, comprising: A doped semiconductor well located above a semiconductor substrate; The insulating region located on the doped semiconductor well; The base layer located on the insulating region; An emitter / collector E / C layer located on the insulating region and adjacent to the first sidewall of the base layer; as well as The E / C contact to the doped semiconductor well includes: The lower portion, located on the doped semiconductor well, includes a first sidewall adjacent to the insulating region and a second sidewall adjacent to the doped semiconductor well, and The upper part is adjacent to and electrically coupled to the horizontal end of the E / C layer, wherein a portion of the E / C contact is located on the upper surface of the E / C layer.

2. The bipolar transistor structure according to claim 1 further includes: An additional E / C layer is located on the insulating region and is adjacent to the second sidewall of the base layer that is opposite to the first sidewall. as well as Additional E / C contacts to the additional E / C layer, wherein the additional E / C contacts are located above the insulating region and do not include the interface with the doped semiconductor well.

3. The bipolar transistor structure according to claim 1 further includes: A gate structure located on the insulating region and horizontally away from the E / C layer, wherein a portion of the E / C contact is located on the upper surface of the gate structure.

4. The bipolar transistor structure according to claim 1, wherein, The E / C layer and the doped semiconductor well have the same doping type.

5. The bipolar transistor structure according to claim 1, further comprising: A spacer located on the E / C layer and adjacent to the sidewall of the base layer, wherein the spacer is horizontally located between the E / C contact and the base layer.

6. The bipolar transistor structure according to claim 5, wherein, The E / C layer includes: A first E / C material, located on the insulating region and adjacent to the first sidewall of the base layer; and A second E / C material is located on top of the first E / C material. The second E / C material includes a first sidewall adjacent to the spacer and a horizontal end adjacent to and covered by the upper portion of the E / C contact.

7. The bipolar transistor structure according to claim 6, wherein, The E / C layer further includes an E / C silicide located on and adjacent to the horizontal end of the second E / C material, the E / C silicide including a first sidewall adjacent to the spacer and a second sidewall adjacent to the E / C contact, wherein the E / C silicide is vertically located between the upper portion of the second E / C material and the E / C contact.

8. A bipolar transistor structure, comprising: A doped semiconductor well located above a semiconductor substrate; The insulating region located on the doped semiconductor well; The base layer located on the insulating region; A first emitter / collector E / C layer located on the insulating region and adjacent to the first sidewall of the base layer; The first E / C contact to the doped semiconductor well, the first E / C contact comprising: The lower portion, located on the doped semiconductor well, includes a first sidewall adjacent to the insulating region and a second sidewall adjacent to the doped semiconductor well, and The upper part is adjacent to and electrically coupled to the horizontal end of the first E / C layer, wherein a portion of the E / C contact is located on the upper surface of the first E / C layer; The second E / C layer is located on the insulating region and adjacent to the second sidewall of the base layer opposite to the first sidewall; and The second E / C contact of the second E / C layer, wherein the lower surface of the second E / C contact is located on the upper surface of the second E / C layer and above the insulating region.

9. The bipolar transistor structure according to claim 8, further comprising: A gate structure is located on the insulating region and horizontally away from the first E / C layer, wherein a portion of the first E / C contact is located on the upper surface of the gate structure.

10. The bipolar transistor structure according to claim 8, wherein, The first E / C layer, the second E / C layer, and the doped semiconductor well have the same doping type.

11. The bipolar transistor structure according to claim 8, further comprising: A spacer is located on the first E / C layer and the second E / C layer, wherein the spacer is horizontally located between the first E / C contact and the base layer.

12. The bipolar transistor structure according to claim 11, wherein, The first E / C layer includes: A first E / C material, located on the insulating region and adjacent to the first sidewall of the base layer; and A second E / C material is located on top of the first E / C material. The second E / C material includes a first sidewall adjacent to the spacer and a horizontal end adjacent to and covered by the upper portion of the first E / C contact.

13. The bipolar transistor structure according to claim 12, wherein, The first E / C layer further includes an E / C silicide located on and adjacent to the horizontal end of the second E / C material, the E / C silicide including a first sidewall adjacent to the spacer and a second sidewall adjacent to the first E / C contact, wherein the E / C silicide is vertically located between the second E / C material and the upper portion of the E / C contact.

14. The bipolar transistor structure according to claim 8, wherein, The horizontal width of the first E / C contact is greater than the horizontal width of the second E / C contact.

15. A method for forming a bipolar transistor structure, comprising: A doped semiconductor well is formed above the semiconductor substrate; A base layer is formed on the insulating region above the doped semiconductor well; An emitter / collector E / C layer is formed on the insulating region and adjacent to the first sidewall of the base layer; as well as An E / C contact is formed to the doped semiconductor well, the E / C contact comprising: The lower portion, located on the doped semiconductor well, includes a first sidewall adjacent to the insulating region and a second sidewall adjacent to the doped semiconductor well, and The upper part is adjacent to and electrically coupled to the horizontal end of the E / C layer, wherein a portion of the E / C contact is located on the upper surface of the E / C layer.

16. The method of claim 15, further comprising: An additional E / C layer is formed on the insulating region and adjacent to the second sidewall of the base layer opposite to the first sidewall; as well as Additional E / C contacts are formed to the additional E / C layer, wherein the additional E / C contacts are located above the insulating region and do not include the interface with the doped semiconductor well.

17. The method of claim 15, further comprising: A gate structure is formed on the insulating region and horizontally away from the E / C layer, wherein forming the E / C contact includes forming a portion of the E / C contact on the upper surface of the gate structure.

18. The method of claim 15, further comprising: A spacer is formed on the E / C layer and adjacent to the sidewall of the base layer, wherein the spacer is horizontally located between the E / C contact and the base layer.

19. The method according to claim 18, wherein, Forming the E / C layer includes: A first E / C material is formed on the insulating region and adjacent to the first sidewall of the base layer; and A second E / C material is formed on the first E / C material, the second E / C material including a first sidewall adjacent to the spacer and a horizontal end adjacent to and covered by the upper portion of the E / C contact.

20. The method according to claim 19, wherein, Forming the E / C layer further includes: forming an E / C silicide on the second E / C material, the E / C silicide including a first sidewall adjacent to the spacer and a second sidewall adjacent to the E / C contact, wherein the E / C silicide is vertically located between the upper portion of the second E / C material and the E / C contact.

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